Computer Organization and Architecture
Designing for Performance
11th Edition, Global Edition
Chapter 6
Internal Memory
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Figure 6.1
Memory Cell Operation
Control Control
Select Data in Select Sense
Cell Cell
(a) Write (b) Read
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Table 6.1
Semiconductor Memory Types
Write
Memory Type Category Erasure Volatility
Mechanism
Read-write Electrically,
Random-access memory (RAM) Electrically Volatile
memory byte-level
Read-only memory (ROM) Read-only Masks
Not possible
Programmable ROM (PROM) memory
UV light,
Erasable PROM (EPROM)
chip-level
Nonvolatile
Electrically Erasable PROM Read-mostly Electrically, Electrically
(EEPROM) memory byte-level
Electrically,
Flash memory
block-level
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Dynamic RAM (DRAM)
• RAM technology is divided into two technologies:
– Dynamic RAM (DRAM)
– Static RAM (SRAM)
• DRAM
– Made with cells that store data as charge on capacitors
– Presence or absence of charge in a capacitor is interpreted as a
binary 1 or 0
– Requires periodic charge refreshing to maintain data storage
– The term dynamic refers to tendency of the stored charge to leak
away, even with power continuously applied
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Figure 6.2
Typical Memory Cell Structures
dc voltage
Address line T3 T4
T5 C1 C2 T6
Transistor
Storage
capacitor
T1 T2
Bit line Ground
Ground
B
Bit line Address Bit line
B line B
(a) Dynamic RAM (DRAM) cell (b) Static RAM (SRAM) cell
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Figure 6.2 Typical Memory Cell Structures
Static RAM (SRAM)
• Digital device that uses the same logic elements used
in the processor
• Binary values are stored using traditional flip-flop logic
gate configurations
• Will hold its data as long as power is supplied to it
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SRAM versus DRAM SRAM
• Both volatile
– Power must be continuously supplied to the memory to preserve the bit
values
• Dynamic cell
– Simpler to build, smaller
– More dense (smaller cells = more cells per unit area)
DRAM
– Less expensive
– Requires the supporting refresh circuitry
– Tend to be favored for large memory requirements
– Used for main memory
• Static
– Faster
– Used for cache memory (both on and off chip)
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Read Only Memory (ROM)
• Contains a permanent pattern of data that cannot be changed
or added to
• No power source is required to maintain the bit values in
memory
• Data or program is permanently in main memory and never
needs to be loaded from a secondary storage device
• Data is actually wired into the chip as part of the fabrication
process
– Disadvantages of this:
▪ No room for error, if one bit is wrong the whole batch of ROMs must
be thrown out
▪ Data insertion step includes a relatively large fixed cost
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Programmable ROM (PROM)
• Less expensive alternative
• Nonvolatile and may be written into only once
• Writing process is performed electrically and may be
performed by supplier or customer at a time later than
the original chip fabrication
• Special equipment is required for the writing process
• Provides flexibility and convenience
• Attractive for high volume production runs
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Read-Mostly Memory
Flash
EPROM EEPROM
Memory
Electrically erasable
programmable read-only Intermediate between
Erasable programmable
memory EPROM and EEPROM in
read-only memory
both cost and functionality
Can be written into at any
time without erasing prior
contents
Uses an electrical erasing
Erasure process can be
technology, does not
performed repeatedly
Combines the advantage of provide byte-level erasure
non-volatility with the
flexibility of being
updatable in place
More expensive than Microchip is organized so
PROM but it has the that a section of memory
advantage of the multiple More expensive than cells are erased in a single
update capability EPROM action or “flash”
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Figure 6.3
Typical 16-Mbit DRAM (4M 4)
RAS CAS WE OE
Timing and Control
Refresh
Counter MUX
Row Row Memory array
Address De- (2048 2048 4)
A0 coder
A1 Buffer
Data Input
A10 Column Buffer D1
Address D2
Refresh circuitry D3
Buffer Data Output D4
Buffer
Column Decoder
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Figure 6.4
Typical Memory Package Pins and Signals
A19 1 32 Vcc Vcc 1 24 Vss
1M 8 4M 4
A16 2 31 A18 D0 2 23 D3
A15 3 30 A17 D1 3 22 D2
A12 4 29 A14 WE 4 21 CAS
A7 5 28 A13 RAS 5 20 OE
A6 6 27 A8 NC 6 19 A9
A5 7 26 A9 A10 7 24 Pin Dip 18 A8
A4 8 25 A11 A0 8 17 A7
0.6"
A3 9 32 Pin Dip 24 Vpp A1 9 16 A6
A2 10 23 A10 A2 10 15 A5
0.6"
A1 11 22 CE A3 11 14 A4
A0 12 21 D7 Vcc 12 13 Vss
Top View
D0 13 20 D6
D1 14 19 D5
D2 15 18 D4
Vss 16 17 D3
Top View
(a) 8 Mbit EPROM (b) 16 Mbit DRAM
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Figure 6.5
256-KByte Memory Organization
512 words by
Decode 1 of
Memory address 512 bits
512
register (MAR) Chip #1
9 Decode 1 of
512 bit-sense Memory buffer
register (MBR)
1
2
9 3
4
5
6
7
8
512 words by
Decode 1 of
512 bits
512
Chip #8
Decode 1 of
512 bit-sense
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Figure 6.6
1-MB Memory Organization
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Composed of a collection of
DRAM chips
Interleaved Memory
Grouped together to form a
memory bank
Each bank is independently
able to service a memory read
or write request
K banks can service K requests
simultaneously, increasing
memory read or write rates by
a factor of K
If consecutive words of
memory are stored in different
banks, the transfer of a block
of memory is speeded up
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Error Correction
• Hard Failure
– Permanent physical defect
– Memory cell or cells affected cannot reliably store data but become stuck at 0 or
1 or switch erratically between 0 and 1
– Can be caused by:
▪ Harsh environmental abuse
▪ Manufacturing defects
▪ Wear
• Soft Error
– Random, non-destructive event that alters the contents of one or more memory
cells
– No permanent damage to memory
– Can be caused by:
▪ Power supply problems
▪ Alpha particles
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Figure 6.7
Error-Correcting Code Function
Error Signal
Data Out M
Corrector
Data In M M K
f
Memory Compare
K K
f
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Figure 6.8
Hamming Error-Correcting Code
(a) A B (b) A B
1 1 1 0
1 1
1 0 1 0
0
C C
(c) A B (d) A B
1 1 0 1 1 0
1 1
0 0 0 0
0 0
C C
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Table 6.2
Increase in Word Length with Error
Correction
Single-Error Correction/
Single-Error Correction
Double-Error Detection
Data Bits Check Bits % Increase Check Bits % Increase
8 4 50.0 5 62.5
16 5 31.25 6 37.5
32 6 18.75 7 21.875
64 7 10.94 8 12.5
128 8 6.25 9 7.03
256 9 3.52 10 3.91
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Figure 6.9
Layout of Data Bits and Check Bits
Bit
12 11 10 9 8 7 6 5 4 3 2 1
Position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Data
D8 D7 D6 D5 D4 D3 D2 D1
Bit
Check
C8 C4 C2 C1
Bit
Figure 6.9 Layout of Data Bits and Check Bits
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Figure 6.10
Check Bit Calculation
Bit
12 11 10 9 8 7 6 5 4 3 2 1
position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
number
Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check
C8 C4 C2 C1
bit
Word
stored 0 0 1 1 0 1 0 0 1 1 1 1
as
Word
fetched 0 0 1 1 0 1 1 0 1 1 1 1
as
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Check
0 0 0 1
Bit
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Figure 6.11
Hamming SEC-DEC Code
(a) (b) (c)
0 0 0 1 1 0 1
1 1 0
1 0 1 0 1 0
0 0
1 1
(d) (e) (f)
1 0 1 1 0 1 1 0 1
0 0 0
1 0 1 1 1 1
0 0 0
1 1 1
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Advanced DRAM Organization SDRAM
• One of the most critical system bottlenecks when
using high-performance processors is the DDR-DRAM
interface to main internal memory
• The traditional DRAM chip is constrained both by
its internal architecture and by its interface to the
processor’s memory bus
RDRAM
• A number of enhancements to the basic DRAM
architecture have been explored
– The schemes that currently dominate the market
are SDRAM and DDR-DRAM
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Synchronous DRAM (SDRAM)
One of the most widely used forms of DRAM
Exchanges data with the processor synchronized
to an external clock signal and running at the full
speed of the processor/memory bus without
imposing wait states
With synchronous access the DRAM moves data in
and out under control of the system clock
• The processor or other master issues the instruction and
address information which is latched by the DRAM
• The DRAM then responds after a set number of clock
cycles
• Meanwhile the master can safely do other tasks while
the SDRAM is processing
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Figure 6.12
256-Mb Synchronous Dynamic RAM (SDRAM)
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Table 6.3
SDRAM Pin Assignments
A0 to A13 Address inputs
BA0, BA1 Bank address lines
CLK Clock input
CKE Clock enable
CS Chip select
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQ0 to DQ7 Data input/output
DQM Data mask
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Figure 6.13
SDRAM Read Timing (burst length = 4, 𝐂𝐀𝐒
latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3
Figure 6.13 SDRAM Read Timing (Burst Length = 4, CAS latency = 2)
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Double Data Rate SDRAM
(DDR SDRAM)
• Developed by the JEDEC Solid State Technology
Association (Electronic Industries Alliance’s
semiconductor-engineering-standardization body)
• Numerous companies make DDR chips, which are
widely used in desktop computers and servers
• DDR achieves higher data rates in three ways:
– First, the data transfer is synchronized to both the rising and falling edge
of the clock, rather than just the rising edge
– Second, DDR uses higher clock rate on the bus to increase the transfer
rate
– Third, a buffering scheme is used
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Table 6.4
DDR Characteristics
DDR1 DDR2 DDR3 DDR4
Prefetch buffer (bits) 2 4 8 8
Voltage level (V) 2.5 1.8 1.5 1.2
Front side bus data rates (Mbps) 200—400 400—1066 800—2133 2133—4266
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Figure 6.14
DDR Generations
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Embedded DRAM
(eDRAM)
• eDRAM is a DRAM integrated on the same chip or MCM of an
application-specific integrated circuit (ASIC) or microprocessor
• For a number of metrics, eDRAM is intermediate between on-chip
SRAM and off-chip DRAM
– For the same surface area, eDRAM provides a larger size memory than
SRAM but smaller than off-chip DRAM
– eDRAM’s cost-per-bit is higher when compared to equivalent stand-alone
DRAM chips used as external memory, but it has a lower cost-per-bit than
SRAM
– Access time to eDRAM is greater than SRAM but, because of its proximity
and the ability to use wider busses, eDRAM provides faster access than
DRAM
• Fundamentally eDRAMs use the same designs and architectures as
DRAM
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Figure 6.15
IBM z13 Storage Control (SC) Chip Layout
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Figure 6.16
Use of eDRAM in Intel Core Systems
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Flash Memory
• Used both for internal memory and external memory applications
• First introduced in the mid-1980’s
• Is intermediate between EPROM and EEPROM in both cost and
functionality
• Uses an electrical erasing technology like EEPROM
• It is possible to erase just blocks of memory rather than an entire
chip
• Gets its name because the microchip is organized so that a section
of memory cells are erased in a single action
• Does not provide byte-level erasure
• Uses only one transistor per bit so it achieves the high density of
EPROM
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Figure 6.17
Flash Memory Operation
Control Gate
N+ N+
Drain Source
P-substrate
(a) Transistor structure
+ + + + + +
Control Gate Control Gate
Floating Gate – – – – – –
N+ N+ N+ N+
Drain Source Drain Source
P-substrate P-substrate
(b) Flash memory cell in one state (c) Flash memory cell in zero state
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Figure 6.18
Flash Memory Structures
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Figure 6.19
Kiviat Graphs for Flash Memory
Cost per bit Cost per bit
Low Low
File storage File storage
Standby Low Standby Low
use use
power power
Easy Easy
High High
High Hard High Hard
Low Easy Low Easy
High Hard High Hard
Active Code Active Code
Low Low Low Low
power Low execution power Low execution
High High
High High
Read speed Capacity Read speed Capacity
High High
Write speed Write speed
(a) NOR (b) NAND
Figure 6.19 Kiviat Graphs for Flash Memory
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Figure 6.20
Nonvolatile RAM within the Memory Hierarchy
Increasing performance
and endurance
SRAM
STT-RAM
DRAM
PCRAM
NAND FLASH
ReRAM
HARD DISK
Decreasing cost
per bit,
increasing capacity
or density
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Figure 6.21
Nonvolatile RAM Technologies
Bit line Bit line
Perpendicular Perpendicular
Free binary 0 Free binary 1
magnetic layer magnetic layer
layer layer
Interface layer Interface layer
Direction of Direction of
Insulating layer Insulating layer
Interface layer magnetization Interface layer magnetization
Reference Reference
layer Perpendicular layer Perpendicular
magnetic layer Electric magnetic layer Electric
current current
Base electrode Base electrode
(a) STT-RAM
Top electrode Top electrode
Polycrystaline
Polycrystaline Amorphous chalcogenide
chalcogenide chalcogenide
Heater Heater
Insulator Insulator
Bottom electrode Bottom electrode
(b) PCRAM
Top electrode Top electrode
Reduction: Oxidation:
Insulator low resistance Insulator high resistance
Filament Filament
Metal oxide Metal oxide
Bottom electrode Bottom electrode
(c) ReRAM
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Figure 6.21 Nonvolatile RAM Technologies
Summary Internal
Memory
Chapter 6
• Semiconductor main memory • DDR DRAM
– Organization – Synchronous DRAM
– DRAM and SRAM – DDR SDRAM
– Types of ROM
– Chip logic • Flash memory
– Chip packaging – Operation
– Module organization – NOR and NAND flash
– Interleaved memory memory
• Error correction • Newer nonvolatile solid-state
• eDRAM memory technologies
– IBM z13 eDRAM cache – STT-RAM
structure – PCRAM
– Intel core system cache – ReRAM
structure
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