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Stage: Fourth Stage: Name of Student: Aqeel Hisham Afdhal

The document outlines an experiment conducted by Aqeel Hisham Afdhal on a digital frequency synthesizer using a CD4046 PLL and SN74190 counter. It details the objectives, equipment, and procedures for testing both one-digit and two-digit programmable counters, as well as the operation of the frequency synthesizer. The report discusses the results, compares different types of frequency synthesizers, and lists their applications in modern communications.

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0% found this document useful (0 votes)
28 views7 pages

Stage: Fourth Stage: Name of Student: Aqeel Hisham Afdhal

The document outlines an experiment conducted by Aqeel Hisham Afdhal on a digital frequency synthesizer using a CD4046 PLL and SN74190 counter. It details the objectives, equipment, and procedures for testing both one-digit and two-digit programmable counters, as well as the operation of the frequency synthesizer. The report discusses the results, compares different types of frequency synthesizers, and lists their applications in modern communications.

Uploaded by

nwr2500
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Name Of Student : Aqeel Hisham Afdhal

Stage : Fourth Stage


Name of Lab: Electronic and Communication
Name of Experiment: Digital frequency Synthesizer (DFS)
Objective:
To determine the operation of a simple 2-decade frequency
synthesizer, using the CD4046 PLL and SN74190 TTL
programmable counter.

Equipment:
-Oscilloscope.
-Clock generator.
-DC power supply.
-Frequency meter.
-SN74190 synchronous up/down counter.
-CD4046 phase-locked loop.
- Resistors and capacitors.

Procedure:-
1-Part one: One digit programmable counter
1 -We connected the circuit shown in the figure (2).
2. We set the input data DCBA=0001.
3. We applied a clock of 5 volts amplitude and frequency 10 kHz to
the counter then we measured the frequency at pin-13 (or pin-12)
using a frequency meter.
4. We varied the input data according to table below, and we
recorded the output frequency for each input.
2-Part two: Two digits programmable counter
1. We connected the circuit shown in figure (3).
2. We applied a clock of 5 volts amplitude and frequency 10 kHz to
the counter then we measured the frequency at pin-13 (or pin -12)
using a frequency meter.
3. We set the input data of the units and tens counters to the setting
in table (2).
4. For each step of input data, We recorded the output frequency.
3-Part three: Two decade frequency synthesizer
1. We connected the CD4046 PLL as shown in figure (4), short link
pin-3 to pin-4.
2. We applied a clock of 5 volts amplitude to the PLL and measure
𝑓𝑚𝑎𝑥 and 𝑓𝑚𝑖𝑛 of the circuit (lock range).
3. We inserted the two-decade programmable counter (from part
two) between pins (3) and (4) of the PLL as shown in figure (4).
4. We set 𝑓𝑟𝑒𝑓 to 10 kHz, set the units counter to DCBA=0011 and
the tens counter to DCBA=0001 (𝑁 = 13−10 = 3). We measured the
output frequency.
5. We set the units counter to DCBA=1000 and the tens counter to
DCBA=0010 (𝑁 =28−10=18).We measured the output frequency.
6.We repeated 4 and 5 for various values of N ( We take about three
readings).
7. We set N=1,and we measured the output frequency.
8. Set N=26,and we measured the output frequency.
9. From the results of steps 7 and 8, we measured the Nmax,Nmin.
Report:-
1. Discuss your results briefly.
Sol:
The experiment demonstrated the operation of a digital frequency
synthesizer using the CD4046 PLL and SN74190 programmable
counter. Key findings include:
- Part One (One-Digit Counter): The output frequency fo matched
the expected fin/N, where N was set via the 4-bit input (DCBA). For
example, with N=1 (DCBA=0001) and fin=10 Khz fout=10 Khz; for
N=2 (DCBA=0010), fout=5 kHz, validating the divide-by-N
function.
- Part Two (Two-Digit Counter): Cascading two counters allowed
division by larger N (e.g., N=96 for DCBA=1001 and 0110 in
tens/units). Output frequencies (e.g., 10 Khz/96 approx 104.17 Hz)
confirmed correct cascading.
- Part Three (Frequency Synthesizer): The PLL locked fout to
N*fref. For fref=10 Khz and N=13, fo=130 Khz. The lock range
fmin to fmax depended on VCO settings.

2. Elaborate of other types of frequency synthesizers and compare


their performance.
Sol:
- Direct Analog Synthesizers: Use mixers/filters to generate
frequencies. Advantages: Low phase noise, fast switching.
Disadvantages: Complex, bulky, expensive.
- Direct Digital Synthesizers (DDS): Digitally generate waveforms
via lookup tables. Advantages: Fine resolution, fast tuning.
Disadvantages: Limited max frequency, higher spurious signals.
- Fractional-N PLL Synthesizers: Combine PLL with fractional
division for fine resolution. Advantages: Balance between speed and
precision. Disadvantages: Higher complexity, potential fractional
spurs.

Comparison:
- Phase Noise: Analog/DDS excel; PLLs are moderate.
- Resolution: DDS/Fractional-N offer finer steps.
- Speed: Analog/DDS switch faster than PLLs.
- Cost/Size: PLLs/DDS are more compact and affordable than
analog.

3. State some applications of frequency synthesizers in present


communications.
Sol:
- Wireless Communication: Used in smartphones (4G/5G), Wi-Fi,
and Bluetooth for channel selection and modulation.
- Broadcasting: FM/AM radios and TV transmitters rely on
synthesizers for stable carrier frequencies.
- Radar/Satellite Systems: Enable precise frequency agility for target
tracking and data links.
- Test Equipment: Signal generators and spectrum analyzers use
synthesizers for calibrated outputs.
- IoT Devices: Low-power synthesizers support frequency hopping
in sensor networks.

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