Frequency synthesizer circuit

• DDS is characterized by:

High frequency resolution

Fast frequency switching time

But at the same time it also has large spurious and limitation to the output

bandwidth
 Frequency synthesizer circuit
• PLL is characterized by:
Low phase noise
wide output bandwidth
But there is problem between its frequency resolution and frequency switching
time
• Here, we will combine with DDS and PLL to make the best use of their respective
strengths to make up for each other's deficiencies
• Therefore, a better quality spectrum can be obtained under the premise of hop
rate, so as to achieve the indexes required by the frequency synthesizer
 Crystal oscillator
• PLL reference clock is provided by the Temperature Compensated Crystal
Oscillator (TCXO-SMD-053-3.3V-19.2MHz)

• The selection criteria of the crystal oscillator mainly includes the following points:

Output frequency accuracy

Stability of output frequency

Output stability over a wide temperature rang

Hardware circuit of Crystal Oscillator
 Hardware circuit of Crystal Oscillator
• When the radio is turned on, the TCXO is powered up to work, and produce 19.2
MHz frequency into the PLL

• 2R17, 2R18 are dividing resistors at the adjust end of the crystal oscillator

• Adjusting the value of the dividing voltage can help to fine-tune the output
frequency

• The accuracy of the crystal oscillator frequency directly affects the accuracy of
the output frequency of subsequent stage of PLL.
 Phased locked loop (PLL)
• We SI4133 circuit produced by SILICON Company

• Dual band RF synthesizer

RF1 is from 900MHz to 1.8GHz

RF2 is from 750MHz to 1.5GHz

• IF synthesizer

The output frequency range is from 62.5MHz to 1000MHz

Functional Block Diagram
Pin Description
 Functional Description
• SI4133 performs IF and dual-band RF synthesis for wireless communications
applications

• SI4133 includes:

Three VCOs

Three loop filters

Three reference and VCO dividers

 Three phase detectors

• The IC is programmed with a three-wire serial interface

 Setting the VCO Center Frequencies
• The PLLs can adjust the IF and RF output frequencies ±5% of the center frequencies of their VCOs

• Each center frequency is established by the value of an external inductance connected to the respective VCO

• Because the total tank inductance is in the low nH range, the inductance of the package must be considered when
determining the correct external inductance

• The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package
inductance (LPKG)

• Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as
follows:
Setting the VCO Center Frequencies
 Design Example
• Consider that the goal is to synthesize frequencies in a 25 MHz band between 1120 and 1145 MHz
using the Si4133-GT.

• The center frequency 1132.5 MHz

• The PLL can adjust the VCO output frequency ±5% of the center frequency, or ±56.6 MHz of
1132.5 MHz

 From 1076 MHz to 1189 MHz

• The RF2 VCO has a CNOM of 4.8 pF

• A 4.1 nH inductance in parallel with this capacitance yields the required center frequency
 Design Example
• An external inductance of 1.8 nH should be connected between RFLC and RFLD

• This, in addition to 2.3 nH of package inductance, presents the correct total

inductance to the VCO
Schematic design of PPL
 Output Frequencies

• The IF and RF output frequencies are set by programming the R-

and N-Divider registers

• Each PLL has R and N registers so that each can be programmed

independently

• Programming either the R- or N-Divider register for RF1 or RF2

automatically selects the associated output
 Output Frequencies
• Phase detector input signals

XIN pin is divided by R

VCO output frequency divided by N

• The PLL acts to make these frequencies equal

 RF output
• In Register 4,
The decimal number of N frequency tuning word of RF2 is 4003

• In Register 7,
The decimal number of R frequency tuning word of RF2 is 80
N
Fout = × Fref
R

Fout = 𝟗𝟔𝟎.72 MHz,

Pin 10 of PLL is RF output
 IF Output
• In Register 5
The decimal number of N frequency tuning word of IF is 1152

• In Register 8
The decimal number of R frequency tuning word of IF is 24

• IF output
N
fout = × fref
R

fout = 𝟗𝟐𝟏. 𝟔 𝑴𝑯𝒛

 IF Output to DDS clock Reference

• Register 0, the input code controls 1/2 of the output frequency of IF,
The frequency is 921.6MHz / 2 = 460.8MHz.

Pin 23 of the circuit outputs 460.8MHz

After subsequent filtering, the signal is input to DDS, being as DDS reference
clock,
 Output coupling and Matching
• The RF output signal must be AC coupled to its load through a capacitor

• An External inductance between the RFOUT pin and the AC coupling capacitor

An Output matching network to maximize power delivered to the load

Filters the output signal to reduce harmonic distortion

This 2 nH inductance can be realized with a PCB trace

• The IFOUT pin must also be AC coupled to its load through a capacitor
The value of Inductor Match
 RF output to Second local oscillator
• Pin 10 outputs 960.72MHz send to UPB587.

• Frequency division of the input frequency can be achieved for

Twice

Four times

Eight times
 Setting of frequency division

• SW1 is pin5 of the circuit, and SW2 is pin6 of the circuit

• In our design:

The level of pin5 and pin6 is Low

Achieving 8 times frequency division

 Output frequency is 120.090MHz

Interfacing Block diagram
 DDS
• We use AD9954 chip produced by ADI Company

• Coupled Internally with :

High speed, high performance DAC to form a complete

Digitally programmable high frequency synthesizer

Capable of generating 160 MHz

• Fast frequency hopping (0.01 Hz or better)

500 hops/sec
 DDS
• During reception AD9954 DDS chip output local oscillator from 31.66 ~
89.635MHz

The radio adopts Super-Heterodyne architecture

A mixer is used to give an intermediate frequency of 119.635MHz

• During transmission DDS output is 30 ~ 87.975MHz

PIN CONFIGURATION
 DDS Core
• The output frequency 𝑓𝑜𝑢𝑡 of the DDS is a function of:

System clock (𝐒𝐘𝐒𝐂𝐋𝐊 )

Frequency tuning word (FTW)

The capacity of the phase accumulator (𝟐𝟑𝟐 , in our case)

𝐹𝑇𝑊
𝑓𝑜𝑢𝑡 = × 𝑓𝑐𝑙𝑘
232
 DDS Core
• Register 4 of DDS is the register of Frequency Control Word

At 30.025MHz

FTW in decimal number is 835,225,736

• 𝑭𝒐𝒖𝒕 ≈ 𝟖𝟗. 𝟔𝟏 𝑴𝑯𝒛

 DAC Output
• Two complementary outputs provide a combined full-scale output current
(IOUT)
• To reduce the amount of common-mode noise that may be present at the DAC
output, resulting in a better signal-to-noise ratio
• The full-scale current is controlled by means of an external resistor (RSET)
connected between the DAC_RSET pin and the DAC ground pin (Pin 49, the
exposed paddle)
• The full-scale current is proportional to the resistor value by the equation

• 𝑅𝑠𝑒𝑡 = ൗ𝐼𝑜𝑢𝑡 Ω
39.9
Common Mode Noise
 Circuit of Transmitting Channel
• During transmitting, DDS outputs RF signals of 30~87.975MHz

• Pin 20 and Pin 21 output the differential RF signals, which can reduce common
mode interference

• 2T2 is a transformer, and its role is to convert the differential RF signal to a

single-ended RF output signal

• Next stage is filter which is a LC low-pass filter

• Its function is to filter out Higher harmonics

 Transformer coupling
• Common mode rejection
DAC outputs (Iout and IoutB) contain common signals
Clock feed through
AC power supply components
Other spurious signals, then

• Opposing fields will cancel each other

• DC isolation
DAC output and final load
DDS circuit
Low Pass Filter
 TX Channel
• DDS output is a common part for RX and TX

• After filtering, the signal is fed to 2N8, which is a RF switch

PE4230 SPDT High Power MOSFET RF Switch

Cover a broad range of applications from DC to 3.0GHz

Single-pin control input

Small 8-lead MSOP (mini small outline package) package

Pin Descriptions
 Controlling the switch
• The control terminal of 2N8 is Pin 2, TX is control signal

• During RX, TX is at High Level

RFC and RF1 are turned ON
LO signal is output to ?
MIXER

• During TX, TX is at Low Level

RFC and RF2 are turned ON
RF signal is output to 2N7
 Controlling the switch
• During TX, RFC and RF2 are turned ON, the RF signal is output to 2Z2

2Z2 is used during TX and RX

PIN7 is input pin and PIN3 output pin

PIN3 input and PIN7 output is for filter

• The output of 2Z is fed to 2N6

• The RF signal is sent to power pre-amplifier 2N18

 Pre-Amplifier
• Features:

DC-8 GHz

Up to 12.3 dBm output power

Single Voltage supply

Internally matched to 50 ohms

Stable

Low performance variation over temperature

Recommended Application Circuit
 Bias Circuit
• Voltage supply through the resistor R-bias and the RF choke (inductor)

The resistor reduces the effect of device voltage variation

RF choke (inductor) block higher-frequency

• Blocking capacitors are needed at the input and output ports

• bypass capacitor at the connection to the DC supply

Final power amplifier
 Final RF Power Amplifier
• RF signal is fed to the final amplifier 2U1 to get the final amplification of the RF
signal

• Achieve the output of maximum power of not less than 4W.

• Then the output power is radiated through the antenna

• During TX 2V1 is OFF

 Technical specification of 30 - 88 MHz/4W PA
• Frequency Range: 30-88 MHz

• Input / Output impedance: 50 Ω

• Output power:

High power =4 W

Middle power = 2 W

Low power = 0.5 W

Technical specification of 30 - 88 MHz/4W PA
• Power control:

 VG = 3V (Regulator?)

• Power gain flatness ≤ 2dB

• Input /Output VSWR ≤ 1.5:1

• Power voltage:

 Rated +7.2V, keep normal operation in the range of +6V ~ +8V

• Power consumption:

 operating in high output 4W, around 1.75 A

 Band Control
• Band control:
 Band1: 30 MHz ~ 49.975 MHz (BSEL1)

 Band2: 50 MHz ~ 87.975 MHz (BSEL2)

 Receiving circuit

• Double Super Heterodyne architecture which is mainly to achieve:

Conversion

Amplification

Mixing and

Demodulation of the RF signal

 Receiving circuit
• Between the antenna terminal and the radio connection end is 2E2

• 2E1 is the test point

• 2L0 inductor is for matching

• RF enter to switching transistor 2V1

• The device model is MA4P7002F-1072T, and its main role is to isolate the
receiving channel from the transmitting channel
 PIN diode
• The device is a high-pressure PIN diode
 Isolation
 Small insertion

• Anode is grounded through a 10uH inductance

• Cathode is connected to the control signal RE through the same inductance

• During RX, RE = -3V

 2V1 is ON

• During TX, RE = + 20V

 2V1 is OFF
 Anode-Cathode
 Protector and Test signal
• The role of 2V2 transistor is to protect the receiving channel

• When large signals are received by the antenna, 2V2 clipped

• Oscillator:

2B4 is the crystal oscillator 50MHz

2N3 is the power supply control circuit

 Self test
• The control signal of 2N3 is BITE signal of Pin5

• The signal is a self-test signal

• Usually BITE is equal to zero, it is high after the operation of MENU-BITE-YES on the

radio

• After 2B3 is turned on, Pin 4 of 2B4 is powered up to work, and it generate 50MHz RF

signal, which later enters the receiving channel

• At the same time, DDS part of the frequency synthesizer generates a local oscillation

signal of 69.635MHz
 Tunable Filter
• 2Z1 is a first-class electrically tunable filter of receiving channel

• The filter is a band-pass filter with voltage-controlled variable center frequency

• The range of control voltage is about 0.8V ~ 13.6V, and the corresponding center
frequency of the filter is 30 ~ 87.975MHz

• The voltage is supplied by 2N21, which is a high precision, low noise, low voltage
bias wideband operational amplifier

• RxTune-V signal is provided by AD / DA of the baseband unit

Amplification Factor
R1
• Vout = 1 + × Vin
R2

2R35
• Vout = 1 + × Vin
2R33 ||2R34

22K
• Vin = 1 + × Vin
3.16K

Vout = 8 ∗ Vin
 OP-AMP output test data
• The amplifier is to amplify the input voltage for eight times

• Required to output the operating voltage of up to 13.6V

The power supply voltage is + 20V

Non-linear Gain
 Parameter table of voltage amplification of
• Positive and Negative power supply for the Op-Amplifier

 Problem of nonlinear amplification solved

 Tuning Voltage
• After 2Z1 tune to the center frequency the signal goes to 2N4 low noise amplifier

Frequency range Corresponding voltage Frequency variation

30 MHz 0.8V
30 MHz-70 MHz 1MHz/0.2V
70 MHz-80 MHz 1MHz/0.25V
80 MHz-90 MHz 1MHz/0.3V
 LOW NOISE AMPLIFIER
• The INA-02184

 High Gain and Low Noise IF or RF amplification

• Features:

Low Noise Figure

 2.0 dB Typical at 0.5 GHz

High Gain

 31 dB Typical at 0.5 GHz

 26 dB Typical at 1.5 GHz

Typical Biasing Configuration
 Mixer
• Mixer completes the frequency conversion of the signal

• Two signals input to the mixer

Plus / Minus of the fundamental frequency of the signal

Also mix the harmonics of the fundamental frequency signal

• So choosing a good mixer is of significant importance for reducing mixing noise

and insertion loss

• 2N9 is a mixer, and the model number of the device is ADE-1ASK

 ADE-1ASK
• Features:

Low conversion loss is 5.3 dB

Excellent L-R isolation,

Low profile package

Aqueous washable
 Intermediate frequency
• Mixer output:

+/- Frequency signals, and

Harmonic signals

• IF output =119.635MHz is the only useful signal, and others are interference

signals or stray signals

• Filter the IF signals after mixing

 Surface Acoustic Wave Filter (SAW)
• Features:

High design flexibility

Analog/ digital compatible

Excellent selectivity

Frequency range is 30MHz ~ 700MHz

Small impedance error of input and output

Small transmission loss

Specific Parameters of SAW
 TB0196A
• Center frequency is 119.64MHz

• Frequency of bandwidth is 30 kHz

• Insertion loss is 5.5dB

• Size of the smaller package is 7.0 × 5.0

• Impedance of SAW is generally a high resistance

We need matching network at Input and output

 Demodulation Circuit (SA605DK)
• High performance monolithic low-power FM IF system

Mixer/oscillator

Two IF amplifiers

Quadrature detector

RSSI
 SA605DK
• Four main sections:

Mixer section

IF section

Demodulator section

Output section
Pin configuration
 Mixer section
• Three areas in the mixer section

RF signal

LO signal

IF output

• This mixing done by a Gilbert cell four-quadrant multiplier

• The Gilbert cell is a differential amplifier (pins 1 and 2) that drives a balanced
switching cell
 Matching circuit
• RF input impedance is about 4.5kΩ

• Match 50Ω of the SAW filter to 4.5kΩ

• From simulation we chooses the value of

2C24=120pF, 2C180=51pF

2L13=47nH

The capacitance to ground 2C25=0.01

Matching at 119.635 MHz
 Choosing IF filter
• 455 kHz

 Good stability, high sensitivity and gain

 Problems in terms of image frequency

 Suitable for a narrowband FM signal (30 kHz IF bandwidth)

• 10.7 MHz

 Solve the problem of image rejection

 Sensitivity is lower

 Wideband modulated signal (200 kHz IF bandwidth)

 IF Section
• Mixer output is connected to the IF filter

• Second IF is 455 KHz.

• The filter used is ceramic filter

 IF Section
• The first stage filter is 2B2, and the model number is LTM455BU

• Pin 20 is connected to ceramic filter

• After filtering the IF signals enter the IF amplifier

• The filter output is connected to Pin18 of the IF amplifier

 IF Section
• Composed of an IF amplifier and an IF limiter

• IF amplifier:

 Amplify IF signals

 Can not provide a good limit in the wide range of input signal

 The output impedance is 1.0kΩ

 The design requirement of the best loss is 12dB

 Add a 10Ω resistor in series to

Cause additional loss, and meet the requirement of design

 Ceramic Filter Bandwidth
• LTM445CU BW =30KHz

• LTM455CU BW=25kHz

• It inputs to pin 14, and then enters the limiter to amplify the limiting
 IF limiter
• Apply high gain to the IF frequency such that the

Top and Bottom of the waveform are clipped

This helps in reducing AM and noise presented upon reception

 Demodulation
• Demodulation is done by quadrature detector

Separate the baseband signal from the IF signal,

• Detector is composed:

Phase comparator (Inside)

Quadrature circuit (outside)

Pin 11 O/P of limiter and Pin 10 I/P to QD

Reading Assignment: SA605 Quadrature detector

 Output
• Pin 9 Audio output

• Pin 7 RSSI

 Provides a voltage level to determine the quality of the received signal

 Before the design, a number of different amplitude of test signals can be added to the radio
antenna end

 Through the measurement of the data, you can obtain different input amplitudes and different
RSSI output voltage

 Then, it is required to set a threshold

 When the self-test signal puts in to the MCU, the size of the level can be used as a

reference whether the receiving channel is working properly

 Audio Amplification
• Dual operational amplifier circuits:

For amplifying the Audio signal

Send RSSI to the subsequent stage

• Power supply + 5V and -3V

• For maximum amplification of the audio signal

We must also add a bias voltage to Pin 3

• Amplification is determined by the value of 2R30 / 2R27

• The amplified audio signal is fed to 2N13

 Low pass filter (MAX7424)
• 5th-order, low-pass,

• Switched capacitor filters (SCFs)

• Power supply +3V Supply

• Allow frequencies from 1Hz to 45 kHz

• MAX7424 300Hz ~ 3 kHz

Pin Configuration
QUESTIONS