Computer Organization and Architecture

Short Answer Questions:

Unit – I
1. Write the generic Instruction types present in a Computer System.
A. Data Transfer Instructions, data manipulation instructions, Arithmetic instructions,
logical instructions, Control Instructions, Input-output instructions.

2. Stack based CPU Organization uses which instruction format?

A. a) Thress address instruction
b) Two address instruction
c) One address instruction
d) Zero address instruction

3. How much memory the CPU can address with the following instruction format?

A. 4 KB

4. Where the instruction is stored at the time of execution?

A. a) Program Counter
b) Instruction Register
c) Memory
d) Control Unit

5. Define the Instruction cycle?

A. The instruction cycle is the sequence of operations performed by a computer's central
processing unit (CPU). The instruction cycle contains four phases i) Fetch Instruction
ii) Decode Instruction iii) Fetch Operand and iv) Execute Instruction

6. Find the error in the following Register transfer statements.

T0: AR  PC
T1: IR  M[AR], PC  PC – 1
T2: D0,….D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

A. PC  PC + 1

7. X= (A+B) *(C+D) Write the zero-address instruction?

A. PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
 MUL
POP X
8. Which bus carries the data between CPU and memory?
a) Address Bus
b) Data Bus
c) Control Bus
d) System Bus
A. B

9. Differentiate Register indirect and indirect addressing modes

A. In register indirect addressing, the operand's address is located in a register. The
content of the register serves as a pointer or reference to the actual memory address
where the data is stored or retrieved.
In indirect addressing, the operand's address is not directly specified in the instruction.
Instead, the instruction contains a reference to a memory location, and the actual
address is stored in that memory location.

10. Differentiate PC & AR registers.

A. The Program Counter is a special-purpose register in a CPU that keeps track of the
address of the next instruction to be executed.
The AR register is also called as MAR, memory address register, which holds the
address of the memory location that is referred by Control Unit.

11. List the phases of Instruction cycle.

A. There are 4 phases in Instruction Cycle. Those are: i) Fetch Instruction ii) Decode
Instruction iii) Fetch Operand and iv) Execute instruction

12. Which addressing mode uses the contents of a register as an operand?

A. Register Addressing Mode

13. Define computer Organization and computer Architecture.

A. Computer Organization is concerned with the way the Hardware components operate
and the way they are connected together to form the computer system
Computer Architecture is concerned with the structure and behavior of the computer as
seen by the user. It includes the instruction formats, the instruction set and techniques
for addressing modes.

14. If a system follows the below instruction format, how many different opcodes it uses?

A. 64

15. Differentiate Addressing modes and instruction format.

A. Addressing modes are techniques used in computer architectures to specify operands
for instructions. An addressing mode defines how the processor interprets the
 operand's address, enabling the retrieval of data for an operation. Different addressing
modes provide flexibility in how operands are specified.
Instruction format refers to the structure and layout of a machine language instruction.
It defines how an instruction is encoded, specifying fields for the operation code
(opcode), Operands and mode bits.

16. What is an Accumulator?

A. An accumulator is a special-purpose register in a CPU (Central Processing Unit) that is
used for arithmetic and logic operations. It is a register where intermediate results of
calculations are stored. The accumulator is often part of the processor's architecture
and plays a central role in many machine language instructions.

17. Differentiate Hardwired control unit and Microprogrammed control unit.

A. In hardwired control unit, the Control unit is made up of sequential and combinational
circuits to generate the control signals
In Microprogrammed control unit, a control memory on the processor contains
microprograms that activate the necessary control signals.

18. A computer uses a memory unit with 256K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four parts: an
indirect bit, an operation code, a register code part to specify one of 64 registers, and
an address part. How many bits are there in the operation code, the register code
part and the address part?

A. Operation code: 7 bits

Register code part: 6 bits
Address part: 18 bits ( 32 -1-8-6 = 7)
19. If opcode part of an instruction contains 5 bits, then what size of the decoder to be used to
decode the instruction.
A. 5 X 32
UNIT - I
Long Answer Questions:

1. Explain about various special purpose registers of basic computer system

A. In a basic computer architecture, several special purpose registers play specific roles
in facilitating the operation of the CPU and the execution of instructions. These
registers are:
1. Program Counter (PC): The program counter keeps track of the memory address
of the next instruction to be fetched and executed.
2. Instruction Register (IR): The instruction register holds the current instruction
being executed. The CPU used this register to decode and execute the instruction.
3. Memory Address Register (MAR): The memory address register stores the
address of the location in memory that the CPU wants to read from or write to. It
is used during memory operations.
4. Memory Data Register (MDR): The memory data register holds the data that is
either read from memory or is about to be written to memory.
5. Accumulator (AC): The accumulator is used for arithmetic and logic operations. It
stores intermediate results during calculations.
6. Temporary Register (TR): The temporary register will be used as a second
accumulator and is used to store the second operand in binary operations
calculated by ALU.
7. Status Register (Flag Register): The status register contains various flags that
indicate the current state of the CPU, as zero flag (ZF), overflow flag (OF), Sign
flag (SF) etc. These flags are set or reset based on the results of arithmetic and
logic operations.
8. Stack Pointer (SP): The stack pointer points to the top of the stack in memory. It is
used in managing the program stack, especially during subroutine calls and
returns.
9. Input Register (INPR): This register is used during input operation to store the
address of the input device.
10. Output Register (OUTR): This register is used during output operation to store the
address of the output device.

2. Illustrate different types of addressing modes?

A. Addressing modes are techniques used in computer architectures to specify operands
for instructions. The effective Address (EA) is the address, that can be directly used
without modification to access an operand for a computation-type instruction, or as
the target address for a branch-type instruction.
Different types of addressing modes are as follows:
• Implied Addressing Mode
Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
EA = AC, or EA = Stack[SP]
 - Example instructions from Basic Computer
CLA, CME, INP
• Immediate Addressing Mode
Instead of specifying the address of the operand, operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
• Direct Addressing Mode
Instruction specifies the memory address which can be used directly to access the
memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large
physical memory space

EA = IR(addr) (IR(addr): address field of IR)

• Indirect Addressing Mode

The address field of an instruction specifies the address of a memory location that
contains the address of the operand.
- When the abbreviated address is used large physical memory can
be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
EA = M[IR(address)]
• Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
EA = IR(R) (IR(R): Register field of IR)
• Register Indirect Mode
Instruction specifies a register which contains the memory address of the operand.
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
EA = [IR(R)] ([x]: Content of x)
• Autoincrement or Autodecrement Mode
When the address in the register is used to access memory, the value in the register
is incremented or decremented by 1 automatically.
• Relative Addressing Modes
The Address fields of an instruction specifies the part of the address (abbreviated
address) which can be used along with a designated register to calculate the address
of the operand.
 - Address field of the instruction is short
- Large physical memory can be accessed with a small number of address bits
EA = f(IR(address), R), R is sometimes implied

3 different Relative Addressing Modes depending on R;

❖ PC Relative Addressing Mode (R = PC)
EA = PC + IR(address)
❖ Indexed Addressing Mode (R = IX, where IX: Index Register)
EA = IX + IR(address)
❖ Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
EA = BAR + IR(address)

3. Describe the concept of instruction execution using the Fetch-Decode-Execute cycle.

Provide a step-by-step explanation with an example.

A. In Basic Computer, a machine instruction is executed in the following cycle:

i) Fetch an instruction from memory
ii) Decode the instruction
iii) Read the effective address from memory if the instruction has an indirect
address
iv) Execute the instruction
After an instruction is executed, the cycle starts again at step 1, for the next
instruction
The flowchart for instruction cycle is as follows:
 The instruction cycle contains the following steps:
a) Fetch Instruction (FI): i) The program counter holds the address of the next instruction to
be executed. ii) The address of the program counter is sent to memory through memory
address register (MAR). iii) The instruction at that memory address is fetched and loaded
into the instruction register (IR). iv) The program counter is then incremented to point to
the next instruction in sequence.
b) Decode Instruction (DI): i) The instruction in the instruction register (IR) is decoded to
the operation to be performed and the operands involved. ii) The control unit interprets
the opcode to understand the instruction’s meaning and identify the required resources.
c) Execute Instruction (EX): i) The control unit sends signals to the appropriate functional
units within the CPU and other system components to perform the operation specified by
the instruction. ii) If the instruction involving data processing, the arithmetic logic unit
(ALU) carries out the necessary calculation. iii) Data may be fetched from or stored in
memory or registers, depending on the instruction.

4. Evaluate the expression X=A + (B*C) - (D*E) using zero address, one address and
two address instruction formats.
A. i) Two address instructions are:
MUL B, C
MUL D, E
SUB B, D
ADD A, B
STORE X, A
ii) One address instruction is:
LOAD D
MUL E
STORE T
LOAD B
MUL C
SUB T
ADD A
STORE X
iii) Zero address instructions are:
PUSH E
PUSH D
MUL
PUSH C
PUSH B
MUL
SUB
PUSH A
ADD
POP X

5. An instruction is stored at address 300 with its address field at location 301. Address
field has the value 400. Processor R1 contains 200. Evaluate Effective Address for
the following. a. Immediate b. Direct c. Register Indirect d. Relative
e. Auto Increment f. Auto Decrement
A.
S. No. Addressing Mode Effective Address
1. Immediate 301
2. Direct 400
3. Register Indirect 200
4. Relative 702
5. Auto Increment 200
6. Auto Decrement 199

6. For the following memory, the two-word instruction at address 200 and 201 is a
“load to AC” instruction with an address field equal to 500. The first word of the
instruction specifies the operation code and mode, and the second word specifies the
address part. PC has the value 200. The content of the processor register R1 is 400
and the content of an index register XR is 100. What is the content of the AC after
executing the instruction with various addressing modes.

200 Load to AC | Mode

PC = 200 Address = 500
201 Next instruction
R1 = 400
202
450
XR = 100 700
399
400 800

500 900

600 325

702 300
800

A.
Addressing Mode Effective Address Content of AC

1. Direct address 500 800

2. Immediate Operand 201 500
3. Indirect address 800 300
4. Relative address 702 325
5. Indexed address 600 900
6. Register address ---- 400
7. Register Indirect 400 700
 8. Auto increment 400 700
9. Auto decrement 399 450

7. Write a program to evaluate the arithmetic statement:

A-B+C*(D*E-F)
X = --------------------------
G+H*K
a) Using a general register computer with three address instructions
b) Using a general register computer with two address instructions.
c) Using an accumulator type computer with one address instructions.
d) Using a stack organized computer with zero-address operation instructions.

A. Three address instructions:

MUL R1, D, E
SUB R1, R1, F
MUL R1, R1, C
SUB R2, A, B
ADD R1, R1, R2
MUL R2, H, K
ADD R2, R2, G
DIV X, R1, R2

Two address instructions:

MOV R1, D
MUL R1, E
SUB R1, F
MUL R1, C
MOV R2, A
SUB R2, B
ADD R1, R2
MOV R2, H
MUL R2, K
ADD R2, G
DIV R1, R2
MOV X, R1

One address Instructions:

LOAD H
MUL K
ADD G
 STORE T
LOAD D
MUL E
SUB F
MUL C
STORE T1
LOAD A
SUB B
ADD T1
DIV T
STORE X

Zero Address Instructions:

PUSH H
PUSH K
MUL
PUSH G
ADD
PUSH A
PUSH B
PUSH C
PUSH F
PUSH E
PUSH D
MUL
SUB
MUL
SUB
ADD
POP X

8. What is the difference between a direct and indirect address instruction? How many
references to memory are needed for each type of instruction to bring an operand
into a processor register?

A. Direct Addressing:
In direct addressing, the address of the operand (the data) is explicitly stated in the
instruction itself.
The CPU reads the memory address directly from the instruction and accesses the
operand at that memory location.
Example: If an instruction specifies LOAD R1, 5000, the value stored at memory
address 5000 will be loaded into register R1.

Memory References Needed:

 One memory reference is required to fetch the operand from the specified memory
address. The memory address is provided directly in the instruction, so the CPU can
directly access the memory to fetch the operand.

Indirect Addressing:
In indirect addressing, the instruction provides the address of a memory location that
contains the effective address of the operand.
The CPU first reads the address from the specified memory location, then accesses
the operand using this effective address.

Example: If an instruction specifies LOAD R1, (5000), the CPU first goes to memory
address 5000, retrieves the value stored there (say 6000), and then uses 6000 as the
address to fetch the actual operand.

Memory References Needed:

Two memory references are required:
The first memory reference is to retrieve the effective address (stored at the address
given in the instruction).
The second memory reference is to fetch the operand from the effective address
obtained in the first step.

9. List the Basic Computer Instruction Formats. Explain them with Suitable
Examples.
A. 1. Memory reference instruction
2. Register Reference Instructions
3. Input-Output Instructions.
10. Differentiate Memory Reference instructions and Register Reference instructions.
A.
Memory Reference Instructions vs. Register Reference Instructions
Memory reference instructions and register reference instructions are two types of
instructions used in computer systems to perform operations involving data access. The key
difference lies in the location from which the operand is accessed: memory or registers.

Feature Memory Reference Instructions Register Reference Instructions

Instructions that access operands Instructions that access operands
Definition
stored in memory. stored in CPU registers.
The operand is located in the CPU's
Operand The operand is located in the system's
registers (such as general-purpose
Location main memory.
registers).
Feature Memory Reference Instructions Register Reference Instructions
No memory access is required;
These instructions require access to
Memory Access operands are already available in
memory to fetch the operand.
registers.
Generally slower due to the need to Generally faster because registers are
Execution Speed access memory, which has higher part of the CPU and can be accessed
latency. more quickly.
Typical Usually involves memory addresses in Typically, instructions directly
Instruction the instruction (e.g., direct or indirect reference registers by name or number
Format addressing). (e.g., R1, R2).
Typically requires one or more
Memory No memory references are needed, as
memory references to access the
References the operands are in registers.
operand.
- LOAD R1, 5000 (loads data from - MOV R1, R2 (moves data from
Examples
memory address 5000 into register R1) register R2 to register R1)
Used when data is stored in memory Used when data is already in registers
Usage and needs to be brought into the CPU and needs to be processed or
for processing. transferred between registers.
Commonly uses direct, indirect,
Addressing Involves register addressing, where
indexed, and other memory addressing
Modes registers are referenced directly.
modes.
May involve more complex addressing Simpler as they involve only register
Instruction
mechanisms, such as indirect or references without complex memory
Complexity
indexed addressing. access.
Examples of - LOAD, STORE, ADD, SUB - MOV, ADD, SUB (involving
Operations (involving memory locations) registers only)