Computer Organization and Architecture
G11+G12+G13
ASSIGNMENT
ADITYA CHOUHAN
19BCY10085 DR. SUBHASH CHANDRA PATEL
ANSWERS:
Q1) Instruction format describes the internal structures (layout
design) of the bits of an instruction, in terms of its constituent parts.
An Instruction format must include an opcode, and address is
dependent on an availability of particular operands. TYPES OF
INSTRUCTION FORMAT: -
1) Zero Address Instructions –
2) One Address Instructions – This uses a implied ACCUMULATOR
register for data manipulation. One operand is in accumulator and
other is in register or memory location. Implied means that the CPU
already know that one operand is in accumulator so there is no need
to specify it
3) Two Address Instructions – This is common in commercial
computers. Here two address can be specified in the instruction.
Unlike earlier in one address instruction the result was stored in
accumulator here result can be stored at different location rather
than just accumulator, but require a greater number of bits to
represent address.
4) Three Address Instructions – This has three address field to specify
a register or a memory location. Program created are much short in
size but number of bits per instruction increase. These instructions
make creation of program much easier but it does not mean that
program will run much faster because now instruction only contain
more information but each micro-operation (changing content of
register, loading address in address bus etc.) will be performed in one
cycle only.
Q2)
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE
It is ancient computer architecture It is modern computer architecture
based on stored program computer based on Harvard Mark I relay based
concept. model.
Same physical memory address is Separate physical memory address is
used for instructions and data. used for instructions and data.
There is common bus for data and Separate buses are used for
instruction transfer. transferring data and instruction.
Two clock cycles are required to An instruction is executed in a single
execute single instruction. cycle.
It is cheaper in cost. It is costly than van Neumann
architecture.
CPU cannot access instructions and CPU can access instructions and
read/write at the same time. read/write at the same time.
It is used in personal computers and It is used in micro controllers and
small computers. signal processing.
Von Neumann Architecture Diagram:
Harvard Architecture Diagram: -
Q3)
BUILDING DATA PATH AND CONTROL IMPLEMENTATION SCHEME: - Datapath
Components of the processor that perform arithmetic operations and holds
data. Control · Components of the processor that commands the Datapath,
memory, I/O devices according to the instructions of the memory. Building a
Datapath · Elements that process data and addresses in the CPU - Memories,
registers, ALUs. · MIPS Datapath can be built incrementally by considering only a
subset of instructions · 3 main elements are
A memory unit to store instructions of a program and supply instructions given
an address. Needs to provide only read access (once the program is loaded). -
No control signal is needed · PC (Program Counter or Instruction address
register) is a register that holds the address of the current instruction Ø A new
value is written to it every clock cycle. No control signal is required to enable
write Ø Adder to increment the PC to the address of the next instruction · An
ALU permanently wired to do only addition. No extra control signal required
Q4)
a) Zero Address Instruction: - Example: - ADD--->TOS <--- X+Y Here the top two
operands X and Y in the stack are removed from the stack and added. The result
is then again placed at the top of the stack (TOS).
B) One Address Instruction: - Example: - ADD X --->AC <---AC+M[X] i.e the
operand at memory location X is added to the accumulator content and the
result is stored in the accumulator itself. So, there are only see explicit operand
address field (i.e., x) and two implicit operand addresses.
C)Two Address Instruction: - Example: - ADD X, Y --->AC<---M[X]+M[Y] Here X, Y
- explicit Operands OR M[X] <---M[X]+M[Y] OR M[Y]<---M[X]+M[Y]
d) Three Address instructions: - Examples: - ADD R1, C, B ---> R1 <---M[C] +M[B]
I.e., the operands at memory addresses C and B are added and the resultant
sum is stored at or third processor register R1.
Q5)
Addressing Mode: - The addressing mode is the method to specify the
operand of an instruction. The job of a microprocessor is to execute a
set of instructions stored in memory to perform a specific task Types
of Addressing Modes: -
1. Immediate: - With immediate addressing mode, the actual data to
be used as the operand is included in the instruction itself. Let's say
we want to store operand 1 into a register and then add operand 2.
With immediate addressing mode, the data values 1 and 2 would be
part of the instruction itself as shown below. This would be a
relatively fast option since there is no memory access required to get
the operand. The operand, however, is limited to the size of one
word.
2. Direct Addressing- When using direct addressing mode, the address
of the operand is specified in the instruction. The processor will
retrieve the data directly from the address specified in the instruction.
In this figure, the example shows how the instruction tells the
processor where to get the data from in memory. The variable
addr_of_2 is a pointer to the effective address of the operand. There
are no calculations required to retrieve the operand since the
effective address (the address of the operand) is addressed directly.
Like immediate addressing mode, the operand is limited to the size of
1 word (8 or 16 bits).
3. Register Addressing - Register addressing mode indicates the
operand data is stored in the register itself, so the instruction contains
the address of the register.
Q8 - The given instruction can be written as:
A [R0] ← A[R0] + @B
So, 2 memory accesses for fetching operand B, 1 for A[R 0] and 1 for
write back into A[R0] ...
Hence 4 memory accesses are required in total.
⇒ Hence 4 is the correct answer.
Delay slots in pipeline caused due to a branch instruction 2.
Q12)
Q13)
Q15)
Q18)
