Chapter 2

Central Processing Unit

 The part of the computer that performs the bulk of data processing operation is called central processing unit
(CPU) which consists of ALU, control unit and register array.

Register set
Control
Arithmetic logic
unit (ALU)

Fig: Major components of CPU

 CPU performs a variety of functions dictated by the type of instructions that are incorporated in the
computer.
 The register set stores intermediate data used during the execution of the instructions. The arithmetic logic
unit (ALU) performs the required microoperations for executing the instructions. The control (CU) unit
supervises the transfer of information among the registers and instructs the ALU as to which operation to be
performed.

2.1 CPU Organizations

There are three types of CPU organization based on the instruction format
1. Single accumulator organization
 In this type of organization all the operations are performed with an implied accumulator register.
 Basic computer is the good example of single accumulator organization.
 The instruction of this type of organization has an address field
E.g. ADD X AC←AC+M[X] where X is the address of the operand

2. General register organization

 When a large number of processor registers are included in the CPU, it is most efficient to connect
them through a common bus system. The registers communicate with each other not only for direct
data transfer, but also while performing various microoperations. Hence, it is necessary to provide a
common unit that can perform all the arithmetic, logic and shift microoperations in the processor.
 In this type of organization the instruction has two or three address field.
E.g. ADD R1, X R1←R1+M[X]
ADD R1, R2 R1←R1+R2
ADD R1, R2, R3 R1←R2+R3

3. Stack organization
 Last-in, first-out (LIFO) mechanism.
 A stack is a storage device that stores information in such a manner that the item stored last is the
first item retrieved.
 In this type of organization of CPU, all the operations are performed with stack.
 The PUSH and POP instruction only need address field. The operation-type instructions do not need
address field.
E.g. PUSH X TOS←M[X]
POP X M[X] ←TOS
ADD
  This ADD instruction in the stack organization performs addition of two top of the stack element and
stores the result in the top of the stack. First pops two operands from the top of the stack; adds them
and stores the result in the top of the stack.

2.2 Instruction Formats

Mode Op-code Address

Mode bit: It specifies the way the operand or the effective address is determined.
Op-code field: It specifies the operation to be performed.
Address field: It designates a memory address or a processor register.
 The length of instruction varies with the variation of number of address in an address field.

There are four types of instruction on the basis of address field they used.
1. Three-Address Instruction
 Computer with three address instruction can use each address field to specify either processor register or
memory operand.
 Advantage –it minimize the size of program
 Disadvantage –binary coded instruction requires too many bits to specify three address fields
 E.g. ADD R1, A, B / R1M[A]+M[B]

Program to evaluate the following arithmetic statement

X = (A+B) * (C+D) using three address fields instruction
ADD R1, A, B / R1M[A] +M[B]
ADD R2, C, D / R2M[C] +M[D]
MUL X, R1, R2 / M[X]R1*R2

2. Two-Address Instruction
 Computer with two address instruction can use each address field to specify either processer register or
memory operand
 Advantage –it minimize the size of instruction
 Disadvantage –the size of program is relatively larger

Program to evaluate the following arithmetic statement

X = (A+B)*(C+D) using two address field instruction
MOV R1, A / R1M[A]
ADD R1, B / R1R1+M[B]
MOV R2, C / R2M[C]
ADD R2, D / R2R2+M[D]
MUL R1, R2 / R1R1*R2
MOV X, R1 / M[X]R1

3. One-Address Instruction
 Execution of one address field instruction use an implied accumulator register for All data manipulation
 Advantage –relatively small instruction size
 Disadvantage –relatively large program size

Program to evaluate the following arithmetic statement

X = (A+B)*(C+D) using one address field instruction
LOAD A / ACM[A]
ADD B / ACAC +M[B]
 STORE T / M[T]AC
LOAD C / ACM[C]
ADD D / ACAC+M[D]
MUL T / ACAC*M[T]
STORE X / M[X]AC

4. Zero-Address Instruction
 This type of instruction is used in stack organization computer. There is no address field in this type of
instruction except PUSH and POP.
 Advantage –small instruction size
 Disadvantages –large the program size

Program to evaluate the following arithmetic statement

X = (A+B)*(C+D) using zero address field instruction
PUSH A / TOS←M[A]
PUSH B / TOS←M[B]
ADD / TOS← (A+B)
PUSH C / TOS←M[C]
PUSH D / TOS←M[D]
ADD / TOS←(C+D)
MUL / TOS← (A+B)*(C+D)
POP X / M[X] ←TOS

2.3 Addressing Modes

 The method of calculating or finding the effective address of the operand in the instruction is called
addressing mode.
 Effective address means the memory address where the required operand is located.
 The addressing mode specifies the rule interpreting or modifying the address field of the instruction before
the operand is actually referenced.
The various addressing modes are:
i. Implied Mode
ii. Immediate Mode
iii. Register Mode
iv. Register Indirect Mode
v. Auto increment or Auto decrement Mode
vi. Direct Address Mode
vii. Indirect Address Mode
viii. Relative Address Mode
ix. Indexed Addressing Mode
x. Base Register Addressing Mode

Implied Mode
 In this type of addressing mode, operands specified implicitly in the definition of instruction.
 All the register reference instructions that use an accumulator and zero-address instruction in a stack
organized computer are implied mode instruction.
E.g. CMA (complement accumulator)

Immediate Mode
 In this addressing mode, the operand is specified in the instruction itself i.e. there is no any address field to
represent the operand
 Immediate mode instructions are useful for initializing register to a constant value.
 E.g. LD #NBR / ACNBR

Register Mode
 In this type of addressing mode, the operands are in the register which is within the CPU.
E.g. LD R1 / ACR1

Register Indirect Mode

 In this addressing mode, the content of register present in the instruction specifies the effective address of
operand.
 The advantage of this addressing mode is that the address field of the instruction uses fewer bits to select a
register than would have been required to specify a memory address directly.
E.g. LD (R1) / ACM[R1]

Auto Increment or Auto Decrement Mode

 In auto increment mode, the content of CPU register is incremented by 1, which gives the effective address
of the operand in memory.
E.g. LD (R1)+ / ACM[R1], R1R1 + 1
 In auto decrement mode, the content of CPU register is decremented by 1, which gives the effective address
of the operand in memory.
E.g. LD (R1)- / ACM[R1 - 1]

Direct Address Mode

 In this addressing mode, the address field of an instruction gives the effective address of operand.
E.g. LD ADR / ACM[ADR]

Indirect Address Mode

 In this addressing mode, the address field of the instruction gives the address of effective address.
E.g. LD @ADR / ACM[M[ADR]]

Relative Address Mode

 In this addressing mode, the content of program counter is added to the address part of the instruction which
gives the effective address of the operand.
 Assume that the PC is 500 and the address part of instruction is 50. The instruction at location 500 is read
from memory during fetch phase and PC is then incremented by 1. Hence, PC is 501, then effective address
is 501+50=551.
E.g. LD $ADR / ACM[PC + ADR]

Indexed Addressing Mode

 In this addressing mode, the content of index register is added to the address field of the instruction which
gives the effective address of operand.
 This type of addressing mode is useful to access the data array, where the address field of an instruction
gives the start address of data array and content of index register gives how far the operand from the start
address is.
E.g. LD ADR(X) / ACM[ADR + XR]
Base Register Addressing Mode
 In this addressing mode, the content of the base register is added to the address part of the instruction which
gives the effective address of the operand.
E.g. LD ADR(B) / ACM[ADR + BR]

Numerical Example
 Fig: Content of AC after each addressing modes

Fig: Numerical example for addressing modes

2.4 RISC and CISC characteristics

RISC (reduced instruction set computer) characteristics
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations done within the registers of the CPU
 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 The control unit is hardwired rather than micro programmed
 Relatively large number of registers in the processor unit
 Efficient instruction pipeline

CISC (complex instruction set computer) characteristics

 A large number of instructions - typically from 100 to 250 instructions
 Some instructions that perform specialized tasks and are used infrequently
 A large variety of addressing modes – typically from 5 to 20 different modes
 Variable-length instruction format
 Uses memory to load and store instruction and operand as well
 Instructions that manipulate operands in memory
 Microprogrammed Control
The function of the control unit in a digital computer is to initiate sequences of microoperations. The number of
different types of rnicrooperations that are available in a given system is finite. The complexity of the digital
system is derived from the number of sequences of microoperations that are performed. When the control
signals are generated by hardware using conventional logic design techniques, the control unit is said to be
hardwired. Microprogramming is a second alternative for designing the control unit of a digital computer. The
principle of microprogramming is an elegant and systematic method for controlling the microoperation
sequences in a digital computer.
A computer that employs a microprogrammed control unit will have two separate memories: a main memory
and a control memory.

2.5 Control Memory

Control Memory (Control Storage: CS): Storage in the microprogrammed control unit to store the
microprogram.

Control word: It is a string of control variables (0’s and 1’s) occupying a word in control memory.

Microprogram
 Program stored in control memory that generates all the control signals required to execute the instruction
set correctly
 Consists of microinstructions

Microinstruction
 Contains a control word and a sequencing word
 Control Word – contains all the control information required for one clock cycle
 Sequencing Word - Contains information needed to decide the next microinstruction address

Microoperation
 A microinstruction contains one or more microoperations to be completed.

Writable Control Memory (Writable Control Storage: WCS)

 CS whose contents can be modified:
 Microprogram can be changed
 Instruction set can be changed or modified
A computer that employs a microprogrammed control unit will have two separate memories: main memory and
a control memory. The user’s program in main memory consists of machine instructions and data whereas
control memory holds a fixed microprogram that cannot be altered by the user. Each machine instruction
initiates a series of microinstructions in control memory.
The general configuration of a microprogrammed control unit is demonstrated in the following block diagram:

Fig: Microprogrammed control organization

Dynamic Microprogramming
 Computer system whose control unit is implemented with a microprogram in WCS.
 Microprogram can be changed by a systems programmer or a user.

Sequencer: The device or program that generates address of next microinstruction to be executed is called
sequencer. While the microoperations are being executed, the next address is computed in the next address
generator circuit and then transferred into the control address register to read the next microinstruction.

The location of the next microinstruction may be the one next in sequence, or it may be located somewhere else
in the control memory. Typical functions of a microprogram sequencer are incrementing the control address
register by one, loading into the control address register an address from control memory, transferring an
external address, or loading an initial address to start the control operations.

Control Address Register: CAR contains address of microinstruction.

Control Data Register: CDR contains microinstruction read from memory. The microinstruction contains a
control word that specifies one or more microoperations. The data register is sometimes called a pipeline
register.
It allows the execution of the microoperations specified by the control word simultaneously with the generation
of the next microinstruction. This configuration requires a two-phase clock, with one clock applied to the
address register and the other to the data register.

2.6 Address Sequencing

Each computer instruction has its own microprogram routine in control memory to generate the microoperations
that execute the instruction. Process of finding address of next microinstruction to be executed is called address
sequencing. The address sequencing capabilities required in a control memory are:
i. Incrementing of the control address register.
ii. Unconditional branch or conditional branch, depending on status bit conditions.
iii. A mapping process from the bits of the instruction to an address for control memory.
iv. A facility for subroutine call and return.

Following is the block diagram for control memory and the associated hardware needed for selecting the next
microinstruction address.

The diagram shows four different paths from which the control address register (CAR) receives the address. The
incrementer increments the content of the control address register by one, to select the next microinstruction in
sequence. Branching is achieved by specifying the branch address in one of the fields of the microinstruction.
Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to
determine its condition. An external address is transferred into control memory via a mapping logic circuit. The
return address for a subroutine is stored in a special register whose value is then used when the microprogram
wishes to return from the subroutine.

Control address register receives address of next microinstruction from different sources.
 Incrementer simply increments the address by one
 In case of branching, branch address is specified in one of the field of microinstruction.
 In case of subroutine call, return address is stored in the register SBR which is used when returning from
called subroutine.
 Fig: Block diagram of address sequencer.

Conditional Branch
Simplest way of implementing branch logic hardware is to test the specified condition and branch to the
indicated address if condition is met otherwise address resister is simply incremented. If Condition is true,
hardware set the appropriate field of status register to 1. Conditions are tested for O (overflow), N (negative), Z
(zero), C (carry), etc.

Unconditional Branch
Fix the value of one status bit at the input of the multiplexer to 1. So that, branching can always be done.

Mapping
Assuming operation code of 4-bits which can specify 16 (24) distinct instructions. Assume further and control
memory has 128 words, requiring an address of 7-bits. Now we have to map 4-bit operation code into 7-bit
control memory address. Thus, we have to map Op-code of an instruction to the address of the Microinstruction
which is the starting microinstruction of its subroutine in memory.

Direct mapping:
Directly use op-code as address of Control memory
 Address
OP-codes of Instructions 0000 ADD Routine
ADD 0000 AND Routine
0001
LDA Routine
AND 0001 . 0010 STA Routine
LDA 0010 BUN Routine
0011
STA
.
0011 0100 Control
BUN
0100
. Storage

Another approach of direct mapping:

Transfer Op-code bits to use it as an address of control memory. In this mapping, one 0 is placed in the MSB
and two 0s in the LSB as shown in figure:

Fig: mapping from instruction code to

microinstruction address

Extended idea: Mapping function implemented by ROM or PLD (Programmable Logic Device)
Use op-code as address of ROM where address of control memory is stored and then use that address as an
address of control memory. This provides flexibility to add instructions for control memory as the need arises.
OPCODE Mapping memory (PLD) Control Address Register Control Memory

Subroutines
Subroutines are programs that are used by another program to accomplish a particular task. Microinstructions
can be saved by employing subroutines that use common sections of micro code.
Example: the sequence of microoperations needed to generate the effective address is common to all memory
reference instructions. Thus, this sequence could be a subroutine that is called from within many other routines
to execute the effective address computation.
Subroutine register is used to save a return address during a subroutine call which is organized in LIFO (last in,
first out) stack.

2.7 Microprogram Example

Once the configuration of a computer and its microprogrammed control unit is established, the designer’s task is
to generate the microcode for the control memory. This code generation is called microprogramming and is a
process similar to conventional machine language programming.

Computer Configuration
 It consists of two memory units: a main memory for storing instructions and data, and a control memory for
storing the microprogram.
 Fig: computer hardware organization
 Four registers are associated with the processor unit and two with the control unit. The processor registers
are PC, AR, DR and AC.
 The control unit has control address register CAR and subroutine register SBR.
 The transfer of information among the registers in processor is done through multiplexer rather than a
common bus. DR can receive information from AC, PC or memory. AR can receive information from PC
or DR. PC can receive information only from AR.
 The arithmetic, logic and shift unit performs microoperations with data from AC and DR and places the
result in AC. Note that memory receives its address from AR. Input data written to memory come from DR,
and data read from memory can go only to DR.
 The computer instruction format has three fields: a 1-bit field for indirect addressing symbolized by I, a 4-
bit operation code (op-code), and an 11-bit address field. The figure below lists four of the 16 possible
memory reference instructions.
 Fig: computer instructions
 The ADD instruction adds the content of the operand found in the effective address to the content of AC.
 The BRANCH instruction causes a branch to the effective address if the operand in AC is negative. The
program proceeds with the next consecutive instruction if AC is not negative. The AC is negative if its sign
bit is a 1.
 The STORE instruction transfers the content of AC into the memory word specified by the effective
address.
 The EXCHANGE instruction swaps the data between AC and the memory word specified by the effective
address.

Microinstruction Format and Description

We know the computer instruction format (explained in previous chapter) for different set of instruction in main
memory. Similarly, microinstruction in control memory has 20-bit format divided into 4 functional parts as
shown below.

Fig: Microinstruction code format (20 bits)

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

Each microoperation below is defined using resister transfer statements and is assigned a symbol for use in
symbolic microprogram.
Description of CD Description of BR

CD (condition) field consists of two bits representing 4 status bits and BR (branch) field (2-bits) used together
with address field AD, to choose the address of the next microinstruction.
Microinstruction fields (F1, F2, F3)

Here, microoperations are subdivided into three fields of 3-bits each. These 3 bits are used to encode 7 different
microoperations. No more than 3 microoperations can be chosen for a microinstruction, one for each field. If
fewer than 3 microoperations are used, one or more fields will contain 000 for no operation.
E.g. the Fetch Routine

Microinstructions for Fetch routine

Assembly language convention

Binary microprogram