Edition 5.

0
Jan. 2000

Fujitsu PLL Frequency Synthesizer

Evaluation Tool (Version 5.0)

User’s Manual

FUJITSU LIMITED

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CONTENTS
CHAPTER 1 : HARDWARE DESCRIPTION
1.1. INTRODUCTION
1.2. HARDWARE SETUP
1.3. INTERFACE BOARD DESCRIPTION
1.4. INTERFACE BOARD LAYOUT

CHAPTER 2 : SOFTWARE DESCRIPTION

2.1.Windows 95 VERSION
2.1.1.STANDARD SYSNTHESIZER(except for MB15E/FxxSL series)
2.1.1.1. INTRODUCTION
2.1.1.2. USED ENVERNOMENT
2.1.1.3. CONTENTS
2.1.1.4. SET UP
2.1.1.5. HOW TO USE THE PROGRAM
2.1.1.5.1. STARTING THE PROGRAM
2.1.1.5.2. SETTING THE TEST CONDITIONS
2.1.2.5.3. MEASUREMENT
2.1.2.5.4. OTHERS

2.1.2.STANDARD SYSNTHESIZER(MB15E/FxxSL series)

2.1.2.1. INTRODUCTION
2.1.2.2. USED ENVERNOMENT
2.1.2.3. CONTENTS
2.1.2.4. SET UP
2.1.2.5. HOW TO USE THE PROGRAM

CHAPTER 3 : EVALUATION BOARD DESCRIPTION

3.1. OVERVIEW
3.2. EVALUATION BOARD DESCRIPTION
3.2.1.MB1500EB01
3.2.2.MB1500EB01B
3.2.3.MB1500EB02
3.2.4.MB1500EB11
3.2.5.MB1500EB12
3.2.6.MB1500EB13
3.2.7.MB1500EB13B
3.2.8.MB1500EB14
3.2.9.MB1500EB16
3.2.10.MB1500EB16B

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CHAPTER 1. HARDWARE DESCRIPTION

1.1. INTRODUCTION
This evaluation tool is designed to demonstrate the operation of the FUJITSU MB15xx series PLL frequency
synthesizers. It will allow the user to investigate the operation capability of the IC and modify the loop parameters.

1.2. HARDWARE SETUP

This programming tool enables you to control FUJITSU PLL frequency synthesizers via a personal computer.
The personal computer is connected to the interface board via a parallel port. The programming software installed
generates signals to the interface board. Then, the signals are converted into control signals and sent to an IC on
the evaluation board.

Fig.1.1 Hardware constructure (image)

Parallel
Port
Key board PC Interface Evaluation
Board Board

Programm Device
file

1.3. INTERFACE BOARD DESCRIPTION

Fig. 1.2 The interface board top view P/No. : MB1500EB00

Connector

Ground

Delay control switch

Trigger switch
Data output pins
BNC connector
Power source pins

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Connectors
The personal computer and the interface board is connected with a cable. The connector should have 25-pin[
connector for the personal computer’s printer port and 36-pin connector for the interface port.

Trigger Switch
Logical level of the trigger signal can be switched by the trigger switch.
/Q : Active high Q : Active Low

Trigger Trigger

BNC Connector
This connector should be connected to a time interval analyzer. A trigger signal is output through this connector.

Delay Control Switch

The delay time between the trigger signal and the last LE signal outputs can be adjusted by the delay control switch.
Turning the white screw part, the delay time can be adjusted in the range from 5µs to 600µs.

Data Output Pin

Connect one side of the three wire (white, blue and yellow) connector to the data output pins on the interface board.
The other side is connected to the data input pins on the evaluation board.

Power Source Pin

Connect two wire (red and black) connector to the power source pins, and the other side to ground and Vcc
respectively. (Vcc = 3V to 5V (needs to be as same as supply voltage for the IC))

Ground
Connect to ground.

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1.4.INTERFACE BOARD LAYOUT

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CHAPTER 2. SOFTWARE DESCRIPTION

2.1. Windows95 VERSION

2.1.1. STANDARD SYNTHESIZERS (except for MB15E/FxxSL series)

2.1.1.1. INTRODUCTION
This program is designed to demonstrate the operation of the Fujitsu PLL frequency synthesizers. It will allow the
user to investigate the operation capability of the IC and modify the loop parameters.

2.1.1.2. USED ENVERNOMENT

OS: Windows95

2.1.1.3. CONTENTS
FiPLL.exe : Execution file to evaluate PLL series.
fjPLL.ini : Initialization file
fjpll.vxd : Virtual device driver
Applied device
MB15E03, MB15E03L, MB15E05, MB15E05L, MB15E06, MB15E07, MB15E07L, MB1516A, MB1517A, MB15A01,
MB15A02, MB15A16, MB15A17, MB15F02, MB15F02L, MB15F03, MB15F03L, MB15F04. MB15F05, MB15F05L,
MB15B03, MB15U10, MB1551, MB15C03, MB15C03, MB15U32
(The device file has to be housed in the directory "LIB" that locates under the same directory as FjPLL.exe does.
Do not change a name of the directory "LIB".)
Only the device file for MB15U10, name its suffix as DT2.
Name suffix for other device files as DT1.

2.1.1.4. SET UP
This programming tool consists of an interface board, a RF evaluation board and programming software.
1.Connect a parallel cable from the interface board to a printer port of a personal computer.
2.Connect the data input wire (three-wire; blue, yellow and white) from the interface board to
the Data, Clock and LE pins on the evaluation board. (Refer to CHAPTER 1.)
3.Insert the floppy disk into the floppy disk drive on the personal computer.
4.Change a disk drive from the current drive to the floppy disk drive.

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2.1.1.5. HOW TO USE THE PROGRAM

2.1.1.5.1. STARTING THE PROGRAM
Double clicking the FjPLL.exe on the windows explorer, and run the program. When you run the program using a
floppy disk, please release a protector of the floppy disk. If a write protect is valid, the following message is appeared
and the program does not run.

2.1.1.5.2. SETTING THE TEST CONDITIONS

The following window is opened on executing the FjPLL.exe.
1. Clicking exit program button, this program is quit.

2. Click the parallel port button and select a used port.

As is indicated below, you can select only valid parallel port.

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3. Select the device file and then click the button "OPEN".
The below shown parameter setting dialog window is opened. An usable parameter is different by the device file.
Set each parameter.

Only for a programmable parameter, button becomes valid. Click each value. button and input data. If any
of the parameter is not filled in, you can not go to the next step.

FjPLL dialog Parameter setting

OSC Frequency input : ALT + O

* Input a positive value
Frequency Range input : ALT + F
* The value in the column "From" must be a positive number and
less than that in the column "To".
Channel Spacing input : ALT + S
* Input a positive value.
Current Channel input : ALT + C
* Input an integer(0 or more)
Hopping Channel input : ALT + H
* The value in the column "From CH#" must be an integer(0 more)
and less than the value in the column "To CH#".
Number of repeat input : ALT + E
* Input an integer(1 or more)

Note : As regards "Frequency Range" value,

in the case that the display of data and real data differ, please confirm the value.
The value be inputed in conformity with the calculation "[(MxN)+A] x fr(channel spacing)".

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2.1.1.5.3. MEASUREMENT
After test conditions are entered, the measurement can be done by sending the serial data to the testing sample
via the interface board.
Hopping enable progress -- ALT + E
Hopping is repeated at designated time by "Number of repeat"
It can be cancelled using a space key.

Click the button "Output current Ch Data", then the value of the present channel is automatically calculated and
output through the port. Click the button "Output Next Ch Data", then the value of the next channel is automatically
calculated and output through the port.
In the both cases, serial data and an trigger is output.
If the calculation is failed, the PLL Frequency Hopping mode can not be selected. Set parameters correctly.

2.1.1.5.4. OHTERS
When any of OSC Frequency, Frequency Range and Channel Spacing is changed, the PLL Frequency Hopping
mode can not be selected. In that case, click the button "Output Current Ch Data".
There is not a function to save the set data.
Certainly house the device files in the LIB directory that locates in the same directory as FjPLL.exe.
Do not change the name of LIB directory.
Only the device file for MB15U10, name its suffix as DT2. Name suffix for other device files as DT1.
Apply DOS 8.3 type for the name of the device file.

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2.1.2. STANDARD SYNTHESIZERS (MB15E/FxxSL/F7xSP series)

2.1.2.1. INTRODUCTION
This program is designed to demonstrate the operation of PLL(MB15E/FxxSL series). It will allow the user to
investigate the operation capability of the IC and modify the loop parameters.

2.1.2.2. USED ENVERNOMENT

OS: Windows95

2.1.2.3. CONTENTS
FiPLL.exe : Execution file to evaluate PLL series.
MB15ExxSL series -- version. 3.4.1
MB15FxxSL,F7xSP series -- version 3.3.2
fjPLL.ini : Initialization file
fjpll.vxd : Virtual device driver
Applied device
Version 3.4.1 -- MB15E03SL, MB15E05SL, MB15E07SL,
Version 3.3.2 -- MB15F02SL, MB15F03SL, MB15F07SL, MB15F08SL
(The device file has to be housed in the directory "LIB" that locates under the same directory as FjPLL.exe does.
Do not change a name of the directory "LIB".).

2.1.2.4. SET UP
This programming tool consists of an interface board, a RF evaluation board and programming software.
1.Connect a parallel cable from the interface board to a printer port of a personal computer.
2.Connect the data input wire (three-wire; blue, yellow and white) from the interface board to
the Data, Clock and LE pins on the evaluation board. (Refer to CHAPTER 1.)
3.Insert the floppy disk into the floppy disk drive on the personal computer.
4.Change a disk drive from the current drive to the floppy disk drive

2.1.2.4. HOW TO USE THE PROGRAM

It conforms to chapter 2.1.1.5.
The bit configuration differs from MB15E/Fxx and MB15E/FxxL series.

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3.EVALUATION BOARD DESCRIPTION

3.1. OVERVIEW
Some synthesizers are pin compatible or similar pin assignment, so that an evaluation board is used for several
PLLs. The below table shows PLL part number and corresponding evaluation board numbers.

Table.1 P/No. of synthesizers and corresponding Evaluation board.

Part No PKG type Eval. board No. Part No. PKG type Eval. board No.
MB15Axx series MB15Fxx series
MB15A01/ MB15F02/
SSOP-16 MB1500EB01 SSOP-16 MB1500EB13
A02/A03 F02L/F02SL
Bump Chip
MB1516A SSOP-16 MB1500EB01 MB1500EB13B
Carrier-16
MB15A16 SSOP-16 MB1500EB01 MB15F03/ SSOP-16 MB1500EB13
F03L/F03SL
Bump Chip
MB1517A SSOP-16 MB1500EB01 Carrier-16 MB1500EB13B

MB15A17 SSOP-16 MB1500EB01 MB15F06 SSOP-16 MB1500EB13

MB15Bxx series MB15F07SL SSOP-16 MB1500EB13

MB15B01 SSOP-20 MB1500EB11 Bump Chip MB1500EB13B

Carrier-16
MB15B03 SSOP-16 MB1500EB13 MB15F08SL SSOP-16 MB1500EB13
MB15B11/ Bump Chip
SSOP-20 MB1500EB11 MB1500EB13B
B13 Carrier-16
MB15Exx series MB15Uxx series
SSOP-16 MB1500EB01 MB15U10 SSOP-20 MB1500EB12
MB15E03/
E03L/E03SL Bump Chip
MB1500EB01B MB15U32 SSOP-20 MB1500EB14
Carrier-16
SSOP-16 MB1500EB01 MB15Cxxx series
MB15E05/
E05L/E05SL Bump Chip MB15C101
MB1500EB01B SSOP-8 MB1500EB02
Carrier-16
Bump Chip
MB15E06 SSOP-16 MB1500EB01 MB1500EB02B
Carrier-16
MB15E07/ SSOP-16 MB1500EB01 MB15C103 SSOP-8 MB1500EB02
E07L/E07SL
Bump Chip Bump Chip
Carrier-16 MB1500EB01B Carrier-16 MB1500EB02B

MB15F7xSP series
MB15F72SP TSSOP-20 MB1500EB16
/F73SP/
F78SP Bump Chip
Carrier-20 MB1500EB16B

There are some components attached on a board. They are used for every synthesizers in common, and not so much influence
to loop characteristics (except for low pass filter components.) Accordingly, additional components such as VCO, a reference
oscillator, optimized loop filter etc. should be properly arranged by customers according to application.

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3.2. EVALUATION BOARD DESCRIPTION

3.2.1 MB1500EB01

Fig.3.1 MB1500EB01 circuit image

C1
From an
1 16
oscillator OSCin φR

2 15
C’1 C2 OSCout φP
Vp
+ 3 14
-
Vp fout or LD/fout
Vcc
+ 4 13 Vcc
C’2 - Vcc NC or ZC SW
C3
5 12
Do (FC or PS)

6 11
GND LE
LPF from a
7 10
C4 (LD or Xfin) Data connector

R1 8 9
fin Clock

R2 R3
VCO
VCO output

+
VVCO
C5
- C’3

Table.2 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 9 R1 18Ω
2 C2 0.1µF 10 R2 18Ω
3 C3 0.1µF 11 R3 18Ω
4 C4 1000pF 12
5 C5 0.1µF 13
6 C’1 10µF 14
7 C’2 10µF 15
8 C’3 10µF 16

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Fig.3.2 MB1500EB01 board layout

(Top view)

OSCIN SW(PS)
Vcc
13pin

Vp

Connector
direction

VCO

Three pins

Vvco

(Bottom view)

SW(PS)

LE
Data
Clk
LPF

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3.2.2 MB1500EB01B

Fig.3.3 MB1500EB01B circuit image

C1 OSCin
From an
oscillator φR

16 15

1 14
C’1 C2 OSCout φP
Vp 13
+ 2
-
Vp fout or LD/fout
Vcc 12
+ 3 Vcc
C’2 - Vcc NC or ZC
C3 SW
4 11
Do (FC or PS)
5 10
GND LE
LPF from a
6 9
C4 (LD or Xfin) 7 8 Data connector

R1 fin Clock

R2 R3
VCO
VCO output

+
VVCO
C5
- C’3

Table.2 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 9 R1 18Ω
2 C2 0.1µF 10 R2 18Ω
3 C3 0.1µF 11 R3 18Ω
4 C4 1000pF 12
5 C5 0.1µF 13
6 C’1 10µF 14
7 C’2 10µF 15
8 C’3 10µF 16

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Fig.3.4 MB1500EB01B board layout

(Top view)

OSCIN SW(PS)
Vcc
13pin

Vp

Connector
direction

VCO

Three pins

Vvco

(Bottom view)

SW(PS)

LE
Data
Clk

LPF

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3.2.3 MB1500EB02

Fig.3.5 MB1500EB02 circuit image

C3
C’1 C1
Vcc from a TCXO
+ 1 8
- Vcc OSCin
LPF 2 7
Do LD

3 6 Vcc
GND fout
R1 R2
VCO SW
4 5
C2 fin Div
R3

Table.3 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 0.1µF 5 R1 18Ω
2 C2 1000pF 6 R2 18Ω
3 C3 1000pF 7 R3 18Ω
4 C’1 10µF

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Fig.3.6 MB1500EB02 board layout

(Top view)
Vcc

LD
Div
VCO

Vvco

(Bottom view)

LPF

SW

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3.2.4 MB1500EB11

Fig.3.7 MB1500EB11 circuit image

1 20
C1 GND Clock
From an from a
2 19
oscillator OSCin Data connector
VCO output
VCO output
3 18
C2 OSCout LE C7
4 17
fin1 fin2
Vcc 5 16 Vcc
Vcc1 Vcc2 C6
C3
6 15
fr fp VCO
VCO
7 14
VVCO
VVCO LD1 LD2
C4 C5
8 13
(BSC1 or Vp1) (BSC2 or Vp2)
9 12
LPF Do1 Do2 LPF

10 11
BS1 BS2

Table.4 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF
2 C2 1000pF
3 C3 0.1µF
4 C4 0.1µF
5 C5 0.1µF
6 C6 0.1µF
7 C7 1000pF

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Fig.3.8 MB1500EB11 board layout

(Top view) Connector
direction

Three pins

Vvco

VCO

Vcc1

Vvco Vcc2

LD Do fr LD Do fr
1 2

(Bottom view)

LE Clk

LPF LPF

fr Do LD fr Do LD

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3.2.5 MB1500EB12

Fig.3.9 circuit image SW4 SW2 R10

R9
R8
R1 R7
1 20
SW3
VDD P1/fp1 ISET
R6
2 19 VDD VCO output
C1 R2 P2/fp2 P0/LD
Vp
VCO LPF 3 18
Do1 Vp C9 SW5
VDD
4 17 LPF VCO
C2 VVCO VDD
VDD1 Do2
C3 VVCO
SW1 5 16
C8
C4 PS AGND C7
6 15
R3 fin1 fin2 R5
7 14 VDD
C5 DGND VDD2 C6
From an R4
8 13
oscillator
OSCin LE
from a
VDD 9 12
P3/fr2 Data connector
10 11
OSCout Clock

Table.5 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 0.1µF 11 R2 2.2kΩ
2 C2 0.1µF 12 R3 51Ω
3 C3 0.1µF 13 R4 51Ω
4 C4 1000pF 14 R5 51Ω
5 C5 1000pF 15 R6 2.2kΩ
6 C6 0.1µF 16 R7 62kΩ
7 C7 1000pF 17 R8 15kΩ
8 C8 0.1µF 18 R9 12kΩ
9 C9 0.1µF 19 R10 5.1kΩ
10 R1 2.2kΩ

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Fig.3.10 MB1500EB12 board layout

(Top view)
SW2 SW3

VDD
LD

SW4 SW5
Vp
SW(PS)

Vvco

Do1 Do2
VCO
VCO
LPF LPF
Vvco Connector
direction
VDD
LE Three pins
Clk

(Bottom view)

SW(PS)

Clk
LE

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3.2.6 MB1500EB13

Fig.3.11 MB1500EB13 circuit image

1 16
C1 GNDRF Clock
From an from a
VCO output 2 15
oscillator connector VCO output
OSCin Data
R1
3 14
R3 GNDIF LE
C2 R9
R4 R8
4 13
R2 C8 R6
R5 fin1 finRF R7
Vcc
Vcc 5 12
VCO + +
C’1 -
VccIF VccRF C6 C’4 VCO
-
VVCO C3 6 11
+ C5 VVCO
LD/fout XfinRF +
- -
SW 7 10 SW
C4 C’2 C’3 C7
PSIF PSRF
LPF 8 9 LPF
DoIF DORF

Table.6 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 0.1µF 16 R4 18Ω
5 C5 1000pF 17 R5 18Ω
6 C6 0.1µF 18 R6 51Ω
7 C7 0.1µF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C’1 10µF 21 R9 18Ω
10 C’2 10µF
11 C’3 10µF
12 C’4 10µF

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Fig.3.12 MB1500EB13 board layout

(Top view) Connector

direction
IF RF
LE
CK

Three pins
Vvco

VCO
VCO

Vvco

VCC VCC
SW Do Do SW
(PS) (PS)

(Bottom view)

LE Clk

LPF LPF

SW(PS)

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3.2.7 MB1500EB13B

Fig.3.13 MB1500EB13B circuit image

GNDRF Clock

C1 1 16
From an from a
VCO output 15
oscillator OSCin 2 Data connector
R1
3 14
R3 GNDIF LE
C2 R9
R4 R8
4 13
R2 fin1 finRF C8 R6
R5 R7
Vcc
Vcc 5 12
+ +
VCO
C’1 VccIF VccRF C6 VCO
VCO
- - C’4
VVCO C3 6 11
+ LD/fout XfinRF C5 VVCO
+
- -
SW 7 10 SW
C4 C’2 PSIF PSRF C’3 C7

8 9
DoIF DORF
LPF
LPF

Table.7Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 0.1µF 16 R4 18Ω
5 C5 1000pF 17 R5 18Ω
6 C6 0.1µF 18 R6 51Ω
7 C7 0.1µF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C’1 10µF 21 R9 18Ω
10 C’2 10µF
11 C’3 10µF
12 C’4 10µF

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Fig.3.14 MB1500EB13B board layout

(Top view) Connector

direction

LE
Clk

Three pins
Vvco

VCO
VCO

Vvco

Vcc Vcc
Do Do

(Bottom view)

Clk LE

LPF LPF

SW(PS) SW(PS)

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3.2.8 MB1500EB14

Fig.3.15 MB1500EB14 circuit image

1 20 Vcc
C1 VccRF VccIF C8
2 19
C2 VpRF VpIF C9
LPF 18 LPF
DORF 3 DOIF
4 17
VCO GNDRF GNDIF C10

C3 R2 5 16 VVCO
R1 C4 finRF finIF
C11 R7
R3 VCO
R4 6 15
C5 XfinRF XfinIF
C12
VVCO R8
7 14
GNDRF GNDRF
R9 R10
From an
8 13
VCO output LE
oscillator R5 C6 OSCin
VCO output
9 12 from a
GNDRF Data
11 connector
10
R6 LD/fout Clock
C7

Table.8 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 0.1µF 13 R1 51Ω
2 C2 0.1µF 14 R2 18Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 1.0nF 16 R4 18Ω
5 C5 1000pF 17 R5 51Ω
6 C6 1.0nF 18 R6 2KΩ
7 C7 0.1µF 19 R7 51Ω
8 C8 0.1µF 20 R8 18Ω
9 C9 0.1µF 21 R9 18Ω
10 C10 0.1µF 22 R10 18Ω
11 C11 1.0nF
12 C12 1000pF

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Fig.3.16 MB1500EB14 board layout

(Top view)
Vp Vcc Vcc Vp
Vvco

Vvco

VCO VCO

Clk LE

(Bottom view)

LPF LPF

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3.2.9 MB1500EB16

Fig.3.17 MB1500EB16 circuit image

From an oscillator
output
1 20
Clock
R6 C9 OSCIN
2 19 from a
GND Data
R7 R9
18 connector
3
R1 C1 finIF LE
R8
4 17
C2 XfinIF finRF R12 R10 output
C8 R2
5 16 R11
GNDIF XfinRF
C7
VVCO 6 15
C3 VccIF GNDRF
VCO
7 14 VCO
SW PSIF VccRF
C10 C6 C11
8 13
C4 VpIF PSRF SW LPF
VVCO
LPF 9 12
DoIF VpRF
C5
10 11
LD/fout DoRF

Table.9 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 10µF 15 R3 18Ω
4 C4 10µF 16 R4 18Ω
5 C5 10µF 17 R5 18Ω
6 C6 10µF 18 R6 51Ω
7 C7 1000pF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C9 1000pF 21 R9 18Ω
10 C10 10µF 22 R10 18Ω
11 C11 10µF 23 R11 18Ω
24 R12 18Ω

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Fig.3.18 MB1500EB16board layout

(Top view)

Data
CLK

LE
OSCin

VCO

RF Block

LPF

VccIF VpIF LD/fout VpRF VccRF

(Bottom view)

LPF

IF Block

VCO

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3.2.10 MB1500EB16B

Fig.3.19 MB1500EB16B circuit image From

an oscillator
from a
connector
output
R6

C9
R7 GND OSCIN Clock Data
C1
1 20 19 18 17 16
R9 R1 finIF LE
C8
R8 output
2 15 finRF
C2 XfinIF R2 R12 R10
VVCO
3 14 R11
VCO GNDIF XfinRF C7

C10 4 13
C3 VccIF GNDRF
VCO C11
5 12
LPF SW PSIF VccRF C6
VVCO
6 7 8 9 10 11
C4 VpIF PSRF SW LPF
DoIF LD/fout DoRF VpRF C5

Table.10 Components list on the evaluation board

No. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 10µF 15 R3 18Ω
4 C4 10µF 16 R4 18Ω
5 C5 10µF 17 R5 18Ω
6 C6 10µF 18 R6 51Ω
7 C7 1000pF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C9 1000pF 21 R9 18Ω
10 C10 10µF 22 R10 18Ω
11 C11 10µF 23 R11 18Ω
24 R12 18Ω

30
 PLL Evaluation tool
(ver5.0)

Fig.3.20 MB1500EB16board layout

(Top view)

Data
CLK

LE
OSCin

RF Block

VCO

LPF

VccIF VpIF LD/fout VpRF VccRF

(Bottom view)

IF Block
VCO

LPF

31