a DC-Coupled Demodulating

120 MHz Logarithmic Amplifier

AD640
FEATURES signal output at +50 dB (referred to input) is provided to operate
Complete, Fully Calibrated Monolithic System AD640s in cascade.
Five Stages, Each Having 10 dB Gain, 350 MHz BW The logarithmic response is absolutely calibrated to within ±1 dB
Direct Coupled Fully Differential Signal Path for dc or square wave inputs from ± 0.75 mV to ± 200 mV, with
Logarithmic Slope, Intercept and AC Response are an intercept (logarithmic offset) at 1 mV dc. An integral X10
Stable Over Full Military Temperature Range attenuator provides an alternative input range of ± 7.5 mV to
Dual Polarity Current Outputs Scaled 1 mA/Decade ± 2 V dc. Scaling is also guaranteed for sinusoidal inputs.
Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.)
The AD640B is specified for the industrial temperature range of
Low Power Operation (Typically 220 mW at ⴞ5 V)
–40°C to +85°C and the AD640T, available processed to MIL-
Low Cost Plastic Packages Also Available
STD-883B, for the military range of –55°C to +125°C. Both are
APPLICATIONS available in 20-lead side-brazed ceramic DIPs or leadless chip
Radar, Sonar, Ultrasonic and Audio Systems carriers (LCC). The AD640J is specified for the commercial
Precision Instrumentation from DC to 120 MHz temperature range of 0°C to +70°C, and is available in both
Power Measurement with Absolute Calibration 20-lead plastic DIP (N) and PLCC (P) packages.
Wide Range High Accuracy Signal Compression
Alternative to Discrete and Hybrid IF Strips This device is now available to Standard Military Drawing
Replaces Several Discrete Log Amp ICs (DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
1. Absolute calibration of a wideband logarithmic amplifier is
The AD640 is a complete monolithic logarithmic amplifier. A single
unique. The AD640 is a high accuracy measurement device,
AD640 provides up to 50 dB of dynamic range for frequencies
not simply a logarithmic building block.
from dc to 120 MHz. Two AD640s in cascade can provide up to
95 dB of dynamic range at reduced bandwidth. The AD640 uses a 2. Advanced design results in unprecedented stability over the
successive detection scheme to provide an output current propor- full military temperature range.
tional to the logarithm of the input voltage. It is laser calibrated to 3. The fully differential signal path greatly reduces the risk of
close tolerances and maintains high accuracy over the full military instability due to inadequate power supply decoupling and
temperature range using supply voltages from ±4.5 V to ± 7.5 V. shared ground connections, a serious problem with com-
monly used unbalanced designs.
The AD640 comprises five cascaded dc-coupled amplifier/limiter
stages, each having a small signal voltage gain of 10 dB and a –3 dB 4. Differential interfaces also ensure that the appropriate ground
bandwidth of 350 MHz. Each stage has an associated full-wave connection can be chosen for each signal port. They further
detector, whose output current depends on the absolute value of its increase versatility and simplify applications. The signal input
input voltage. The five outputs are summed to provide the video impedance is ~500 kΩ in shunt with ~2 pF.
output (when low-pass filtered) scaled at 1 mA per decade (50 µA 5. The dc-coupled signal path eliminates the need for numerous
per dB). On chip resistors can be used to convert this output cur- interstage coupling capacitors and simplifies logarithmic
rent to a voltage with several convenient slope options. A balanced conversion of subsonic signals.
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
RG1 1kV RG0 1kV RG2 LOG OUT LOG COM
17 16 15 14 13 INTERCEPT POSITIONING BIAS 12 +VS
COM 18

ATN OUT 19 FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE

DETECTOR DETECTOR DETECTOR DETECTOR DETECTOR
SIG +IN 20 11 SIG +OUT
10dB 10dB 10dB 10dB 10dB
SIG –IN 1 10 SIG –OUT

ATN LO 2 AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER

27V
ATN COM 3 9 BL2
30V 270V
ATN COM 4 5 6 GAIN BIAS REGULATOR 7 SLOPE BIAS REGULATOR 8 ITC
ATN IN BL1 –VS

REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999-2016
AD640–SPECIFICATIONS
DC SPECIFICATIONS (V = ⴞ5 V, T = +25ⴗC, unless otherwise noted)
S A

Model AD640J AD640B AD640T

Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units

TRANSFER FUNCTION 1
IOUT = IY LOG |V IN/VX | for VIN = ± 0.75 mV to ± 200 mV dc

SIGNAL INPUTS (Pins 1, 20)

Input Resistance Differential 500 500 500 kΩ
Input Offset Voltage Differential 50 500 50 200 50 200 µV
vs. Temperature 0.8 0.8 0.8 µV/°C
Over Temperature T MIN to TMAX 300 µV
vs. Supply 2 2 2 µV/V
Input Bias Current 7 25 7 25 7 25 µA
Input Bias Offset 1 1 1 µA
Common-Mode Range –2 +0.3 –2 +0.3 –2 +0.3 V

INPUT ATTENUATOR
(Pins 2, 3, 4, 5 and 19)
Attenuation2 Pin 5 to Pin 19 20 20 20 dB
Input Resistance Pins 5 to 3/4 300 300 300 Ω

SIGNAL OUTPUT (Pins 10, 11)

Small Signal Gain 3 50 50 50 dB
Peak Differential Output 4 ±180 ± 180 ± 180 mV
Output Resistance Either Pin to COM 75 75 75 Ω
Quiescent Output Voltage Either Pin to COM –90 –90 –90 mV

LOGARITHMIC OUTPUT 5 (Pin 14)

Voltage Compliance Range –0.3 +V S –1 –0.3 +V S –1 –0.3 VS –1 V
Slope Current, IY 0.95 1.00 1.05 0.98 1.00 1.02 0.98 1.00 1.02 mA
Accuracy vs. Temperature 0.002 0.002 0.002 %/°C
TMIN to TMAX 0.96 1.02 mA
Accuracy vs. Supply +VS = 4.5 V to 7.5 V 0.08 1.0 0.08 0.4 0.08 0.4 %/V
Intercept Voltage 6, V X 0.85 0.99 1.15 0.93 0.99 1.05 0.93 0.99 1.05 mV
vs. Temperature 0.5 0.5 0.5 µV/°C
Over Temperature TMIN to TMAX 0.90 1.10 mV
vs. Supply ±VS = 4.5 V to 7.5 V 2 2 2 µV/V
Logarithmic Offset
(Alt. Definition of VX ) –61.5 –60.0 –58.7 –60.5 –60.0 –59.5 –60.5 –60.0 –59.5 dBV
vs. Temperature 0.004 0.004 0.004 dB/°C
Over Temperature TMIN to TMAX –60.9 –59.1 dB
vs. Supply ±VS = 4.5 V to 7.5 V 0.017 0.017 0.017 dB/V
Intercept Voltage Using Attenuator 8.25 10.0 11.75 9.0 10.0 11.0 9.0 10.0 11.0 mV
Zero Signal Output Current 7 –0.2 –0.2 –0.2 mA
ITC Disabled Pin 8 to COM –0.27 –0.27 –0.27 mA
Maximum Output Current 2.3 2.3 2.3 mA

APPLICATIONS RESISTORS
(Pins 15, 16, 17) 1.000 0.995 1.000 1.005 0.995 1.000 1.005 kΩ

DC LINEARITY
VIN ±1 mV to ± 100 mV 0.35 1.2 0.35 0.6 0.35 0.6 dB

TOTAL ABSOLUTE DC
ACCURACY
VIN = ± 1 mV to ±100 mV8 0.55 2 0.55 1.2 0.55 1.2 dB
Over Temperature T MIN to TMAX 3 2.0 2.0 dB
Over Supply Range ±VS = 4.5 V to 7.5 V 2 1.5 1.5 dB
VIN = ± 0.75 mV to ±200 mV 1.0 3 1.0 2.0 1.0 2.0 dB
Using Attenuator
VIN = ± 10 mV to ± 1 V 0.4 2.5 0.4 1.5 0.4 1.5 dB
Over Temperature T MIN to TMAX 0.6 3 0.6 2.2 0.6 2.2 dB
VIN = ± 7.5 mV to 2 V 1.2 3.5 1.2 2.5 1.2 2.5 dB

POWER REQUIREMENTS
Voltage Supply Range ⴞ4.5 ⴞ7.5 ⴞ4.5 ⴞ7.5 ⴞ4.5 ⴞ7.5 V
Quiescent Current9
+VS (Pin 12) TMIN to TMAX 9 15 9 15 9 15 mA
–VS (Pin 7) TMIN to TMAX 35 60 35 60 35 60 mA

–2– REV. D
 AD640
AC SPECIFICATIONS (V S = ⴞ5 V, TA = +25ⴗC, unless otherwise noted)
Model AD640J AD640B AD640T
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance Either Pin to COM 2 2 2 pF
Noise Spectral Density 1 kHz to 10 MHz 2 2 2 nV/√Hz
Tangential Sensitivity BW = 100 MHz –72 –72 –72 dBm
3 dB BANDWIDTH
Each Stage 350 350 350 MHz
All Five Stages Pins 1 & 20 to 10 & 11 145 145 145 MHz
LOGARITHMIC OUTPUTS 5
Slope Current, IY
f< = 1 MHz 0.96 1.0 1.04 0.98 1.0 1.02 0.98 1.0 1.02 mA
f = 30 MHz 0.88 0.94 1.00 0.91 0.94 0.97 0.91 0.94 0.97 mA
f = 60 MHz 0.82 0.90 0.98 0.86 0.90 0.94 0.86 0.90 0.94 mA
f = 90 MHz 0.88 0.88 0.88 mA
f = 120 MHz 0.85 0.85 0.85 mA
Intercept, Dual AD640s 10, 11
f< = 1 MHz –90.6 –88.6 –86.6 –90.0 –88.6 –87.6 –90.0 –88.6 –87.6 dBm
f = 30 MHz –87.6 –87.6 –87.6 dBm
f = 60 MHz –86.3 –86.3 –86.3 dBm
f = 90 MHz –83.9 –83.9 –83.9 dBm
f = 120 MHz –80.3 –80.3 –80.3 dBm
AC LINEARITY
–40 dBm to –2 dBm12 f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB
–35 dBm to –10 dBm 12 f = 1 MHz 0.25 1.0 0.25 0.5 0.25 0.5 dB
–75 dBm to 0 dBm 10 f = 1 MHz 0.75 3.0 0.75 1.5 0.75 1.5 dB
–70 dBm to –10 dBm 10 f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB
–75 dBm to +15 dBm13 f = 10 kHz 0.5 3.0 0.5 1.5 0.5 1.5 dB
PACKAGE OPTION
20-Lead Ceramic SBDIP Package (D) AD640TD
20-Terminal Ceramic LCC (E) AD640BE AD640TE
20-Lead Plastic DIP Package (N) AD640]N
20-Lead Plastic Leaded Chip Carrier (P) AD640JP AD640BP
NUMBER OF TRANSISTORS 155 155 155
NOTES
1
Logarithms to base 10 are used throughout. The response is independent of the sign of V IN.
2
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C.
3
Overall gain is trimmed using a ± 200 µV square wave at 2 kHz, corrected for the onset of compression.
4
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5
Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.
6
The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG 10 (VX /1 V).
7
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8
Operating in circuit of Figure 24 using ± 0.1% accurate values for RLA and R LB. Includes slope and nonlinearity errors. Input offset errors also included for
VIN >3 mV dc, and over the full input range in ac applications.
9
Essentially independent of supply voltages.
10
Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
11
For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12
Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
13
Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.

THERMAL CHARACTERISTICS

␪JC (ⴗC/W) ␪JA (ⴗC/W)

20-Lead Ceramic SBDIP Package (D-20) 25 85
20-Terminal Ceramic LCC (E-20-1) 25 85
20-Lead Plastic DIP Package (N-20) 24 61
20-Lead Plastic Leaded Chip Carrier (P-20) 28 75

REV. D –3–
AD640
(continued from page 1) ABSOLUTE MAXIMUM RATINGS*
6. The low input offset voltage of 50 µV (200 µV max) ensures Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7.5 V
good accuracy for low level dc inputs. Input Voltage (Pin 1 or Pin 20 to COM) . . . . –3 V to +300 mV
7. Thermal recovery “tails,” which can obscure the response Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . . ± 4 V
when a small signal immediately follows a high level input, Storage Temperature Range D, E . . . . . . . . . –65°C to +150°C
have been minimized by special attention to design details. Storage Temperature Range N, P . . . . . . . . . –65°C to +125°C
Ambient Temperature Range, Rated Performance
8. The noise spectral density of 2 nV/√Hz results in a noise floor of
Industrial, AD640B . . . . . . . . . . . . . . . . . . . –40°C to +85°C
~23 µV rms (–80 dBm) at a bandwidth of 100 MHz. The dy-
Military, AD640T . . . . . . . . . . . . . . . . . . . –55°C to +125°C
namic range using cascaded AD640s can be extended to 95 dB
Commercial, AD640J . . . . . . . . . . . . . . . . . . . 0°C to +70°C
by the inclusion of a simple filter between the two devices.
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
CHIP DIMENSIONS AND device at these or any other conditions above those indicated in the operational
BONDING DIAGRAM section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Dimensions shown in inches and (mm).

ESD CAUTION

CONNECTION DIAGRAMS
20-Lead Ceramic SBDIP (D) Package 20-Lead PLCC (P) Package 20-Terminal Ceramic LCC (E) Package
20-Lead Plastic DIP (N) Package
ATN COM
ATN COM

ATN OUT
ATN OUT

ATN LO

SIG +IN
SIG –IN
ATN LO

SIG +IN
SIG –IN

SIG –IN 1 20 SIG +IN

ATN LO 2 19 ATN OUT 3 2 1 20 19

3 2 1 20 19
ATN COM 3 18 CKT COM
ATN COM 4 18 CKT COM
PIN 1 ATN COM 4 18 CKT COM
ATN COM 4 17 RG1 IDENTIFIER
ATN IN 5 17 RG1 ATN IN 5 17 RG1
ATN IN 5 AD640 16 RG0 AD640 AD640
BL1 6 16 RG0 BL1 6 16 RG0
TOP VIEW 15 RG2 TOP VIEW
BL1 6 TOP VIEW
(Not to Scale) –VS 7 15 RG2 –VS 7 (Not to Scale) 15 RG2
(Not to Scale)
–VS 7 14 LOG OUT ITC 8 14 LOG OUT
ITC 8 14 LOG OUT
ITC 8 13 LOG COM 9 10 11 12 13
9 10 11 12 13
BL2
SIG –OUT
SIG +OUT
+VS
LOG COM

BL2 9 12 +VS
BL2
SIG –OUT
SIG +OUT
+VS
LOG COM

SIG –OUT 10 11 SIG +OUT

–4– REV. D
 Typical DC Performance Characteristics–AD640
1.015 1.20 1.006

1.010 1.15 1.004

SLOPE CURRENT – mA
SLOPE CURRENT – mA

1.005 1.10

INTERCEPT – mV
1.002

1 1.05
1.000
0.995 1.00
0.998
0.990 0.95

0.996
0.985 0.90

0.980 0.85 0.994

–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 4.5 5.0 5.5 6.0 6.5 7.0 7.5
TEMPERATURE – 8C TEMPERATURE – 8C POWER SUPPLY VOLTAGES – 6 Volts

Figure 1. Slope Current, I Y vs. Figure 2. Intercept Voltage, VX, vs. Figure 3. Slope Current, IY vs.
Temperature Temperature Supply Voltages

14

DEVIATION OF INPUT OFFSET VOLTAGE – mV

1.015 +0.4

13 +0.3
1.010
INTERCEPT VOLTAGE – mV

INPUT OFFSET VOLTAGE

12 +0.2 DEVIATION WILL BE WITHIN
INTERCEPT – mV

1.005 SHADED AREA.

11 +0.1
1.000
10 0
0.995
9 –0.1

0.990 8 –0.2

0.985 7 –0.3
4.5 5.0 5.5 6.0 6.5 7.0 7.5 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
POWER SUPPLY VOLTAGES – 6 Volts TEMPERATURE – 8C TEMPERATURE – 8C

Figure 4. Intercept Voltage, VX, vs. Figure 5. Intercept Voltage (Using Figure 6. Input Offset Voltage
Supply Voltages Attenuator) vs. Temperature Deviation vs. Temperature

2 2.5 2.5
ERROR – dB

2.4
1
2.2
0
2.0
2.0 2.0
ABSOLUTE ERROR – dB

1.8
OUTPUT CURRENT – mA

ABSOLUTE ERROR – dB

1.6
1.4
1.5 1.5
1.2
1.0
0.8 1.0 1.0
0.6
0.4
0.2 0.5 0.5
0
–0.2
–0.4
0 0
0.1 1.0 10.0 100.0 1000.0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
INPUT VOLTAGE – mV TEMPERATURE – 8C TEMPERATURE – 8C
(EITHER SIGN)

Figure 7. DC Logarithmic Transfer Figure 8. Absolute Error vs. Tem- Figure 9. Absolute Error vs.
Function and Error Curve for Single perature, VIN = ⴞ1 mV to ⴞ 100 mV Temperature, Using Attenuator.
AD640 VIN = ⴞ10 mV to ⴞ1 V, Pin 8
Grounded to Disable ITC Bias

REV. D –5–
AD640 –Typical AC Performance Characteristics
–2.5 –2.5
+1258C
30MHz +1258C +258C
–2.0 60MHz –2.0
90MHz +258C

OUTPUT CURRENT – mA
OUTPUT CURRENT – mA

120MHz
–558C
–1.5 –1.5 +1

ERROR IN dB
–558C
–1.0 –1.0 0

+1258C
–0.5 –5 +258C –1
+1258C
–558C
0 AD640 6VS = 5 VOLTS 0 AD640 –2
TEMPERATURE = +258C FREQUENCY = 60MHz
–558C
0.5 0.5
–50 –40 –30 –20 –10 0 –50 –40 –30 –20 –10 0
INPUT LEVEL – dBm INPUT LEVEL – dBm

Figure 10. AC Response at 30 MHz, 60 MHz, 90 MHz and Figure 13. Logarithmic Response and Linearity at 60 MHz,
120 MHz, vs. dBm Input (Sinusoidal Input) TA for TA = –55 ⴗC, +25 ⴗC, +125 ⴗC

1.0 90

89

88

INTERCEPT LEVEL – dBm

0.95
SLOPE CURRENT – mA

87

86

0.90 85

84

83
0.85
82

81

0.80 80
DC 30 60 90 120 150 0 10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY – MHz INPUT FREQUENCY – MHz

Figure 11. Slope Current, IY, vs. Input Frequency Figure 14. Intercept Level (dBm) vs. Frequency
(Cascaded AD640s – Sinusoidal Input)

5µs 5µs
100
90

10
0%

20mV 20mV

Figure 12. Baseband Pulse Response of Single AD640, Figure 15. Baseband Pulse Response of Cascaded
Inputs of 1 mV, 10 mV and 100 mV AD640s, Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV

–6– REV. D
 AD640
CIRCUIT DESCRIPTION LOG OUT LOG COM

The AD640 uses five cascaded limiting amplifiers to approxi- Q9 Q10

COMMON
mate a logarithmic response to an input signal of wide dynamic R3 R4
75V 75V
range and wide bandwidth. This type of logarithmic amplifier SIG IN
Q1

has traditionally been assembled from several small scale ICs Q2 SIG OUT

and numerous external components. The performance of these

R1 R2
semidiscrete circuits is often unsatisfactory. In particular, the 85V 85V
Q3 Q4 Q5 Q6 Q7 Q8
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
–VS
laborious and expensive individual calibration. The AD640 1.09mA 1.09mA 565mA 565mA 2.18mA
employs high precision analog circuit techniques to ensure sta- PTAT PTAT PTAT

bility of scaling over wide variations in supply voltage and tem- Figure 16. Simplified Schematic of a Single AD640 Stage
perature. Laser trimming, using ac stimuli and operating
deviation or ripple in the transfer function of ± 0.15 dB from the
conditions similar to those encountered in practice, provides fully
ideal response when the input is either a dc voltage or a square
calibrated logarithmic conversion.
wave. The slope of the transfer function is unaffected by the
Each of the amplifier/limiter stages in the AD640 has a small input waveform; however, the intercept and ripple are waveform
signal voltage gain of 10 dB (×3.162) and a –3 dB bandwidth of dependent (see EFFECT OF WAVEFORM ON INTERCEPT).
350 MHz. Fully differential direct coupling is used throughout. The input will usually be an amplitude modulated sinusoidal
This eliminates the many interstage coupling capacitors usually carrier. In these circumstances the output is a fluctuating current at
required in ac applications, and simplifies low frequency signal twice the carrier frequency (because of the full wave detection)
processing, for example, in audio and sonar systems. The whose average value is extracted by an external low-pass filter,
AD640 is intended for use in demodulating applications. Each which recovers a logarithmic measure of the baseband signal.
stage incorporates a detector (a full wave transconductance
Circuit Operation
rectifier) whose output current depends on the absolute value of
With reference to Figure 16, the transconductance pair Q7, Q8
its input voltage.
and load resistors R3 and R4 form a limiting amplifier having a
Figure 16 is a simplified schematic of one stage of the AD640. small signal gain of 10 dB, set by the tail current of nominally
All transistors in the basic cell operate at near zero collector to 2.18 mA at 27°C. This current is basically proportional to abso-
base voltage and low bias currents, resulting in low levels of ther- lute temperature (PTAT) but includes additional current to
mally induced distortion. These arise when power shifts from one compensate for finite beta and junction resistance. The limiting
set of transistors to another during large input signals. Rapid output voltage is ± 180 mV at 27°C and is PTAT. Emitter fol-
recovery is essential when a small signal immediately follows a lowers Q1 and Q2 raise the input resistance of the stage, provide
large one. This low power operation also contributes signifi- level shifting to introduce collector bias for the gain stage and
cantly to the excellent long-term calibration stability of the AD640. detectors, reduce offset drift by forming a thermally balanced
The complete AD640, shown in Figure 17, includes two bias quad with Q7 and Q8 and generate the detector biasing across
regulators. One determines the small signal gain of the amplifier resistors R1 and R2.
stages; the other determines the logarithmic slope. These bias Transistors Q3 through Q6 form the full wave detector, whose
regulators maintain a high degree of stability in the resulting output is buffered by the cascodes Q9 and Q10. For zero input
function by compensating for potentially large uncertainties Q3 and Q5 conduct only a small amount (a total of about
in transistor parameters, temperature and supply voltages. A 32 µA) of the 565 µA tail currents supplied to pairs Q3–Q4 and
third biasing block is used to accurately control the logarithmic Q5–Q6. This “pedestal” current flows in output cascode Q9 to
intercept. the LOG OUT node (Pin 14). When driven to the peak output
By summing the signals at the output of the detectors, a good of the preceding stage, Q3 or Q5 (depending on signal polarity)
approximation to a logarithmic transfer function can be achieved. conducts lost of the tail current, and the output rises to 532 µA.
The lower the stage gain, the more accurate the approximation, The LOG OUT current has thus changed by 500 µA as the
but more stages are then needed to cover a given dynamic input has changed from zero to its maximum value. Since the
range. The choice of 10 dB results in a theoretical periodic detectors are spaced at 10 dB intervals, the output increases by
RG1 1kV RG0 1kV RG2 LOG OUT LOG COM
17 16 15 14 13 INTERCEPT POSITIONING BIAS 12 +VS
COM 18

ATN OUT 19 FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE

DETECTOR DETECTOR DETECTOR DETECTOR DETECTOR
SIG +IN 20 11 SIG +OUT
10dB 10dB 10dB 10dB 10dB
SIG –IN 1 10 SIG –OUT

ATN LO 2 AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER

27V
ATN COM 3 9 BL2
30V 270V
ATN COM 4 5 6 GAIN BIAS REGULATOR 7 SLOPE BIAS REGULATOR 8 ITC
ATN IN BL1 –VS

Figure 17. Block Diagram of the Complete AD640

REV. D –7–
AD640
50 µA/dB, or 1 mA per decade. This scaling parameter is 2.5

ABSOLUTE ERROR – dB
+258C –558C
trimmed to absolute accuracy using a 2 kHz square wave. At 1
0
frequencies near the system bandwidth, the slope is reduced due 2.0
–1
to the reduced output of the limiter stages, but it is still rela- +858C –2

OUTPUT CURRENT – mA
+1258C
tively insensitive to temperature variations so that a simple ex- 1.5
ternal slope adjustment in restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the 1.0

pedestal current from the summed detector outputs. It is ad-

justed during manufacture such that the output (flowing into 0.5
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly
± 10 mV is applied to the AD640. This places the dc intercept at 0
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an –0.5
1 10 100 1000 10000
inverted slope of –1 mA/decade. Because its pedestal is very INPUT VOLTAGE – mV
large (equivalent to about 100 dB), its intercept voltage is not
Figure 19. Logarithmic Output and Absolute Error vs. DC
guaranteed. The intercept positioning currents include a special
or Square Wave Input at TA = –55 °C, +25 °C, +85 °C and
internal temperature compensation (ITC) term which can be
+125 °C, Input via On-Chip Attenuator
disabled by connecting Pin 8 to ground.
roughly a square waveform. The signal path may be extended
The logarithmic function of the AD640 is absolutely calibrated
using these outputs (see OPERATION OF CASCADED
to within ± 0.3 dB (or ± 15 µA) for 2 kHz square-wave inputs of
AD640s). The logarithmic outputs from two or more AD640s
± 1 mV to ± 100 mV, and to within ± 1 dB between ± 750 µV and
can be directly summed with full accuracy.
± 200 mV. Figure 18 is a typical plot of the dc transfer function,
showing the outputs at temperatures of –55°C, +25°C and A pair of 1 kΩ applications resistors, RG1 and RG2 (Figure 17)
+125°C. While the slope and intercept are seen to be little af- are accessed via Pins 15, 16 and 17. These can be used to con-
fected by temperature, there is a lateral shift in the endpoints of vert an output current to a voltage, with a slope of 1 V/decade
the “linear” region of the transfer function, which reduces the (using one resistor), 2 V/decade (both resistors in series) or
effective dynamic range. The cause of this shift is explained in 0.5 V/decade (both in parallel). Using all the resistors from two
Fundamentals of Logarithmic Conversion section. AD640s (for example, in a cascaded configuration) ten slope
2.5
options from 0.25 V to 4 V/decade are available.
ABSOLUTE ERROR – dB

+1258C
+258C
2 FUNDAMENTALS OF LOGARITHMIC CONVERSION
2.0 –558C
1 The conversion of a signal to its equivalent logarithmic value
involves a nonlinear operation, the consequences of which can be
OUTPUT CURRENT – mA

0
1.5 –1
–558C
–2
very confusing if not fully understood. It is important to realize
+258C
from the outset that many of the familiar concepts of linear
1.0 +1258C
circuits are of little relevance in this context. For example, the
incremental gain of an ideal logarithmic converter approaches
0.5 infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at
0 the input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
–0.5
0.1 1.0 10.0 100.0 1000.0 We assume a dc signal in the following discussion to simplify the
INPUT VOLTAGE – mV
concepts; ac behavior and the effect of input waveform on cali-
Figure 18. Logarithmic Output and Absolute Error vs. DC bration are discussed later. A logarithmic converter having a
or Square Wave Input at T A = –55 °C, +25 °C, Input Direct voltage input VIN and output VOUT must satisfy a transfer func-
to Pins 1 and 20 tion of the form
The on chip attenuator can be used to handle input levels 20 dB VOUT = VY LOG (VIN/VX) Equation (1)
higher, that is, from ± 7.5 mV to ± 2 V for dc or square wave where Vy and Vx are fixed voltages which determine the scaling
inputs. It is specially designed to have a positive temperature of the converter. The input is divided by a voltage because the
coefficient and is trimmed to position the intercept at 10 mV dc argument of a logarithm has to be a simple ratio. The logarithm
(or –24 dBm for a sinusoidal input) over the full temperature must be multiplied by a voltage to develop a voltage output.
range. When using the attenuator the internal bias compensa- These operations are not, of course, carried out by explicit com-
tion should be disabled by grounding Pin 8. Figure 19 shows putational elements, but are inherent in the behavior of the
the output at –55°C, +25°C, +85°C and +125°C for a single converter. For stable operation, VX and VY must be based on
AD640 with the attenuator in use; the curves overlap almost sound design criteria and rendered stable over wide temperature
perfectly, and the lateral shift in the transfer function does not and supply voltage extremes. This aspect of RF logarithmic
occur. Therefore, the full dynamic range is available at all amplifier design has traditionally received little attention.
temperatures.
When VIN = VX, the logarithm is zero. VX is, therefore, called
The output of the final limiter is available in differential form at
the Intercept Voltage, because a graph of VOUT versus LOG (VIN)
Pins 10 and 11. The output impedance is 75 Ω to ground from
—ideally a straight line—crosses the horizontal axis at this point
either pin. For most input levels, this output will appear to have
–8– REV. D
 AD640
(see Figure 20). For the AD640, VX is calibrated to exactly When the attenuator is not used, the PTAT variation in VX
1 mV. The slope of the line is directly proportional to VY. Base will result in the intercept being temperature dependent. Near
10 logarithms are used in this context to simplify the relation- 300K (27°C) it will vary by 20 LOG (301/300) dB/°C, about
ship to decibel values. For VIN = 10 VX, the logarithm has a 0.03 dB/°C. Unless corrected, the whole output function would
value of 1, so the output voltage is VY. At VIN = 100 VX , the drift up or down by this amount with changes in temperature. In
output is 2 VY, and so on. VY can therefore be viewed either as the AD640 a temperature compensating current IYLOG(T/TO)
the Slope Voltage or as the Volts per Decade Factor. is added to the output. This effectively maintains a constant
intercept VXO. This correction is active in the default state (Pin
VYLOG (VIN /VX) IDEAL
8 open circuited). When using the attenuator, Pin 8 should be
2VY
ACTUAL grounded, which disables the compensation current. The drift
term needs to be compensated only once; when the outputs of
SLOPE = VY two AD540s are summed, Pin 8 should be grounded on at least
one of the two devices (both if the attenuator is used).
VY Conversion Range
Practical logarithmic converters have an upper and lower limit
on the input, beyond which errors increase rapidly. The upper
limit occurs when the first stage in the chain is driven into limit-
0
ACTUAL VIN = VX VIN = 10VX VIN = 100VX INPUT ON ing. Above this, no further increase in the output can occur and
LOG SCALE the transfer function flattens off. The lower limit arises because
IDEAL a finite number of stages provide finite gain, and therefore at
low signal levels the system becomes a simple linear amplifier.
Figure 20. Basic DC Transfer Function of the AD640
Note that this lower limit is not determined by the intercept
The AD640 conforms to Equation (1) except that its two out-
voltage, VX ; it can occur either above or below VX, depending
puts are in the form of currents, rather than voltages:
on the design. When using two AD640s in cascade, input offset
IOUT = IY LOG (VIN /VX ) Equation (2) voltage and wideband noise are the major limitations to low
IY the Slope Current, is 1 mA. The current output can readily be level accuracy. Offset can be eliminated in various ways. Noise
converted to a voltage with a slope of 1 V/decade, for example, can only be reduced by lowering the system bandwidth, using a
using one of the 1 kΩ resistors provided for this purpose, in filter between the two devices.
conjunction with an op amp, as shown in Figure 21.
EFFECT OF WAVEFORM ON INTERCEPT
1mA PER R2 The absolute value response of the AD640 allows inputs of
DECADE
R1
48.7V AD844
either polarity to be accepted. Thus, the logarithmic output in
response to an amplitude-symmetric square wave is a steady
C1
330pF value. For a sinusoidal input the fluctuating output current will
OUTPUT VOLTAGE usually be low-pass filtered to extract the baseband signal. The
1V PER DECADE
15 14 13 12 11
FOR R2 = 1kV unfiltered output is at twice the carrier frequency, simplifying the
LOG LOG +VS SIG 100mV PER dB design of this filter when the video bandwidth must be maxi-
OUT COM +OUT for R2 = 2kV
mized. The averaged output depends on waveform in a roughly
AD640
SIG
analogous way to waveform dependence of rms value. The effect
–VS ITC BL2 –OUT is to change the apparent intercept voltage. The intercept volt-
6 7 8 9 10
age appears to be doubled for a sinusoidal input, that is, the
averaged output in response to a sine wave of amplitude (not rms
Figure 21. Using an External Op Amp to Convert the
value) of 20 mV would be the same as for a dc or square wave
AD640 Output Current to a Buffered Voltage Output
input of 10 mV. Other waveforms will result in different inter-
Intercept Stabilization cept factors. An amplitude-symmetric-rectangular waveform
Internally, the intercept voltage is a fraction of the thermal volt- has the same intercept as a dc input, while the average of a
age kT/q, that is, VX = VXOT/TO, where VXO is the value of VX baseband unipolar pulse can be determined by multiplying the
at a reference temperature TO. So the uncorrected transfer response to a dc input of the same amplitude by the duty cycle.
function has the form It is important to understand that in responding to pulsed RF
IOUT = IY LOG (VIN TO/VXOT) Equation (3) signals it is the waveform of the carrier (usually sinusoidal) not
the modulation envelope, that determines the effective intercept
Now, if the amplitude of the signal input VIN could somehow be
voltage. Table I shows the effective intercept and resulting deci-
rendered PTAT, the intercept would be stable with tempera-
bel offset for commonly occurring waveforms. The input wave-
ture, since the temperature dependence in both the numerator
form does not affect the slope of the transfer function. Figure 22
and denominator of the logarithmic argument would cancel.
shows the absolute deviation from the ideal response of cascaded
This is what is actually achieved by interposing the on-chip
AD640s for three common waveforms at input levels from
attenuator, which has the necessary temperature dependence to
–80 dBV to –10 dBV. The measured sine wave and triwave
cause the input to the first stage to vary in proportion to abso-
responses are 6 dB and 8.7 dB, respectively, below the square
lute temperature. The end limits of the dynamic range are now
wave response—in agreement with theory.
totally independent of temperature. Consequently, this is the
preferred method of intercept stabilization for applications
where the input signal is sufficiently large.

REV. D –9–
AD640
Table I. The accuracy at low signal inputs is also waveform dependent.
The detectors are not perfect absolute value circuits, having a
Input Peak Intercept Error (Relative sharp “corner” near zero; in fact they become parabolic at low
Waveform or RMS Factor to a DC Input) levels and behave as if there were a dead zone. Consequently,
Square Wave Either 1 0.00 dB the output tends to be higher than ideal. When there are enough
Sine Wave Peak 2 –6.02 dB stages in the system, as when two AD640s are connected in
Sine Wave rms 1.414(√2) –3.01 dB cascade, most detectors will be adequately loaded due to the
Triwave Peak 2.718 (e) –8.68 dB high overall gain, but a single AD640 does not have sufficient
Triwave rms 1.569(e/√3) –3.91 dB gain to maintain high accuracy for low level sine wave or triwave
Gaussian Noise rms 1.887 –5.52 dB inputs. Figure 23 shows the absolute deviation from calibration
for the same three waveforms for a single AD640. For inputs
Logarithmic Conformance and Waveform between –10 dBV and –40 dBV the vertical displacement of the
The waveform also affects the ripple, or periodic deviation from traces for the various waveforms remains in agreement with the
an ideal logarithmic response. The ripple is greatest for dc or predicted dependence, but significant calibration errors arise at
square wave inputs because every value of the input voltage low signal levels.
maps to a single location on the transfer function and thus
traces out the full nonlinearities in the logarithmic response. SIGNAL MAGNITUDE
AD640 is a calibrated device. It is, therefore, important to be
By contrast, a general time varying signal has a continuum of
clear in specifying the signal magnitude under all waveform
values within each cycle of its waveform. The averaged output is
conditions. For dc or square wave inputs there is, of course, no
thereby “smoothed” because the periodic deviations away from
ambiguity. Bounded periodic signals, such as sinusoids and
the ideal response, as the waveform “sweeps over” the transfer
triwaves, can be specified in terms of their simple amplitude
function, tend to cancel. This smoothing effect is greatest for a
(peak value) or alternatively by their rms value (which is a mea-
triwave input, as demonstrated in Figure 22.
sure of power when the impedance is specified). It is generally bet-
2 ter to define this type of signal in terms of its amplitude because
the AD640 response is a consequence of the input voltage, not
DEVIATION FROM EXACT LOGARITHMIC

SQUARE WAVE INPUT

0 power. However, provided that the appropriate value of inter-
cept for a specific waveform is observed, rms measures may be
TRANSFER FUNCTION – dB

–2 used. Random waveforms can only be specified in terms of rms

value because their peak value may be unbounded, as is the case
–4 for Gaussian noise. These must be treated on a case-by-case
basis. The effective intercept given in Table I should be used for
SINE WAVE INPUT
–6
Gaussian noise inputs.
On the other hand, for bounded signals the amplitude can be
–8 expressed either in volts or dBV (decibels relative to 1 V). For
TRIWAVE INPUT
example, a sine wave or triwave of 1 mV amplitude can also be
–10 defined as an input of –60 dBV, one of 100 mV amplitude as
–80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz –20 dBV, and so on. RMS value is usually expressed in dBm
(decibels above 1 mW) for a specified impedance level. Through-
Figure 22. Deviation from Exact Logarithmic Transfer out this data sheet we assume a 50 Ω environment, the customary
Function for Two Cascaded AD640s, Showing Effect of impedance level for high speed systems, when referring to signal power
Waveform on Calibration and Linearity in dBm. Bearing in mind the above discussion of the effect of
waveform on the intercept calibration of the AD640, it will be
4 apparent that a sine wave at a power of, say, –10 dBm will not
produce the same output as a triwave or square wave of the
DEVIATION FROM EXACT LOGARITHMIC

2
SQUARE WAVE INPUT
same power. Thus, a sine wave at a power level of –10 dBm has
an rms value of 70.7 mV or an amplitude of 100 mV (that is, √2
TRANSFER FUNCTION – dB

0
times as large, the ratio of amplitude to rms value for a sine
–2
wave), while a triwave of the same power has an amplitude
–4 which is √3 or 1.73 times its rms value, or 122.5 mV.
SINE WAVE INPUT
–6
“Intercept” and “Logarithmic Offset”
If the signals are expressed in dBV, we can write the output in a
–8 simpler form, as
–10
TRIWAVE INPUT
IOUT = 50 µA (InputdBV – XdBV) Equation (4)
–12
where InputdBV is the input voltage amplitude (not rms) in dBV
–70 –60 –50 –40 –30 –20 –10 and XdBV is the appropriate value of the intercept (for a given
INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz
waveform) in dBV. This form shows more clearly why the intercept
Figure 23. Deviation from Exact Logarithmic Transfer is often referred to as the logarithmic offset. For dc or square
Function for a Single AD640; Compare Low Level wave inputs, VX is 1 mV so the numerical value of XdBV is –60,
Response with that of Figure 22 and Equation (4) becomes

–10– REV. D
 AD640
IOUT = 50 µA (InputdBV + 60) Equation (5) Erie RPE113-Z5U-105-K50V). Ferrite beads may be used
Alternatively, for a sinusoidal input measured in dBm (power in instead of supply decoupling resistors in cases where the supply
dB above 1 mW in a 50 Ω system) the output can be written voltage is low.
IOUT = 50 µA (InputdBm + 44) Equation (6) Active Current-to-Voltage Conversion
The compliance at LOG OUT limits the available output volt-
because the intercept for a sine wave expressed in volts rms is at age swing. The output of the AD640 may be converted to a
1.414 mV (from Table I) or –44 dBm. larger, buffered output voltage by the addition of an operational
amplifier connected as a current-to-voltage (transresistance)
OPERATION OF A SINGLE AD640 stage, as shown in Figure 21. Using a 2 kΩ feedback resistor
Figure 24 shows the basic connections for a single device, using (R2) the 50 µA/dB output at LOG OUT is converted to a volt-
100 Ω load resistors. Output A is a negative going voltage with a age having a slope of +100 mV/dB, that is, 2 V per decade. This
slope of –100 mV per decade; output B is positive going with a output ranges from roughly –0.4 V for zero signal inputs to the
slope of +100 mV per decade. For applications where absolute AD640, crosses zero at a dc input of precisely +1 mV (or
calibration of the intercept is essential, the main output (from –1 mV) and is +4 V for a dc input of 100 mV. A passive
LOG OUT, Pin 14) should be used; the LOG COM output can prefilter, formed by R1 and C1, minimizes the high frequency
then be grounded. To evaluate the demodulation response, a energy conveyed to the op amp. The corner frequency is here
simple low-pass output filter having a time constant of roughly shown as 10 MHz. The AD844 is recommended for this appli-
500 µs (3 dB corner of 320 Hz) is provided by a 4.7 µF (–20% cation because of its excellent performance in transresistance
+80%) ceramic capacitor (Erie type RPE117-Z5U-475-K50V) modes. Its bandwidth of 35 MHz (with the 2 kΩ feedback resis-
placed across the load. A DVM may be used to measure the tor) will exceed the baseband response of the system in most
averaged output in verification tests. The voltage compliance at applications. For lower bandwidth applications other op amps
Pins 13 and 14 extends from 0.3 V below ground up to 1 V and multipole active filters may be substituted (see, for example,
below +VS. Since the current into Pin 14 is from –0.2 mA at Figure 32 in the APPLICATIONS section).
zero signal to +2.3 mA when fully limited (dc input of >300 mV)
the output never drops below –230 mV. On the other hand, the Effect of Frequency on Calibration
current out of Pin 13 ranges from 0.2 mA to +2.3 mA, and if The slope and intercept of the AD640 are calibrated during
desired, a load resistor of up to 2 kΩ can be used on this output; manufacture using a 2 kHz square wave input. Calibration de-
the slope would then be 2 V per decade. Use of the LOG COM pends on the gain of each stage being 10 dB. When the input
output in this way provides a numerically correct decibel read- frequency is an appreciable fraction of the 350 MHz bandwidth
ing on a DVM (+100 mV = +1.00 dB). of the amplifier stages, their gain becomes imprecise and the
logarithmic slope and intercept are no longer fully calibrated.
Board layout is very important. The AD640 has both high gain However, the AD640 can provide very stable operation at fre-
and wide bandwidth; therefore every signal path must be very quencies up to about one half the 3 dB frequency of the ampli-
carefully considered. A high quality ground plane is essential, fier stages. Figure 10 shows the averaged output current versus
but it should not be assumed that it behaves as an equipotential input level at 30 MHz, 60 MHz, 90 MHz and 120 MHz. Fig-
plane. Even though the application may only call for modest ure 11 shows the absolute error in the response at 60 MHz and
bandwidth, each of the three differential signal interface pairs at temperatures of –55°C, +25°C and +125°C. Figure 12 shows
(SIG IN, Pins 1 and 20, SIG OUT, Pins 10 and 11, and LOG, the variation in the slope current, and Figure 13 shows the
Pins 13 and 14) must have their own “starred” ground points to variation in the intercept level (sinusoidal input) versus frequency.
avoid oscillation at low signal levels (where the gain is highest).
If absolute calibration is essential, or some other value of slope
Unused pins (excluding Pins 8, 10 and 11) such as the attenua- or intercept is required, there will usually be some point in the
tor and applications resistors should be grounded close to the user’s system at which an adjustment may be easily introduced.
package edge. BL1 (Pin 6) and BL2 (Pin 9) are internal bias For example, the 5% slope deficit at 30 MHz (see Figure 12)
lines a volt or two above the –VS node; access is provided solely may be restored by a 5% increase in the value of the load resis-
for the addition of decoupling capacitors, which should be con- tor in the passive loading scheme shown in Figure 24, or by
nected exactly as shown (not all of them connect to the ground). inserting a trim potentiometer of 100 Ω in series with the feed-
Use low impedance ceramic 0.1 µF capacitors (for example, back resistor in the scheme shown in Figure 21. The intercept
DENOTES A SHORT, DIRECT CONNECTION 10V
TO THE GROUND PLANE. +5V
ALL UNMARKED CAPACITORS ARE OUTPUT A
0.1mF CERAMIC (SEE TEXT)
OUTPUT B
NC
20 19 18 17 16 15 14 13 12 11
OPTIONAL RLA RLB
SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG
TERMINATION +IN OUT COM OUT COM +OUT 4.7mF 100V 4.7mF 100V
RESISTOR 1kV 1kV 0.1% 0.1%

SIGNAL AD640
INPUT
SIG ATN ATN ATN ATN SIG
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT
1 2 3 4 5 6 7 8 9 10
NC NC
4.7V
OPTIONAL –5V
OFFSET BALANCE
RESISTOR NC = NO CONNECT

Figure 24. Connections for a Single AD640 to Verify Basic Performance

REV. D –11–
AD640
can be adjusted by adding or subtracting a small current to the CASCADED OPERATION explains how the offset can be
output. Since the slope current is 1 mA/decade, a 50 µA incre- automatically nulled to submicrovolt levels by the use of a nega-
ment will move the intercept by 1 dB. Note that any error in tive feedback network.
this current will invalidate the calibration of the AD640. For Using Higher Supply Voltages
example, if one of the 5 V supplies were used with a resistor to The AD640 is calibrated using ±5 V supplies. Scaling is very
generate the current to reposition the intercept by 20 dB, a insensitive to the supply voltages (see dc SPECIFICATIONS)
± 10% variation in this supply will cause a ± 2 dB error in the and higher supply voltages will not directly cause significant
absolute calibration. Of course, slope calibration is unaffected. errors. However, the AD640 power dissipation must be kept
Source Resistance and Input Offset below 500 mW in the interest of reliability and long-term stabil-
The bias currents at the signal inputs (Pins 1 and 20) are typi- ity. When using well regulated supply voltages above ± 6 V, the
cally 7 µA. These flow in the source resistances and generate decoupling resistors shown in the application schematics can be
input offset voltages which may limit the dynamic range because increased to maintain ± 5 V at the IC. The resistor values are
the AD640 is direct coupled and an offset is indistinguishable calculated using the specified maximum of 15 mA current into
from a signal. It is good practice to keep the source resistances the +VS terminal (Pin 12) and a maximum of 60 mA into the
as low as possible and to equalize the resistance seen at each –VS terminal (Pin 7). For example, when using ± 9 V supplies, a
input. For example, if the source resistance to Pin 20 is 100 Ω, a resistor of (9 V–5 V)/15 mA, about 261 Ω, should be included in
compensating resistor of 100 Ω should be placed in series with the +VS lead to each AD640, and (9 V–5 V)/60 mA, about 64.9 Ω,
Pin l. The residual offset is then due to the bias current offset, in each –VS lead. Of course, asymmetric supplies may be dealt
which is typically under 1 µA, causing an extra offset uncertainty with in a similar way.
of 100 µV in this example. For a single AD640 this will rarely be Using the Attenuator
troublesome, but in some applications it may need to be nulled In applications where the signal amplitude is sufficient, the on-
out, along with the internal voltage offset component. This may chip attenuator should be used because it provides a tempera-
be achieved by adding an adjustable voltage of up to ± 250 µV at ture independent dynamic range (compare Figures 18 and 19).
the unused input. (Pins l and 20 may be interchanged with no Figure 26 shows this attenuator in more detail. R1 is a thin-film
change in function.) resistor of nominally 270 Ω and low temperature coefficient
In most applications there will be no need to use any offset (TC). It is trimmed to calibrate the intercept to 10 mV dc (or
adjustment. However, a general offset trimming circuit is shown –24 dBm for sinusoidal inputs), that is, to an attenuation of
in Figure 25. RS is the source resistance of the signal. Note: 50 Ω nominally 20 dBs at 27°C. R2 has a nominal value of 30 Ω and
rf sources may include a blocking capacitor and have no dc path to has a high positive TC, such that the overall attenuation factor
ground, or may be transformer coupled and have a near zero resis- is 0.33%/°C at 27°C. This results in a transmission factor that is
tance to ground. Determine whether the source resistance is zero, proportional to absolute temperature, or PTAT. (See Intercept
25 Ω or 50 Ω (with the generator terminated in 50 Ω) to find Stabilization for further explanation.) To improve the accuracy
the correct value of bias compensating resistor, RB, which of the attenuator, the ATN COM nodes are bonded to both
should optimally be equal to RS, unless RS = 0, in which case Pin 3 and Pin 4. These should be connected directly to the “SIG-
use RB = 5 Ω. The value of ROS should be set to 20,000 RB to NAL LOW” of the source (for example, to the grounded side of
provide a ± 250 µV trim range. To null the offset, set the source the signal connector, as shown in Figure 32) not to an arbitrary
voltage to zero and use a DVM to observe the logarithmic out- point on the ground plane.
put voltage. Recall that the LOG OUT current of the AD640
SIG ATN
exhibits an absolute value response to the input voltage, so the offset +IN OUT
potentiometer is adjusted to the point where the logarithmic output 20 19 18 17 16
“turns around” (reaches a local maximum or minimum). R1
AD640
R2
RS

(SOURCE RESISTANCE 20 19
OF TERMINATED R3 FIRST
GENERATOR) AMPLIFIER
AD640 R4

1 2 1 2 3 4 5
RB
SIG ATN ATN ATN ATN
–IN LO COM COM IN
+5V
ROS
20kV INPUT

–5V Figure 26. Details of the Input Attenuator

Figure 25. Optional Input Offset Voltage Nulling Circuit; R4 is identical to R2, and in shunt with R3 (270 Ω thin film)
See Text for Component Values forms a 27 Ω resistor with the same TC as the output resistance
At high frequencies it may be desirable to insert a coupling of the attenuator. By connecting Pin 1 to ATN LOW (Pin 2)
capacitor and use a choke between Pin 20 and ground, when this resistance minimizes the offset caused by bias currents. The
Pin 1 should be taken directly to ground. Alternatively, trans- offset nulling scheme shown in Figure 25 may still be used, with
former coupling may be used. In these cases, there is no added the external resistor RB omitted and ROS = 500 kΩ. Offset sta-
offset due to bias currents. When using two dc coupled AD640s bility is improved because the compensating voltage introduced
(overall gain 100,000), it is impractical to maintain a sufficiently at Pin 20 is now PTAT. Drifts of under 1 µV/°C (referred to
low offset voltage using a manual nulling scheme. The section Pins 1 and 20) can be maintained using the attenuator.

–12– REV. D
 AD640
It may occasionally be desirable to attenuate the signal even to null the input offset and minimize drift due to input bias
further. For example, the source may have a full-scale value of offset. It is recommended that the input attenuator be used,
± 10 V, and since the basic range of the AD640 extends only to providing a practical input range of –74 dBV (± 200 µV dc) to
± 200 mV dc, an attenuation factor of ×50 might be chosen. +6 dBV (± 2 V dc) when nulled using the adjustment circuit
This may be achieved either by using an independent external shown in Figure 25.
attenuator or more simply by adding a resistor in series with Eliminating the Effect of First Stage Offset
ATN IN (Pin 5). In the latter case the resistor must be trimmed Usually, the input signal will be sinusoidal and U1 and U2 can
to calibrate the intercept, since the input resistance at Pin 5 is be ac coupled. Figure 28a shows a low resistance choke at the
not guaranteed. A fixed resistor of 1 kΩ in series with a 500 Ω input of U2 which shorts the dc output of U1 while preserving
variable resistor calibrate to an intercept of 50 mV (or –26 dBV) the hf response. Coupling capacitors may be inserted (Fig-
for dc or square wave inputs and provide a ± 10 V input range. ure 28b) in which case two chokes are used to provide bias
The intercept stability will be degraded to about 0.003 dB/°C. paths for U2. These chokes must exhibit high impedance over
the operating frequency range.
OPERATION OF CASCADED AD640S
Frequently, the dynamic range of the input will be 50 dB or
more. AD640s can be cascaded, as shown in Figure 27. The 11 20 11 20
balanced signal output from U1 becomes the input to U2. Re- U1 U2 U1 U2
sistors are included in series with each LOG OUT pin and
10 1 10 1
capacitors C1 and C2 are placed directly between Pins 13 and 14
to provide a local path for the RF current at these output pairs.
C1 through C3 are chosen to provide the required low-pass a. b.
corner in conjunction with the load RL. Board layout and Figure 28. Two Methods for AC-Coupling AD640s
grounding disciplines are critically important at the high gain
Alternatively, the input offset can be nulled by a negative feed-
(X100,000) and bandwidth (~150 MHz) of this system.
back network from the SIG OUT nodes of U2 to the SIG IN
The intercept voltage is calculated as follows. First, note that if nodes of U1, as shown in Figure 29. The low-pass response of
its LOG OUT is disconnected, U1 simply inserts 50 dB of the feedback path transforms to a closed-loop high-pass re-
gain ahead of U2. This would lower the intercept by 50 dB, to sponse. The high gain (×100,000) of the signal path results in a
–110 dBV for square wave calibration. With the LOG OUT of commensurate reduction in the effective time constant of this
U1 added in, there is a finite zero signal current which slightly network. For example, to achieve a high-pass corner of 100 kHz,
shifts the intercept. With the intercept temperature compensa- the low-pass corner must be at 1 Hz.
tion on U1 disabled this zero signal output is –270 µA (see DC
In fact, it is somewhat more complicated than this. When the ac
SPECIFICATIONS) equivalent to a 5.4 dB upward shift in the
input sufficiently exceeds that of the offset, the feedback be-
intercept, since the slope is 50 µA/dB. Thus, the intercept is at
comes ineffective and the response becomes essentially dc
–104.6 dBV (–88.6 dBm for 50 Ω sine calibration). ITC may be
coupled. Even for quite modest inputs the last stage will be
disabled by grounding Pin 8 of either U1 or U2.
limiting and the output (Pins 10 and 11) of U2 will be a square
Cascaded AD640s can be used in dc applications, but input wave of about ± 180 mV amplitude, dwelling approximately
offset voltage will limit the dynamic range. The dc intercept is equal times at its two limit values, and thus having a net average
6 µV. The offset should not be confused with the intercept, which is value near zero. Only when the input is very small does the high-
found by extrapolating the transfer function from its central “log pass behavior of this nulling loop become apparent. Consequently,
linear” region. This can be understood by referring to Equation the low-pass time constant can usually be reduced considerably
(1) and noting that an input offset is simply additive to the value without serious performance degradation.
of VIN in the numerator of the logarithmic argument; it does not
The resistor values are chosen such that the dc feedback is ade-
affect the denominator (or intercept) VX. In dc coupled applica-
quate to null the worst case input offset, say, 500 µV. There
tions of wide dynamic range, special precautions must be taken
DENOTES A CONNECTION TO THE GROUND PLANE;
OBSERVE COMMON CONNECTIONS WHERE SHOWN. +5V
ALL UNMARKED CAPACITORS ARE 0.1mF CERAMIC. 1mA/DECADE
SEE TEXT FOR VALUES OF NUMBERED COMPONENTS.
10V 10V OUTPUT
10V 10V
–50mV/DECADE
C1 C2
NC
C3 RL= 50V
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG
SIGNAL +IN OUT COM OUT COM +OUT +IN OUT COM OUT COM +OUT
R1 1kV 1kV 1kV 1kV
INPUT
U1 AD640 U2 AD640
SIG ATN ATN ATN ATN SIG SIG ATN ATN ATN ATN SIG
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT –IN LO COM COM IN BL1 –VS ITC BL2 –OUT
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
R2
NC NC

NC = NO CONNECT 4.7V 4.7V

–5V

Figure 27. Basic Connections for Cascaded AD640s

REV. D –13–
AD640
14mA
must be some resistance at Pins 1 and 20 across which the offset R3 R4
compensation voltage is developed. The values shown in the 4.99kV AVE = –40mV 4.99kV
–200mV
figure assume that we wish to terminate a 50 Ω source at Pin 20. R1 20 11 20 11 C1
The 50 Ω resistor at Pin 1 is essential, both to minimize offsets
INPUT 50V

due to bias current mismatch and because the outputs at Pins U1 U2

R2
10 and 11 can only swing negatively (from ground to –180 mV) 50V
1 10 1 10 C2

whereas we need to cater for input offsets of either polarity. –700mV R5 R6

AVE = –140mV
For a sine input of 1 µV amplitude (–120 dBV) and in the
4.99kV 4.99kV
4mA
absence of offset, the differential voltage at Pins 10 and 11 of
U2 would be almost sinusoidal but 100,000 times larger, or Figure 29. Feedback Offset Correction Network
100 mV. The last limiter in U2 would be entering saturation. A –3 dB frequency of the filter must be above the highest fre
1 µV input offset added to this signal would put the last limiter quency to be handled by the converter; if not, nonlinearity in
well into saturation, and its output would then have a different the transfer function will occur. This can be seen intuitively by
average value, which is extracted by the low-pass network and noting that the system would then contract to a single AD640 at
delivered back to the input. For larger signals, the output ap- very high frequencies (when U2 has very little input). At inter-
proaches a square wave for zero input offset and becomes rect- mediate frequencies, U2 will contribute less to the output than
angular when offset is present. The duty cycle modulation of would be the case if there were no interstage attenuation, result-
this output now produces the nonzero average value. Assume a ing in a kink in the transfer function.
maximum required differential output of 100 mV (after averag-
ing in C1 and C2) as shown in Figure 29. R3 through R6 can More complex filtering may be considered. For example, if the
now be chosen to provide ± 500 µV of correction range, and with signal has a fairly narrow bandwidth, the simple chokes shown
these values the input offset is reduced by a factor of 500. Using in Figure 28 might be replaced by one or more parallel tuned
4.7 µF capacitors, the time constant of the network is about circuits. Two separate tuned circuits or transformer coupling
1.2 ms, and its corner frequency is at 13.5 Hz. The closed loop should be used to eliminate all undesirable hf common mode
high-pass corner (for small signals) is, therefore, at 1.35 MHz. coupling between U1 and U2. The choice of Q for these circuits
requires compromise. Frequency sensitive nonlinearities can
Bandwidth/Dynamic Range Trade-Offs arise at the edges of the band if the Q is set too high; if too low,
The first stage noise of the AD640 is 2 nV/√Hz (short circuited the transmission of the signal from U1 to U2 will be affected
input) and the full bandwidth of the cascaded ten stages is about even at the center frequency, again resulting in nonlinearity in
150 MHz. Thus, the noise referred to the input is 24.5 µV rms, the conversion response. In calculating the Q, note that the
or –79 dBm, which would limit the dynamic range to 77 dBs resistance from Pins 10 and 11 to ground is 75 Ω. The input
(–79 dBm to –2 dBm). In practice, the source resistances will resistance at Pins 1 and 20 is very high, but the capacitances at
also generate noise, and the full bandwidth dynamic range will these pins must also be factored into the total LCR circuit.
be less than this.
A low-pass filter between U1 and U2 can limit the noise band- PRACTICAL APPLICATIONS
width and extend the dynamic range. The simplest way to do We show here two applications, using cascaded AD640s to
this is by the addition of a pair of grounded capacitors at the achieve a wide dynamic range. As already mentioned, the use of
signal outputs of U1 (shown as C1 and C2 in Figure 32). The a differential signal path and differential logarithmic outputs
R13
1.13kV (SEE TEXT)
4.7V
+6V

DENOTES A CONNECTION TO THE GROUND PLANE; LOG

OBSERVE COMMON CONNECTIONS WHERE SHOWN. U3 OUTPUT
ALL UNMARKED CAPACITORS ARE 0.1mF CERAMIC. AD844 +50mV/dB
SEE TEXT FOR VALUES OF NUMBERED COMPONENTS. 4.7V
–6V

(LO)

R3 +6V R4
100V 68V 68V 100V

C1 C2
47pF 47pF
NC
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
R1
SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG
+IN OUT COM OUT COM +OUT +IN OUT COM OUT COM +OUT
SIGNAL
1kV 1kV L1 1kV 1kV
INPUT U1 AD640 (SEE U2 AD640
TEXT)
SIG ATN ATN ATN ATN SIG SIG ATN ATN ATN ATN SIG
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT –IN LO COM COM IN BL1 –VS ITC BL2 –OUT
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
R2
NC NC
18V 18V

NC = NO CONNECT –6V

Figure 30. Complete 70 dB Dynamic Range Converter for 50 MHz–150 MHz Operation

–14– REV. D
 AD640
diminishes the risk of instability due to poor grounding. Never- A transimpedance op amp (U3, AD844) converts the summed
theless, it must be remembered that at high frequencies even logarithmic output currents of U1 and U2 to a ground referenced
very small lengths of wire, including the leads to capacitors, voltage scaled 1 V per decade. The resistor R5 is nominally 1 kΩ
have significant impedance. The ground plane itself can also but is increased slightly to compensate for the slope deficit at the
generate small but troublesome voltages due to circulating cur- operating frequency, which can be determined from Figure 12.
rents in a poor layout. A printed circuit evaluation board is The inverting input of U3 forms a virtual ground, so that each
available from Analog Devices (Part Number ADEB640) to logarithmic output of U1 and U2 is loaded by 100 Ω (R3 or
facilitate the prototyping of an application using one or two R4). These resistors in conjunction with capacitors C1 and C2
AD640s, plus various external components. form independent low-pass filters with a time constant of about
At very low signal levels various effects can cause significant
deviation from the ideal response, apart from the inherent non- 4 +1

ERROR – dB
linearities of the transfer function already discussed. Note that 0
any spurious signal presented to the AD640s is demodulated and

LOW-PASS FILTERED OUTPUT – V

added to the output. Thus, in the absence of thorough shielding, 3 –1
emissions from any radio transmitters or RFI from equipment
operating in the locality will cause the output to appear too
high. The only cure for this type of error is the use of very care- 2
ful grounding and shielding techniques.
50 MHz–150 MHz Converter with 70 dB Dynamic Range
Figure 30 shows a logarithmic converter using two AD640s 1
which can provide at least 70 dB of dynamic range, limited
mostly by first stage noise. In this application, an rf choke (L1)
prevents the transmission of dc offset from the first to the sec-
0
ond AD640. One or two turns in a ferrite core will generally –70 –60 –50 –40 –30 –20 –10 0
INPUT LEVEL – dBm IN 50V
suffice for operation at frequencies above 30 MHz. For ex-
ample, one complete loop of 20 gauge wire through the two Figure 31. Logarithmic Output and Nonlinearity for Circuit
holes in a Fair-Rite type 2873002302 core provides an inductance of Figure 30, for a Sine Wave Input at f = 80 MHz
of 5 µH, which presents an impedance of 1.57 kΩ at 50 MHz.
5 ns. These capacitors should be connected directly across Pins
The shunting effect across the 150 Ω differential impedance at
13 and 14, as shown, to prevent high frequency output currents
the signal interface is thus fairly slight.
from circulating in the ground plane. A second 5 ns time con-
The signal source is optionally terminated by R1. To minimize stant is formed by feedback resistor R5 in conjunction with the
the input offset voltage R2 should be chosen to match the dc transcapacitance of U3.
resistance of the terminated source. (However, the offset voltage
This filtering is adequate for input frequencies of 50 MHz or
is not a critical consideration in this ac-coupled application.)
above; more elaborate filtering can be devised for pulse
Note that all unused inputs are grounded; this improves the applications requiring a faster rise time. In applications where
isolation from the outputs back to the inputs. only a long term measure of the input is needed, C1 and C2 can

DENOTES A CONNECTION TO THE GROUND PLANE; C4

4.7mF C5
OBSERVE COMMON CONNECTIONS WHERE SHOWN. 0.1mF
ALL UNMARKED CAPACITORS ARE 0.1mF CERAMIC.
9.1V C3
R1 1/2
+6V
100mF
49.9V 2 AD712 R2 R3 1/2
+15V
TO U3 TO U1 1 50kV 50kV 5 AD712
AND U4 AND U2 3 U3a 7
–15V –6V 6 U3b
9.1V R4
C6 LOG
200kV
0.1mF OUTPUT
+15V
0.1mF R5 +100mV/dB
TO U3
AND U4 +6V 200kV
0.1mF 68V 68V
–15V
R6 1/2
5kV 3.3MV 3 AD712
A NC 1
2 U4a B
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
C1 C7
SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG (SEE SIG ATN CKT RG1 RG0 RG2 LOG LOG +VS SIG
+IN OUT COM OUT COM +OUT +IN OUT COM OUT COM +OUT 4.7mF
TEXT)
OFFSET 1kV 1kV 1kV 1kV
NULLING OFFSET
FEEDBACK U1 AD640 U2 AD640 NULLING
SIG ATN ATN ATN ATN SIG C2 SIG ATN ATN ATN ATN SIG FEEDBACK
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT (SEE C8
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT
TEXT) 4.7mF 1/2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
5kV 5 AD712
B 7
R7 6 U4b A
18V 18V 3.3MV
NC = NO CONNECT
SIGNAL INPUT –6V

Figure 32. Complete 95 dB Dynamic Range Converter

REV. D –15–
AD640
be increased and U3 can be replaced by a low speed op amp. high-pass filter is only operative for very small inputs; see page
Figure 31 shows typical performance of this converter. 13.) Figure 33 shows the performance for square wave inputs.
10 Hz–100 kHz Converter with 95 dB Dynamic Range Since the attenuator is used, the upper end of the dynamic
To increase the dynamic range it is necessary to reduce the range now extends to +6 dBV and the intercept is at –82 dBV.
bandwidth by the inclusion of a low-pass filter at the signal The noise limited dynamic range is over 100 dB, but in practice
interface between U1 and U2 (Figure 32). To provide operation spurious signals at the input will determine the achievable range.
down to low frequencies, dc coupling is used at the interface 9 2
between AD640s and the input offset is nulled by a feedback
8 0
circuit.
7 –2
Using values of 0.02 µF in the interstage filter formed by capaci-

LOG OUTPUT FROM CIRCUIT

TRANSFER FUNCTION – dB
tors C1 and C2, the hf corner occurs at about 100 kHz. U3 6

ERROR FROM IDEAL

OF FIGURE 32 – V
(AD712) forms a 4-pole 35 Hz low-pass filter. This provides 5
operation to signal frequencies below 20 Hz. The filter response 4
is not critical, allowing the use of an electrolytic capacitor to
3
form one of the poles.
R1 is restricted to 50 Ω by the compliance at Pin 14, so C3 2

needs to be large to form a 5 ms time constant. A tantalum 1

capacitor is used (note polarity). The output of U3a is scaled 0
+1 V per decade, and the X2 gain of U3b raises this to +2 V per
–1
decade, or +100 mV/dB. The differential offset at the output of –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 dBV
31.6m 100m 316m 1m 3.16m 10m 31.6m 100m 316m 1 3.16 V
U2 is low-pass filtered by R6/C7 and R7/C8 and buffered by INPUT AMPLITUDE AT 10kHz
voltage followers U4a and U4b. The 16s open loop time constant
translates to a closed loop high-pass corner of 10 Hz. (This Figure 33. Logarithmic Output and Nonlinearity for Circuit
of Figure 32, for a Square Wave Input at f = 10 kHz

–16– REV. D
AD640

OUTLINE DIMENSIONS
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)

20 11 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
10
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

070706-A
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 33. 20-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.048 (1.22 ) 0.165 (4.19)
0.042 (1.07) 0.056 (1.42)
0.20 (0.51) 0.020 (0.50)
0.042 (1.07) MIN R
3 19
0.021 (0.53)
0.048 (1.22) 4 18
PIN 1 0.050 0.013 (0.33)
0.042 (1.07) IDENTIFIER 0.330 (8.38) BOTTOM
(1.27)
TOP VIEW BSC VIEW
0.032 (0.81) 0.290 (7.37) (PINS UP)
(PINS DOWN)
14
0.026 (0.66)
8
9 13
0.020 0.045 (1.14)
(0.51) 0.356 (9.04) R
R SQ 0.025 (0.64)
0.350 (8.89)
0.120 (3.04)
0.395 (10.03) 0.090 (2.29)
SQ
0.385 (9.78)

COMPLIANT TO JEDEC STANDARDS MO-047-AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 34. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20)
Dimensions shown in inches and (millimeters)

Rev. D | Page 17
 AD640
0.005 (0.13) MIN 0.080 (2.03) MAX

20 11
0.300 (7.62)
PIN 1 0.280 (7.11)
1 10

0.320 (8.13)
1.060 (28.92)
0.060 (1.52) 0.300 (7.62)
0.200 (5.08) 0.990 (25.15)
0.015 (0.38)
MAX

0.150
(3.81)
0.200 (5.08) MIN
0.125 (3.18) 0.015 (0.38)
0.100 0.070 (1.78) SEATING
(2.54) PLANE 0.008 (0.20)
0.023 (0.58) 0.030 (0.76)
0.014 (0.36) BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 35. 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-20)
Dimensions shown in inches and (millimeters)
0.200 (5.08)
0.075 (1.91) REF
0.100 (2.54) REF
0.100 (2.54) REF
0.064 (1.63) 0.095 (2.41) 0.015 (0.38)
0.075 (1.90) MIN
19 3
18 20 4
0.028 (0.71)
0.358 (9.09) 0.358 1
(9.09) 0.011 (0.28) 0.022 (0.56)
0.342 (8.69) BOTTOM
MAX 0.007 (0.18) VIEW
SQ SQ R TYP 0.050 (1.27)
14 8 BSC
0.075 (1.91) 13 9
REF
45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

022106-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 36. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-20-1)
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD640JNZ 0°C to 70°C 20-Lead PDIP N-20
AD640JPZ 0°C to 70°C 20-Lead PLCC P-20
AD640JPZ-REEL7 0°C to 70°C 20-Lead PLCC, 7” Tape and Reel P-20
AD640BE −40°C to +85°C 20-Terminal LCC E-20-1
AD640BPZ −40°C to +85°C 20-Lead PLCC P-20
AD640TD/883B −55°C to +125°C 20-Lead SBDIP D-20
AD640TE/883B −55°C to +125°C 20-Terminal LCC E-20-1
5962-9095502MRA −55°C to +125°C 20-Lead SBDIP D-20
5962-9095502M2A −55°C to +125°C 20-Terminal LCC E-20-1
AD640TCHIPS −55°C to +125°C Die
1 Z = RoHS Compliant Part.

REVISION HISTORY
7/2016—Rev. C to Rev. D
Changes to Specifications Section .................................................. 2
Moved Outline Dimensions .......................................................... 17
Updated Outline Dimensions ....................................................... 17
Moved Ordering Guide ................................................................. 18
Changes to Ordering Guide ......................................................... 18
Rev. D | Page 18
AD640

©1999–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14166-0-7/16

Rev. D | Page 19