Voltage-to-Frequency and

Frequency-to-Voltage Converter
Data Sheet AD650
FEATURES FUNCTIONAL BLOCK DIAGRAM
V/F conversion to 1 MHz
AD650
Reliable monolithic construction VOUT 1 14
OFFSET
INPUT NULL
Very low nonlinearity OP OFFSET
TRIM OFFSET
0.002% typ at 10 kHz +IN 2 AMP 13
NULL
0.005% typ at 100 kHz
–IN 3 12 +VS
0.07% typ at 1 MHz
BIPOLAR
Input offset trimmable to zero OFFSET 4 S1 11
ANALOG
GND
CURRENT
CMOS- or TTL-compatible –VS
1mA
–0.6V
DIGITAL
Unipolar, bipolar, or differential V/F –VS 5 OUT –VS
10
GND
IN
V/F or F/V conversion ONE
SHOT 6
FREQ ONE
9
COMPARATOR
SHOT OUT INPUT
Available in surface mount CAPACITOR COMP

MIL-STD-883 compliant versions available NC 7 8 FOUTPUT

00797-001
NC = NO CONNECT

Figure 1.
PRODUCT DESCRIPTION
The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage The AD650JN and AD650KN are offered in plastic 14-lead DIP
converter) provides a combination of high frequency operation packages. The AD650JP is available in a 20-lead plastic leaded
and low nonlinearity previously unavailable in monolithic form. chip carrier (PLCC). Both plastic packaged versions of the
The inherent monotonicity of the V/F transfer function makes AD650 are specified for the commercial temperature range
the AD650 useful as a high-resolution analog-to-digital converter. (0°C to 70°C). For industrial temperature range (−25°C to
A flexible input configuration allows a wide variety of input +85°C) applications, the AD650AD and AD650BD are offered
voltage and current formats to be used, and an open-collector in ceramic packages. The AD650SD is specified for the full
output with separate digital ground allows simple interfacing to −55°C to +125°C extended temperature range.
either standard logic families or opto-couplers.
PRODUCT HIGHLIGHTS
The linearity error of the AD650 is typically 20 ppm (0.002% of 1. Can operate at full-scale output frequencies up to 1 MHz
full scale) and 50 ppm (0.005%) maximum at 10 kHz full scale. (in addition to having very high linearity).
This corresponds to approximately 14-bit linearity in an analog-
to-digital converter circuit. Higher full-scale frequencies or 2. Can be configured to accommodate bipolar, unipolar, or
longer count intervals can be used for higher resolution differential input voltages, or unipolar input currents.
conversions. The AD650 has a useful dynamic range of six
3. TTL or CMOS compatibility is achieved by using an open
decades allowing extremely high resolution measurements.
collector frequency output. The pull-up resistor can be
Even at 1 MHz full scale, linearity is guaranteed less than
1000 ppm (0.1%) on the AD650KN, BD, and SD grades. connected to voltages up to 30 V.

4. The same components used for V/F conversion can also be

In addition to analog-to-digital conversion, the AD650 can be
used for F/V conversion by adding a simple logic biasing
used in isolated analog signal transmission applications,
network and reconfiguring the AD650.
phased-locked loop circuits, and precision stepper motor speed
controllers. In the F/V mode, the AD650 can be used in 5. Separate analog and digital grounds prevent ground loops
precision tachometer and FM demodulator circuits. in real-world applications.
The input signal range and full-scale output frequency are user- 6. Available in versions compliant with MIL-STD-883.
programmable with two external capacitors and one resistor.
Input offset voltage can be trimmed to zero with an external
potentiometer.

Rev. E Document Feedback

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AD650 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 F/V Conversion .......................................................................... 10

Functional Block Diagram .............................................................. 1 High Frequency Operation ....................................................... 10

Product Description ......................................................................... 1 Decoupling and Grounding ...................................................... 12

Product Highlights ........................................................................... 1 Temperature Coefficients .......................................................... 12

Revision History ............................................................................... 2 Nonlinearity Specification ........................................................ 13

Specifications..................................................................................... 3 PSRR............................................................................................. 14

Absolute Maximum Ratings ............................................................ 5 Other Circuit Considerations ................................................... 14

ESD Caution .................................................................................. 5 Applications..................................................................................... 16

Pin Configurations and Function Descriptions ........................... 6 Differential Voltage-to-Frequency Conversion ...................... 16

Circuit Operation ............................................................................. 7 Autozero Circuit ......................................................................... 16

Unipolar Configuration ............................................................... 7 Phase-Locked Loop F/V Conversion ...................................... 17

Component Selection................................................................... 8 Outline Dimensions ....................................................................... 19

Bipolar V/F .................................................................................. 10 Ordering Guide .......................................................................... 20

Unipolar V/F, Negative Input Voltage ..................................... 10

REVISION HISTORY
3/13—Rev. D to Rev. E
Changes to Figure 13 ...................................................................... 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19

3/06—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Product Highlights....................................................... 1
Changes to Table 1 ............................................................................ 3
Added Pin Function Descriptions Table ...................................... 6
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19

Rev. E | Page 2 of 20
Data Sheet AD650

SPECIFICATIONS
T = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
AD650J/AD650A AD650K/AD650B AD650S
Model Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE
Full-Scale Frequency Range 1 1 1 MHz
Nonlinearity 1
fMAX = 10 kHz 0.002 0.005 0.002 0.005 0.002 0.005 %
fMAX = 100 kHz 0.005 0.02 0.005 0.02 0.005 0.02 %
fMAX = 500 kHz 0.02 0.05 0.02 0.05 0.02 0.05 %
fMAX = 1 MHz 0.1 0.05 0.1 0.05 0.1 %
Full-Scale Calibration Error 2
100 kHz ±5 ±5 ±5 %
1 MHz ± 10 ± 10 ± 10 %
% of
vs. Supply 3 −0.015 +0.015 −0.015 +0.015 −0.015 +0.015 FSR/V
vs. Temperature
A, B, and S Grades
at 10 kHz ±75 ±75 ±75 ppm/°C
at 100 kHz ±150 ±150 ±200 ppm/°C
J and K Grades
at 10 kHz ±75 ±75 ppm/°C
at 100 kHz ±150 ±150 ppm/°C
BIPOLAR OFFSET CURRENT
Activated by 1.24 kΩ Between
Pin 4 and Pin 5 0.45 0.5 0.55 0.45 0.5 0.55 0.45 0.5 0.55 mA
DYNAMIC RESPONSE
Maximum Settling Time for
Full-Scale Step Input 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs
Overload Recovery Time
Step Input 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs 1 pulse of new frequency plus 1 μs
ANALOG INPUT AMPLIFIER
(V/F CONVERSION)
Current Input Range (Figure 4) 0 +0.6 0 +0.6 0 +0.6 mA
Voltage Input Range (Figure 12) −10 0 −10 0 −10 0 V
Differential Impedance 2 MΩ||10 pF 2 MΩ||10 pF 2 MΩ||10 pF
Common-Mode Impedance 1000 MΩ||10 pF 1000 MΩ||10 pF 1000 MΩ||10 pF
Input Bias Current
Noninverting Input 40 100 40 100 40 100 nA
Inverting Input ±8 ±20 ±8 ±20 ±8 ±20 nA
Input Offset Voltage
(Trimmable to Zero) ±4 ±4 ±4 mV
vs. Temperature (TMIN to TMAX) ±30 ±30 ±30 µV/°C
Safe Input Voltage ±VS ±VS ±VS V
COMPARATOR (F/V CONVERSION)
Logic 0 Level −VS −1 −VS −1 −VS −1 V
Logic 1 Level 0 +VS 0 +VS 0 +VS V
Pulse Width Range 4 0.1 (0.3 × tOS) 0.1 (0.3 × tOS) 0.1 (0.3 × tOS) µs
Input Impedance 250 250 250 kΩ
OPEN COLLECTOR OUTPUT
(V/F CONVERSION)
Output Voltage in Logic 0
ISINK ≤ 8 mA, TMIN to TMAX 0.4 0.4 0.4 V
Output Leakage Current in Logic 1 100 100 100 nA
Voltage Range 5 0 36 0 36 0 36 V

Rev. E | Page 3 of 20
AD650 Data Sheet
AD650J/AD650A AD650K/AD650B AD650S
Model Min Typ Max Min Typ Max Min Typ Max Units
AMPLIFIER OUTPUT (F/V CONVERSION)
Voltage Range
(1500 Ω Min Load Resistance) 0 10 0 10 0 10 V
Source Current
(750 Ω Max Load Resistance) 10 10 10 mA
Capacitive Load
(Without Oscillation) 100 100 100 pF
POWER SUPPLY
Voltage, Rated Performance ±9 ±18 ±9 ±18 ±9 ±18 V
Quiescent Current 8 8 8 mA
TEMPERATURE RANGE
Rated Performance
N Package 0 +70 0 +70 °C
D Package −25 +85 −25 +85 −55 +125 °C
1
Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale.
2
Full-scale calibration error adjustable to zero.
3
Measured at full-scale output frequency of 100 kHz.
4
Refer to F/V conversion section of the text.
5
Referred to digital ground.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Rev. E | Page 4 of 20
Data Sheet AD650

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Stresses above those listed under Absolute Maximum Ratings
Total Supply Voltage 36 V may cause permanent damage to the device. This is a stress
Storage Temperature Range −55°C to +150°C rating only; functional operation of the device at these or any
Differential Input Voltage ±10 V other conditions above those indicated in the operational
Maximum Input Voltage ±VS section of this specification is not implied. Exposure to absolute
Open Collector Output Voltage 36 V maximum rating conditions for extended periods may affect
Above Digital GND device reliability.
Current 50 mA
Amplifier Short Circuit to Ground Indefinite
Comparator Input Voltage ±VS

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. E | Page 5 of 20
AD650 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OFFSET

OFFSET
VOUT 1 14 OFFSET NULL

NULL

NULL
VOUT
+IN
+IN 2 OFFSET NULL

NC
13

–IN 3 AD650 12 +VS 3 2 1 20 19

BIBOLAR OFFSET 4 TOP VIEW 11 ANALOG GND
CURRENT PIN 1
(Not to Scale) –IN 4 18 +VS
–VS 5 10 DIGITAL GND INDENTFIER
ONE SHOT 6 9
COMPARATOR NC 5 17 NC
CAPACITOR INPUT
8 FOUTPUT BIPOLAR OFFSET 6 AD650 16 ANALOG GND

00797-010
NC 7
CURRENT TOP VIEW
NC = NO CONNECT NC 7 (Not to scale) 15 NC
–VS 8 14 DIGITAL GND
Figure 2. D-14, N-14 Pin Configurations
9 10 11 12 13

ONE SHOT
CAPACITOR
NC
NC

COMPARATOR
INPUT
FOUTPUT

00797-011
NC = NO CONNECT

Figure 3. P-20 Pin Configuration

Table 2. Pin Function Descriptions

Pin No.
D-14, N-14 P-20 Mnemonic Description
1 2 VOUT Output of Operational Amplifier. The operational amplifier, along with CINT,
is used in the integrate stage of the V to F conversion.
2 3 +IN Positive Analog Input.
3 4 –IN Negative Analog Input.
4 6 BIPOLAR OFFSET On-Chip Current Source. This can be used in conjunction with an external
CURRENT resistor to remove the operational amplifier’s offset.
5 8 –VS Negative Power Supply Input.
6 9 ONE-SHOT The Capacitor, COS, is Connected to This Pin. COS determines the time period
CAPACITOR for the one shot.
7 1, 5, 7, 10, 11, 15, 17 NC No Connect.
8 12 FOUTPUT Frequency Output from AD650.
9 13 COMPARATOR INPUT Input to Comparator. When the input voltage reaches −0.6 V, the one shot is
triggered.
10 14 DIGITAL GND Digital Ground.
11 16 ANALOG GND Analog Ground.
12 18 +VS Positive Power Supply Input.
13, 14 19, 20 OFFSET NULL Offset Null Pins. Using an external potentiometer, the offset of the
operational amplifier can be removed.

Rev. E | Page 6 of 20
Data Sheet AD650

CIRCUIT OPERATION
COS
UNIPOLAR CONFIGURATION INTEGRATOR
CINT

The AD650 is a charge balance voltage-to-frequency converter. IIN

FREQUENCY
In the connection diagram shown in Figure 4, or the block RIN
COMPARATOR OUTPUT
diagram of Figure 5, the input signal is converted into an +
ONE
VIN SHOT
equivalent current by the input resistance RIN. This current is –
exactly balanced by an internal feedback current delivered in –0.6V
S1
short, timed bursts from the switched 1 mA internal current
source. These bursts of current can be thought of as precisely AD650 1mA ± 20% t
tOS
defined packets of charge. The required number of charge

00797-004
packets, each producing one pulse of the output transistor, –VS
depends upon the amplitude of the input signal. Because the Figure 5. Block Diagram
number of charge packets delivered per unit time is dependent
on the input signal amplitude, a linear voltage-to-frequency
CINT
transformation is accomplished. The frequency output is IIN 1mA – I IN
furnished via an open collector transistor. +
VIN RIN
– 1mA
A more rigorous analysis demonstrates how the charge balance
voltage-to-frequency conversion takes place. S1

A block diagram of the device arranged as a V-to-F converter is 1mA

shown in Figure 5. The unit is comprised of an input integrator,

00797-005
a current source and steering switch, a comparator, and a one –VS
shot. When the output of the one shot is low, the current Figure 6. Reset Mode
steering switch S1 diverts all the current to the output of the op
amp; this is called the integration period. When the one shot CINT IIN
IIN
has been triggered and its output is high, the switch S1 diverts 1mA – I IN
+
all the current to the summing junction of the op amp; this is VIN RIN
called the reset period. The two different states are shown in – 1mA
Figure 6 and Figure 7 along with the various branch currents. It
should be noted that the output current from the op amp is the S1

same for either state, thus minimizing transients.

1mA

00797-006
–VS

AD650 Figure 7. Integrate Mode

CINT 1 14
INPUT 20kΩ
OP OFFSET
2 AMP TRIM
13
RESET INTEGRATE
RIN
250kΩ

VIN 3 12 +15V
R3 R1
0.1µF
S1
VOLTS

4 11
ANALOG
1mA GROUND
–VS –0.6V 1µF
–15V 5 OUT 10 VLOGIC ∆V
–VS
0.1µF IN
FREQ ONE
6 9
SHOT OUT COMP
R2
COS DIGITAL
GROUND
00797-003

7 8 FOUT
t

–0.6
00797-007

Figure 4. Connection Diagram for V/F Conversion, Positive Input Voltage

tOS T1

Figure 8. Voltage Across CINT

Rev. E | Page 7 of 20
AD650 Data Sheet
The positive input voltage develops a current (IIN = VIN/RIN) that −3.4 V × COS
charges the integrator capacitor CINT. As charge builds up on t OS = + 300 × 10 −9 sec (6)
− 0.5 × 10 −3 A
CINT, the output voltage of the integrator ramps downward
towards ground. When the integrator output voltage (Pin 1) This simplifies into the timed period equation (see Equation 1).
crosses the comparator threshold (–0.6 V) the comparator
COMPONENT SELECTION
triggers the one shot, whose time period, tOS is determined by
the one-shot capacitor COS. Only four component values must be selected by the user. These
are input resistance RIN, timing capacitor COS, logic resistor R2,
Specifically, the one-shot time period is and integration capacitor CINT. The first two determine the
input voltage and full-scale frequency, while the last two are
t OS = COS × 6.8 × 10 3 sec / F + 3.0 × 10 −7 sec (1)
determined by other circuit considerations.
The reset period is initiated as soon as the integrator output Of the four components to be selected, R2 is the easiest to
voltage crosses the comparator threshold, and the integrator define. As a pull-up resistor, it should be chosen to limit the
ramps upward by an amount current through the output transistor to 8 mA if a TTL
= OS (1 mA − I IN )
dV t maximum VOL of 0.4 V is desired. For example, if a 5 V logic
∆V = t OS × (2)
dt C INT supply is used, R2 should be no smaller than 5 V/8 mA or
625 Ω. A larger value can be used if desired.
After the reset period has ended, the device starts another
integration period, as shown in Figure 8, and starts ramping RIN and COS are the only two parameters available to set the full-
downward again. The amount of time required to reach the scale frequency to accommodate the given signal range. The swing
comparator threshold is given as variable that is affected by the choice of RIN and COS is nonlinearity.
The selection guides of Figure 9 and Figure 10 show this quite
t OS
(1mA − I IN )  1mA  graphically. In general, larger values of COS and lower full-scale
∆V C INT input currents (higher values of RIN) provide better linearity. In
T1 = = = t OS  − 1 (3)
dV IN
 I IN  Figure 10, the implications of four different choices of RIN are
dt C INT shown. Although the selection guide is set up for a unipolar
configuration with a 0 V to 10 V input signal range, the results
The output frequency is now given as can be extended to other configurations and input signal ranges.
1 I IN For a full-scale frequency of 100 kHz (corresponding to 10 V
f OUT = = =
t OS + T1 t OS × 1 mA input), among the available choices RIN = 20 kΩ and COS = 620 pF
(4) gives the lowest nonlinearity, 0.0038%. In addition, the highest
F × Hz VIN / R IN
0.15 frequency that gives the 20 ppm minimum nonlinearity is
A COS + 4.4 × 10 −11 F
approximately 33 kHz (40.2 kΩ and 1000 pF).
Note that CINT, the integration capacitor, has no effect on the For input signal spans other than 10 V, the input resistance
transfer relation, but merely determines the amplitude of the must be scaled proportionately. For example, if 100 kΩ is called
sawtooth signal out of the integrator. out for a 0 V to 10 V span, 10 kΩ would be used with a 0 V to 1 V
One-Shot Timing span, or 200 kΩ with a ±10 V bipolar connection.
A key part of the preceding analysis is the one-shot time period The last component to be selected is the integration capacitor
given in Equation 1. This time period can be broken down into CINT. In almost all cases, the best value for CINT can be calculated
approximately 300 ns of propagation delay and a second time using the equation
segment dependent linearly on timing capacitor COS. When the
10 −4 F / sec
one shot is triggered, a voltage switch that holds Pin 6 at analog C INT = (1000 pF minimum) (7)
ground is opened, allowing that voltage to change. An internal f MAX
0.5 mA current source connected to Pin 6 then draws its
When the proper value for CINT is used, the charge balance
current out of COS, causing the voltage at Pin 6 to decrease
architecture of the AD650 provides continuous integration
linearly. At approximately –3.4 V, the one shot resets itself,
of the input signal, therefore, large amounts of noise and
thereby ending the timed period and starting the V/F
interference can be rejected. If the output frequency is
conversion cycle over again. The total one-shot time period can
measured by counting pulses during a constant gate period,
be written mathematically as
the integration provides infinite normal-mode rejection for
∆V COS frequencies corresponding to the gate period and its harmonics.
t OS = + TGATE DELAY (5)
I DISCHARGE However, if the integrator stage becomes saturated by an
excessively large noise pulse, then the continuous integration of
substituting actual values quoted in Equation 5, the signal is interrupted, allowing the noise to appear at the output.
Rev. E | Page 8 of 20
Data Sheet AD650
If the approximate amount of noise that appears on CINT is known 1MHz
(VNOISE), then the value of CINT can be checked using the following
inequality:

FREQUENCY FULL-SCALE
t OS  1  10 3 A
C INT  (8)
 VS  3V  VNOISE 100kHz
INPUT
RESISTOR
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 V to 1 V signal range, and supply 16.9k
20k
voltages of only ±9 V. The component selection guide of Figure 9
10kHz 40.2k
is used to select 2.0 kΩ for RIN and 1000 pF for COS. This results
in a one-shot time period of approximately 7 μs. Substituting

00797-008
100k
75 kHz into Equation 7 yields a value of 1300 pF for CINT. When
the input signal is near zero, 1 mA flows through the integration 50 100 1000
COS (pF)
capacitor to the switched current sink during the reset phase,
causing the voltage across CINT to increase by approximately 5.5 V. Figure 9. Full-Scale Frequency vs. COS
Because the integrator output stage requires approximately 3 V
INPUT
headroom for proper operation, only 0.5 V margin remains for RESISTOR
1000
integrating extraneous noise on the signal line. A negative noise 16.9k

TYPICAL NONLINEARITY (ppm)

pulse at this time could saturate the integrator, causing an error 20k
in signal integration. Increasing CINT to 1500 pF or 2000 pF
provides much more noise margin, thereby eliminating this
40.2k
potential trouble spot.
100 100k

20

00797-009
50 100 1000
ONE SHOT CAPACITOR
COS (pF)

Figure 10. Typical Nonlinearity vs. COS

Rev. E | Page 9 of 20
AD650 Data Sheet
BIPOLAR V/F Circuit operation for negative input voltages is very similar to
positive input unipolar conversion described in the Unipolar
Figure 11 shows how the internal bipolar current sink is used to Configuration section. For best operating results use Equation 7
provide a half-scale offset for a ±5 V signal range, while providing and Equation 8 in the Component Selection section.
a 100 kHz maximum output frequency. The nominally 0.5 mA
(±10%) offset current sink is enabled when a 1.24 kΩ resistor is F/V CONVERSION
connected between Pin 4 and Pin 5. Thus, with the grounded The AD650 also makes a very linear frequency-to-voltage
10 kΩ nominal resistance shown, a −5 V offset is developed at converter. Figure 13 shows the connection diagram for F/V
Pin 2. Because Pin 3 must also be at −5 V, the current through RIN conversion with TTL input logic levels. Each time the input
is 10 V/40 kΩ = +0.25 mA at VIN = +5 V, and 0 mA at VIN = –5 V. signal crosses the comparator threshold going negative, the one
Components are selected using the same guidelines outlined for shot is activated and switches 1 mA into the integrator input for
the unipolar configuration with one alteration. The voltage a measured time period (determined by COS). As the frequency
across the total signal range must be equated to the maximum increases, the amount of charge injected into the integration
input voltage in the unipolar configuration. In other words, the capacitor increases proportionately. The voltage across the
value of the input resistor RIN is determined by the input voltage integration capacitor is stabilized when the leakage current
span, not the maximum input voltage. A diode from Pin 1 to through R1 and R3 equals the average current being switched
ground is also recommended. This is further discussed in the into the integrator. The net result of these two effects is an
Other Circuit Considerations section. average output voltage that is proportional to the input
frequency. Optimum performance can be obtained by selecting
As in the unipolar circuit, RIN and COS must have low temperature components using the same guidelines and equations listed in
coefficients to minimize the overall gain drift. The 1.24 kΩ the Bipolar V/F section.
resistor used to activate the 0.5 mA offset current should also
have a low temperature coefficient. The bipolar offset current For a more complete description of this application, refer to
has a temperature coefficient of approximately −200 ppm/°C. Analog Devices’ Application Note AN-279.

UNIPOLAR V/F, NEGATIVE INPUT VOLTAGE HIGH FREQUENCY OPERATION

Figure 12 shows the connection diagram for V/F conversion of Proper RF techniques must be observed when operating the
negative input voltages. In this configuration, full-scale output AD650 at or near its maximum frequency of 1 MHz. Lead
frequency occurs at negative full-scale input, and zero output lengths must be kept as short as possible, especially on the one
frequency corresponds with zero input voltage. shot and integration capacitors, and at the integrator summing
junction. In addition, at maximum output frequencies above
A very high impedance signal source can be used because it only 500 kHz, a 3.6 kΩ pull-down resistor from Pin 1 to −VS is
drives the noninverting integrator input. Typical input impedance required (see Figure 14). The additional current drawn through
at this terminal is 1 GΩ or higher. For V/F conversion of positive the pulldown resistor reduces the op amp’s output impedance
input signals using the connection diagram of Figure 4, the and improves its transient response.
signal generator must be able to source the integration current
to drive the AD650. For the negative V/F conversion circuit of
Figure 12, the integration current is drawn from ground
through R1 and R3, and the active input is high impedance.

CINT
AD650
1000pF 1 14
INPUT
OP OFFSET 20kΩ
AMP TRIM
2 13
R1 10kΩ 250kΩ
5kΩ
VIN
3 12 +15V
±5V R3
37.4kΩ 0.1µF
4
S1 11 ANALOG
1mA GND
1.24kΩ –VS –0.6V 1µF
–15V 5
OUT 10 +5V
–VS
0.1µF IN
FREQ ONE DIGITAL
6 9 GND 1kΩ
COS SHOT OUT COMP
330pF
7 8 FOUT
00797-012

Figure 11. Connections for ±5 V Bipolar V/F with 0 kHz to 100 kHz TTL Output
Rev. E | Page 10 of 20
Data Sheet AD650

R3 CINT
R1

AD650
1 14
INPUT
OP OFFSET 20kΩ
AMP TRIM
–VIN 2 13
250kΩ

3 12 +15V
0.1µF
4
S1 11 ANALOG
1mA GND
–VS –0.6V 1µF
–15V 5
OUT 10 +VLOGIC
–VS
0.1µF IN
FREQ ONE DIGITAL
6 9 GND R2
SHOT OUT COMP
COS

00797-013
7 8 FOUT

Figure 12. Connection Diagram for V/F Conversion, Negative Input Voltage

VOUT

AD650
R3 1 14
INPUT
CINT OP OFFSET 20kΩ
AMP TRIM
R1 2 13
250kΩ

3 12 +15V
0.1µF
4
S1 11 ANALOG
1mA –0.6V GND
–VS
–15V 5 10 500Ω 560pF
OUT –VS FIN
0.1µF IN
FREQ 2kΩ 500Ω
ONE +5V
6 9
SHOT OUT COMP
COS 1N914

00797-014
7 8

Figure 13. Connection Diagram for F/V Conversion

1000pF AD650
1 14 OFFSET
INPUT ADJUST
OP OFFSET 20kΩ
GAIN AMP TRIM
2 13
ADJUST 250kΩ
5kΩ
VIN 14.3kΩ
3 12 +15V
0V TO 10V
0.1µF
3.6kΩ S1
4 11 ANALOG
1mA GND PLANE
–VS –0.6V
–15V 5
OUT 10 DIGITAL
–VS 1µF
IN GND
0.1µF FREQ ONE
6 9
SHOT OUT COMP +5V
51pF
510Ω
7 8 FOUT
00797-015

0MHz TO 1MHz

Figure 14. 1 MHz V/F Connection Diagram

Rev. E | Page 11 of 20
AD650 Data Sheet
DECOUPLING AND GROUNDING to the supply side of the pull-up resistor and to the digital
ground (Pin 10). The pull-up resistor should be connected
It is effective engineering practice to use bypass capacitors on directly to the frequency output (Pin 8). The lead lengths on the
the supply-voltage pins and to insert small-valued resistors bypass capacitor and the pull-up resistor should be as short as
(10 Ω to 100 Ω) in the supply lines to provide a measure of possible. The capacitor supplies (or absorbs) the current
decoupling between the various circuits in a system. Ceramic transients, and large ac signals flows in a physically small loop
capacitors of 0.1 μF to 1.0 μF should be applied between the through the capacitor, pull-up resistor, and frequency output
supply-voltage pins and analog signal ground for proper transistor. It is important that the loop be physically small for
bypassing on the AD650. two reasons: first, there is less self-inductance if the wires are
In addition, a larger board level decoupling capacitor of 1 μF to short, and second, the loop does not radiate RFI efficiently.
10 μF should be located relatively close to the AD650 on each The digital ground (Pin 10) should be separately connected to
power supply line. Such precautions are imperative in high the power supply ground. Note that the leads to the digital
resolution, data acquisition applications where users expect to power supply are only carrying dc current and cannot radiate
exploit the full linearity and dynamic range of the AD650. RFI. There can also be a dc ground drop due to the difference in
Although some types of circuits can operate satisfactorily with currents returned on the analog and digital grounds. This does
power supply decoupling at only one location on each circuit not cause any problem. In fact, the AD650 tolerates as much as
board, such practice is strongly discouraged in high accuracy 0.25 V dc potential difference between the analog and digital
analog design. grounds. These features greatly ease power distribution and
Separate digital and analog grounds are provided on the ground management in large systems. Proper technique for
AD650. The emitter of the open collector frequency output grounding requires separate digital and analog ground returns
transistor is the only node returned to the digital ground. All to the power supply. Also, the signal ground must be referred
other signals are referred to analog ground. The purpose of the directly to analog ground (Pin 11) at the package. All of the
two separate grounds is to allow isolation between the high signal grounds should be tied directly to Pin 11, especially the
precision analog signals and the digital section of the circuitry. one-shot capacitor. More information on proper grounding and
As much as several hundred millivolts of noise can be tolerated reduction of interference can be found in “Noise Reduction
on the digital ground without affecting the accuracy of the Techniques in Electronic Systems, 2nd edition” by Henry W. Ott,
VFC. Such ground noise is inevitable when switching the large (John Wiley & Sons, Inc., 1988).
currents associated with the frequency output signal.
TEMPERATURE COEFFICIENTS
At 1 MHz full scale, it is necessary to use a pull-up resistor of The drift specifications of the AD650 do not include
about 500 Ω in order to get the rise time fast enough to provide temperature effects of any of the supporting resistors or
well defined output pulses. This means that from a 5 V logic capacitors. The drift of the input resistors R1 and R3 and the
supply, for example, the open collector output draws 10 mA. timing capacitor COS directly affect the overall temperature
stability. In the application of Figure 5, a 10 ppm/°C input
This much current being switched causes ringing on long resistor used with a 100 ppm/°C capacitor can result in a
ground runs due to the self-inductance of the wires. For maximum overall circuit gain drift of:
instance, 20 gauge wire has an inductance of about 20 nH per
inch; a current of 10 mA being switched in 50 ns at the end of 150 ppm/°C (AD650A) + 100 ppm/°C (COS)
12 inches of 20 gauge wire produces a voltage spike of 50 mV. + 10 ppm/°C (RIN) = 260 ppm/°C
The separate digital ground of the AD650 easily handles these In bipolar configuration, the drift of the 1.24 kΩ resistor used to
types of switching transients. activate the internal bipolar offset current source directly affects
A problem remains from interference caused by radiation of the value of this current. This resistor should be matched to the
electromagnetic energy from these fast transients. Typically, a resistor connected to the op amp noninverting input, Pin 2 (see
voltage spike is produced by inductive switching transients; Figure 11). That is, the temperature coefficients of these two
these spikes can capacitively couple into other sections of the resistors should be equal. If this is the case, then the effects of the
circuit. Another problem is ringing of ground lines and power temperature coefficients of the resistors cancel each other, and the
supply lines due to the distributed capacitance and inductance drift of the offset voltage developed at the op amp noninverting
of the wires. Such ringing can also couple interference into input is solely determined by the AD650. Under these conditions,
sensitive analog circuits. The best solution to these problems is the TC of the bipolar offset voltage is typically −200 ppm/°C and
proper bypassing of the logic supply at the AD650 package. A is a maximum of −300 ppm/°C. The offset voltage always
1 μF to 10 μF tantalum capacitor should be connected directly decreases in magnitude as temperature is increased.

Rev. E | Page 12 of 20
Data Sheet AD650
Other circuit components do not directly influence the accuracy It is not possible to achieve much improvement in performance
of the VFC over temperature changes as long as their actual unless the expected ambient temperature range is known. For
values are not as different from the nominal value as to preclude example, in a constant low temperature application such as
operation. This includes the integration capacitor CINT. A change gathering data in an Arctic climate (approximately −20°C), a
in the capacitance value of CINT simply results in a different rate of COS with a drift of −310 ppm/°C is called for in order to compensate
voltage change across the capacitor. During the integration phase the gain drift of the AD650. However, if that circuit should see
(see Figure 8), the rate of voltage change across CINT has the an ambient temperature of 75°C, then the COS capacitor would
opposite effect that it does during the reset phase. The result is change the gain TC from approximately 0 ppm to 310 ppm/°C.
that the conversion accuracy is unchanged by either drift or
tolerance of CINT. The net effect of a change in the integrator The temperature effects of these components are the same when
capacitor is simply to change the peak-to-peak amplitude of the the AD650 is configured for negative or bipolar input voltages,
sawtooth waveform at the output of the integrator. and for F/V conversion as well.

The gain temperature coefficient of the AD650 is not a constant NONLINEARITY SPECIFICATION
value. Rather, the gain TC is a function of both the full-scale The linearity error of the AD650 is specified by the endpoint
frequency and the ambient temperature. At a low full-scale method. That is, the error is expressed in terms of the deviation
frequency, the gain TC is determined primarily by the stability of from the ideal voltage to frequency transfer relation after
the internal reference (a buried Zener reference). This low speed calibrating the converter at full scale and zero. The nonlinearity
gain TC can be quite effective; at 10 kHz full scale, the gain TC near varies with the choice of one-shot capacitor and input resistor
25°C is typically 0 ± 50 ppm/°C. Although the gain TC changes (see Figure 10). Verification of the linearity specification
with ambient temperature (tending to be more positive at higher requires the availability of a switchable voltage source (or a
temperatures), the drift remains within a ±75 ppm/°C window over DAC) having a linearity error below 20 ppm, and the use of
the entire military temperature range. At full-scale frequencies very long measurement intervals to minimize count
higher than 10 kHz, dynamic errors become much more important uncertainties. Every AD650 is automatically tested for linearity,
than the static drift of the dc reference. At a full-scale frequency and it is not usually necessary to perform this verification,
of 100 kHz and above, these timing errors dominate the gain which is both tedious and time consuming. If it is required to
TC. For example, at 100 kHz full-scale frequency (RIN = 40 kΩ and perform a nonlinearity test either as part of an incoming quality
COS = 330 pF) the gain TC near room temperature is typically screening or as a final product evaluation, an automated bench-
−80 ±50 ppm/°C, but at an ambient temperature near 125°C, the top tester proves useful. Such a system based on Analog
gain TC tends to be more positive and is typically 15 ±50 ppm/°C. Devices’ LTS-2010 is described in “V-F Converters Demand
This information is presented in a graphical form in Figure 15. Accurate Linearity Testing,” by L. DeVito, (Electronic Design,
The gain TC always tends to become more positive at higher March 4, 1982).
temperatures. Therefore, it is possible to adjust the gain TC of
The voltage-to-frequency transfer relation is shown in Figure 16
the AD650 by using a one-shot capacitor with an appropriate
and Figure 17 with the nonlinearity exaggerated for clarity. The
TC to cancel the drift of the circuit. For example, consider the
first step in determining nonlinearity is to connect the endpoints of
100 kHz full-scale frequency. An average drift of −100 ppm/°C
the operating range (typically at 10 mV and 10 V) with a straight
means that as temperature is increased, the circuit produces a
line. This straight line is then the ideal relationship that is desired
lower frequency in response to a given input voltage. This means
from the circuit. The second step is to find the difference between
that the one-shot capacitor must decrease in value as temperature
this line and the actual response of the circuit at a few points
increases in order to compensate the gain TC of the AD650; that
between the endpoints—typically ten intermediate points
is, the capacitor must have a TC of −100 ppm/°C. Now consider
the 1 MHz full-scale frequency. suffices. The difference between the actual and the ideal
response is a frequency error measured in hertz. Finally, these
frequency errors are normalized to the full-scale frequency and
100 TEMPERATURE (°C)
expressed either as parts per million of full scale (ppm) or parts
–50 –25 0 25 50 75 per hundred of full scale (%). For example, on a 100 kHz full
0
100 125
scale, if the maximum frequency error is 5 Hz, the nonlinearity
GAIN TC (ppm/°C)

10kHz is specified as 50 ppm or 0.005%. Typically on the 100 kHz

–100
scale, the nonlinearity is positive and the maximum value
–200 occurs at about midscale (Figure 16). At higher full-scale
100kHz frequencies, (500 kHz to 1 MHz), the nonlinearity becomes “S”
–300 shaped and the maximum value can be either positive or negative.
Typically, on the 1 MHz scale (RIN = 16.9 kΩ, COS = 51 pF) the
–400
nonlinearity is positive below about 2/3 scale and is negative
00797-016

1MHz
above this point. This is shown graphically in Figure 17.
Figure 15. Gain TC vs. Temperature
Rev. E | Page 13 of 20
AD650 Data Sheet
PSRR
100k The power supply rejection ratio is a specification of the change
in gain of the AD650 as the power supply voltage is changed.
OUTPUT FREQUENCY (Hz)

The PSRR is expressed in units of parts-per-million change of

ACTUAL
the gain per percent change of the power supply (ppm/%). For
example, consider a VFC with a 10 V input applied and an
50ppm
IDEAL
output frequency of exactly 100 kHz when the power supply
potential is ±15 V. Changing the power supply to ±12.5 V is a
5 V change out of 30 V, or 16.7%. If the output frequency changes
100 to 99.9 kHz, then the gain has changed 0.1% or 1000 ppm. The
PSRR is 1000 ppm divided by 16.7%, which equals 60 ppm/%.

00797-017
10mV 10V The PSRR of the AD650 is a function of the full-scale operating
INPUT VOLTAGE
frequency. At low full-scale frequencies the PSRR is determined
Figure 16. Exaggerated Nonlinearity at 100 kHz Full Scale
by the stability of the reference circuits in the device and can be
very effective. At higher frequencies, there are dynamic errors
that become more important than the static reference signals,
and consequently the PSRR is not quite as effective. The values
of PSRR are typically 0 ± 20 ppm/% at 10 kHz full-scale frequency
1M
(RIN = 40 kΩ, COS = 3300 pF). At 100 kHz (RIN = 40 kΩ, COS =
330 pF) the PSRR is typically +80 ± 40 ppm/%, and at 1 MHz
OUTPUT FREQUENCY (Hz)

ACTUAL
VOLTAGE TO FREQUENCY
TRANSFER RELATION 600ppm
(RIN = 16.9 kΩ, COS = 51 pF) the PSRR is +350 ± 50 ppm/%.
This information is summarized graphically in Figure 18.
600ppm IDEAL RELATION OTHER CIRCUIT CONSIDERATIONS
The input amplifier connected to Pin 1, Pin 2, and Pin 3 is not a
standard operational amplifier. Rather, the design has been
1k
optimized for simplicity and high speed. The single largest
difference between this amplifier and a normal op amp is the lack
00797-018

10mV 10V of an integrator (or level shift) stage. Consequently, the voltage on
INPUT VOLTAGE
the output (Pin 1) must always be more positive than 2 V below the
Figure 17. Exaggerated Nonlinearity at 1 MHz Full Scale inputs (Pin 2 and Pin 3). For example, in the F-to-V conversion
mode (Figure 13) the noninverting input of the op amp (Pin 2)
is grounded, which means that the output (Pin 1) is not able to
go below –2 V. Normal operation of the circuit shown in Figure 13
never calls for a negative voltage at the output, but users can
1k imagine an arrangement calling for a bipolar output voltage (for
example, ±10 V) by connecting an extra resistor from Pin 3 to a
PSRR (ppm/%)

positive voltage. However, this does not work.

100
Care should be taken under conditions where a high positive
input voltage exists at or before power up. These situations can
cause a latch up at the integrator output (Pin 1). This is a
10
nondestructive latch and, as such, normal operation can be
restored by cycling the power supply. Latch up can be prevented
by connecting two diodes (for example, 1N914 or 1N4148) as
shown in Figure 11, thereby preventing Pin 1 from swinging
00797-019

10k 100k 1M
FULL SCALE FREQUENCY (Hz) below Pin 2.
Figure 18. PSRR vs. Full-Scale Frequency

Rev. E | Page 14 of 20
Data Sheet AD650
A second major difference is that the output only sinks 1 mA to The bipolar offset current is activated by connecting a 1.24 kΩ
the negative supply. There is no pulldown stage at the output resistor between Pin 4 and the negative supply. The resulting
other than the 1 mA current source used for the V-to-F current delivered to the op amp noninverting input is nominally
conversion. The op amp sources a great deal of current from the 0.5 mA and has a tolerance of ±10%. This current is then used
positive supply, and it is internally protected by current limiting. to provide an offset voltage when Pin 2 is tied to ground through
The output of the op amp can be driven to within 3 V of the a resistor. The 0.5 mA that appears at Pin 2 is also flowing
positive supply when it is not sourcing external current. When through the 1.24 kΩ resistor. An external resistor is used to
sourcing 10 mA the output voltage can be driven to within 6 V activate the bipolar offset current source to provide the lowest
of the positive supply. tolerance and temperature drift of the resulting offset voltage.
It is possible to use other values of resistance between Pin 4 and
A third difference between this op amp and a normal device is −VS to obtain a bipolar offset current different from 0.5 mA.
that the inverting input, Pin 3, is bias current compensated and Figure 19 shows the relationship between the bipolar offset
the noninverting input is not bias-current compensated. The current and the value of the resistor used to activate the source.
bias current at the inverting input is nominally zero, but can be
µA
as much as 20 nA in either direction. The noninverting input
typically has a bias current of 40 nA that always flows into the
node (an npn input transistor). Therefore, it is not possible to 1000

BIPOLAR OFFSET CURRENT

match input voltage drops due to bias currents by matching
input resistors. 800

The op amp has provisions for trimming the input offset 600
voltage. A potentiometer of 20 kΩ is connected from Pin 13 to
Pin 14 and the wiper is connected to the positive supply 400
through a 250 kΩ resistor. A potential of about 0.6 V is
established across the 250 kΩ resistor, and the 3 μA current is 200
injected into the null pins. It is also possible to null the op amp
offset voltage by using only one of the null pins and by using a Ω

00797-020
bipolar current either into or out of the null pin. The amount of 500 1000 1500 2000 2500 3000 3500 4000
EXTERNAL RESISTOR
current required is very small—typically less than 3 μA. This
technique is shown in the Applications section of this data Figure 19. Bipolar Offset Current vs. External Resistor
sheet; the autozero circuit uses this technique.

Rev. E | Page 15 of 20
AD650 Data Sheet

APPLICATIONS
DIFFERENTIAL VOLTAGE-TO-FREQUENCY and-hold amplifier to control the offset, and the input voltage to
CONVERSION the VFC is switched between ground and the signal to be
measured via an AD7512DI analog switch. The offset of the
The circuit in Figure 20 accepts a true floating differential input AD650 is adjusted by injecting a current into—or drawing a
signal. The common-mode input, VCM, can be in the range current out of—Pin 13. Note that only one of the offset null pins
+15 V to −5 V with respect to analog ground. The signal input, is used. During the VFC norm mode, the SHA is in the hold
VIN, can be ±5 V with respect to the common-mode input. Both mode and the hold capacitor is very large, 0.1 μF, which holds
inputs are low impedance; the source that drives the common- the AD650 offset constant for a long period of time.
mode input must supply the 0.5 mA drawn by the bipolar offset
current source, and the source that drives the signal input must When the circuit is in the autozero mode, the SHA is in sample
supply the integration current. mode and behaves like an op amp. The circuit is a variation of
the classical two amplifier servo loop, where the output of the
If less common-mode voltage range is required, then a lower device under test (DUT)—here the DUT is the AD650 op
voltage Zener can be used. For example, if a 5 V Zener is used, amp—is forced to ground by the feedback action of the control
the VCM input can be in the range +10 V to −5 V. If the Zener is amplifier—the SHA. Because the input of the VFC circuit is
not used at all, the common-mode range is ±5 V with respect to connected to ground during the autozero mode, the input
analog ground. If no Zener is used, the 10 kΩ pulldown resistor current that can flow is determined by the offset voltage of the
is not needed and the integrator output (Pin 1) is connected AD650 op amp. Because the output of the integrator stage is
directly to the comparator input (Pin 9). forced to ground, it is known that the voltage is not changing (it
AUTOZERO CIRCUIT is equal to ground potential). Therefore, if the output of the
integrator is constant, its input current must be zero, so the
In order to exploit the full dynamic range of the AD650 VFC,
offset voltage has been forced to be zero. Note that the output of
very small input voltages need to be converted. For example, a the DUT could have been forced to any convenient voltage
six decade dynamic range based on a full scale of 10 V requires other than ground. All that is required is that the output voltage
accurate measurement of signals down to 10 μV. In these be known to be constant. Note also that the effect of the bias
situations, a well-controlled input offset voltage is imperative. A current at the inverting input of the AD650 op amp is also
constant offset voltage does not affect dynamic range but simply mulled in this circuit. The 1000 pF capacitor shunting the
shifts all of the frequency readings by a few hertz. However, if 200 kΩ resistor is compensation for the two amplifier servo
the offset should change, it is not possible to distinguish loop. Two integrators in a loop require a single zero for
between a small change in a small input voltage and a drift of compensation. The 3.6 kΩ resistor from Pin 1 of the AD650 to
the offset voltage. Therefore, the usable dynamic range is less. the negative supply is not part of the autozero circuit, but rather,
The circuit shown in Figure 21 provides automatic adjustment it is required for VFC operation at 1 MHz.
of the op amp offset voltage. The circuit uses an AD582 sample-
10V ZENER 1N5240

AD650
1 14
CI INPUT
1000pF OP OFFSET 20kΩ
10kΩ AMP TRIM
VCM 2 13

INPUT 250kΩ
40kΩ
VIN 3 12 +15V
+
0.1µF
1.24kΩ –
S1
4 11 GND
1mA –0.6V +
–VS 0.1µF
–
5 10
OUT –VS
IN
FREQ ONE
6 9
SHOT OUT COMP
COS
330pF
7 8 10kΩ

–15V
FREQUENCY
OUTPUT
0kHz TO 100kHz GND
–
1kΩ 1µF
+
+5V

NOTES
00797-021

1. VCM IS THE COMMON MODE INPUT +15V TO –5V WITH RESPECT TO ANALOG GROUND.
2. VIN IS THE SIGNAL INPUT ±5V WITH RESPECT TO VCM.

Figure 20. Differential Input

Rev. E | Page 16 of 20
Data Sheet AD650
PHASE-LOCKED LOOP F/V CONVERSION
Although the F/V conversion technique shown in Figure 13 is In a phase-locked loop circuit, the oscillator is driven to a
quite accurate and uses only a few extra components, it is very frequency and phase equal to an input reference signal. In
limited in terms of signal frequency response and carrier feed- applications such as a synthesizer, the oscillator output
through. If the carrier (or input) frequency changes frequency is first processed through a programmable “divide by
instantaneously, then the output cannot change very rapidly due N” before being applied to the phase detector as feedback. Here
to the integrator time constant formed by CINT and RIN. While it the oscillator frequency is forced to be equal to “N times” the
is possible to decrease the integrator time constant to provide reference frequency. It is this frequency output that is the
faster settling of the F-to-V output voltage, the carrier desired output signal and not a voltage. In this case, the AD650
feedthrough then becomes larger. For signal frequency response offers compact size and wide dynamic range.
in excess of 2 kHz, a phase-locked F/V conversion technique
such as the one shown in Figure 22 is recommended.

+VS
+VS
10
1 9
1kΩ
2 8
OUTPUT
10kΩ
3 7 3.6kΩ

CAP 1000pF
4
AD582 6
200kΩ
–VS
5 0.1µF
1000pF
–VS INPUT FREQUENCY
VOLTAGE 14 13 1 9 OUTPUT
NULL COMPARATOR FREQUENCY
NULL

–VS 1 14 INPUT OUTPUT

16.9kΩ +IN 8
2 13 3 500Ω
ONE
3 12 –IN SHOT
2 OP +
4 11 10
AMP
COMPARATOR DIGITAL 10µF
5 10 GND
–0.6 VOLT
6 9
0.5mA 1mA
ANALOG
+VS 7
AD7512 8
+VS GND AD650
BIPOLAR
OFFSET –VS COS
4 5 12 11 6
CONTROL
INPUT
0.1µF 51pF
–5 VOLTS VFC NORMAL

00797-022
GND AUTO ZERO 0.1µF
+5V
–15V +15V GND

Figure 21. Autozero Circuit

D TYPE FLIP FLOP

12 10

D1 PR1
Q1 9
1/2 7474

11 CLOCK1 CLEAR1
INPUT 13
CARRIER 1 NAND XOR C R
2 4 51pF 140kΩ
3 6
7486
2 4 1 1 5
1/4 7400 SD211
D2 PR2 CLEAR2 DMOSFET 15pF
G
5
INPUT 1/2 7474 Q2 71.5kΩ S D
CARRIER
3 CLOCK2 B
590kΩ
AD650 AD509
1MHz FULL-SCALE OP AMP
RIN = 16.9k –15V
COS = 51pF
FREQ VOLTS INPUT F/V
00797-023

CINT = 1000pF
OUT TO AD650 VOLTAGE
(UNIPOLAR INPUT) OUTPUT

Figure 22. Phase-Locked Loop F/V Conversion

Rev. E | Page 17 of 20
AD650 Data Sheet
In signal recovery applications of a PLL, the desired output KoKd
ωn = (11)
signal is the voltage applied to the oscillator. In these situations, C
a linear relationship between the input frequency and the
output voltage is desired; the AD650 makes a superb oscillator and damping factor (ζ) is
for FM demodulation. The wide dynamic range and R CK o K d
outstanding linearity of the AD650 VFC allow simple ζ= (12)
2
embodiment of high performance analog signal isolation or
telemetry systems. The circuit shown in Figure 22 uses a digital For the values shown in Figure 22, these relations simplify to a
phase detector that also provides proper feedback in the event natural frequency of 35 kHz with a damping factor of 0.8.
of unequal frequencies. Such phase-frequency detectors (PFDs)
are available in integrated form. For a full discussion of phase- For a simple approach to determine component values for other
lock loop circuits see “Phase Lock Techniques,” 3rd Edition, by PLL frequencies and VFC full-scale voltage, follow these steps:
F.M. Gardner, (John Wiley & Sons, Inc., 1979). 1. Determine Ko (in units of radians per volt second) from the
An analysis of this circuit must begin at the 7474 Dual D flip maximum input carrier frequency fMAX (in hertz) and the
flop. When the input carrier matches the output carrier in both maximum output voltage VMAX.
phase and frequency, the Q outputs of the flip flops rise at 2π × FMAX
Ko = (13)
exactly the same time. With two zeros, and then two ones on V MAX
the inputs of the exclusive or (XOR) gate, the output remains
low keeping the DMOS FET switched off. Also, the NAND gate 2. Calculate a value for C based upon the desired loop
goes low resetting the flip-flops to zero. Throughout this entire bandwidth fn. Note that this is the desired frequency range
cycle, the DMOS integrator gate remains off, allowing the of the output signal. The loop bandwidth (fn) is not the
voltage at the integrator output to remain unchanged from the maximum carrier frequency (fMAX). The signal can be very
previous cycle. However, if the input carrier leads the output narrow even though it is transmitted over a 1 MHz carrier.
carrier by a few degrees, the XOR gate is turned on for the short Ko V ×F
time span that the two signals are mismatched. Because Q2 is C= × 1× 10 −7 (14)
fn 2
Rad × sec
low during the mismatch time, a negative current is fed into the
integrator, causing its output voltage to rise. This in turn where:
increases the frequency of the AD650 slightly, driving the C units = farads
system towards synchronization. In a similar manner, if the fn units = hertz
input carrier lags the output carrier, the integrator is forced Ko units = rad/volt × sec
down slightly to synchronize the two signals.
3. Calculate R to yield a damping factor of approximately 0.8
Using a mathematical approach, the ±25 μA pulses from the using this equation:
phase detector are incorporated into the phase-detector gain (Kd).
fn Rad × Ω
25 μA R= × 2.5 × 10 6 (15)
Kd = = 4 × 10 −6 amperes / radian (9) Ko V
2π
where:
Also, the V/F converter is configured to produce 1 MHz in
R units = ohms
response to a 10 V input so its gain (Ko) is
fn units = hertz
2π × 1× 10 6 Hz radians Ko units = rad/volt × sec
KO = = 6.3 × 10 5 (10)
10 V volt × sec If in actual operation the PLL overshoots or hunts excessively
before reaching a final value, the damping factor can be raised
The dynamics of the phase relationship between the input and
by increasing the value of R. Conversely, if the PLL is
output signals can be characterized as a second order system
overdamped, a smaller value of R should be used.
with natural frequency (ωn).

Rev. E | Page 18 of 20
Data Sheet AD650

OUTLINE DIMENSIONS
0.005 (0.13) MIN 0.080 (2.03) MAX

14 8
0.310 (7.87)
1 0.220 (5.59)
7
PIN 1
0.100 (2.54)
BSC 0.320 (8.13)
0.765 (19.43) MAX 0.290 (7.37)
0.200 (5.08) 0.060 (1.52)
MAX 0.015 (0.38)
0.150
(3.81)
0.200 (5.08) MIN
0.125 (3.18) SEATING 0.015 (0.38)
0.070 (1.78) 0.008 (0.20)
PLANE
0.023 (0.58) 0.030 (0.76)
0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 23. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-14)
Dimensions shown in inches and (millimeters)

0.775 (19.69)
0.750 (19.05)
0.735 (18.67)

14 8 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
7
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.110 (2.79) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
070606-A

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 24. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
Dimensions shown in inches and (millimeters)

Rev. E | Page 19 of 20
AD650 Data Sheet
0.180 (4.57)
0.048 (1.22 ) 0.165 (4.19)
0.042 (1.07) 0.056 (1.42)
0.20 (0.51) 0.020 (0.50)
0.042 (1.07) MIN R
3 19
0.021 (0.53)
0.048 (1.22) 4 18
PIN 1 0.050 0.013 (0.33)
0.042 (1.07) IDENTIFIER 0.330 (8.38) BOTTOM
(1.27)
TOP VIEW BSC VIEW
0.032 (0.81) 0.290 (7.37) (PINS UP)
(PINS DOWN) 0.026 (0.66)
8 14
9 13
0.020 0.045 (1.14)
(0.51) 0.356 (9.04) R
R SQ 0.025 (0.64)
0.350 (8.89)
0.120 (3.04)
0.395 (10.03) 0.090 (2.29)
SQ
0.385 (9.78)

COMPLIANT TO JEDEC STANDARDS MO-047-AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20)
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Gain Tempco
ppm/°C 1 MHz Temperature Package
Model1 100 kHz Linearity Range Package Description Option
AD650JN 150 typ 0.1% typ 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD650JNZ 150 typ 0.1% typ 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD650KN 150 typ 0.1% max 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD650KNZ 150 typ 0.1% max 0°C to 70°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
AD650JP 150 typ 0.1% typ 0°C to 70°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
AD650JPZ 150 typ 0.1% typ 0°C to 70°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20
AD650AD 150 max 0.1% typ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD650BD 150 max 0.1% max −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD650SD 200 max 0.1% max −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD650SD/883B 200 max 0.1% max −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD650ACHIPS Die
1
Z = RoHS Compliant Part.

©2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00797-0-3/13(E)

Rev. E | Page 20 of 20