lOMoARcPSD|27739474

21CS43- Module-5

ARM Microcontrollers & Embedded Systems (Visvesvaraya Technological University)

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ARM Instruction Set

Computer
p Organization
g z and Assemblyy Languages
g g
Yung-Yu Chuang

with slides by Peng-Sheng Chen

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Int roduct ion

• The ARM processor is easy t o program at t he
assembly level
level. (It is a RISC)
• We will learn ARM assembly programming at t he
user level
l l andd run it on a GBA emulat
l t or.

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ARM programmer model

• The st at e of an ARM syst em is det ermined by
t he cont ent of visible regist ers and memory.
memory
• A user-mode program can see 15 32-bit general-
purpose registi t ers (R0
(R0-R14),
R14) program countt er
(PC) and CPSR.
• Inst ruct ion set defines t he operat ions t hat can
change t he st at e.

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Memory syst em
• Memory is a linear array of 0x00000000 00
byt es addressed from 0 t o 0x00000001 10
232-1 20
0x00000002
• Word,
W d h half-word,
lf d bbytt e 0x00000003 30
• Lit t le-endian 0x00000004
FF
FF
0x00000005
FF
0x00000006

00
0 FFFFFFFD
0xFFFFFFFD
00
0xFFFFFFFE 00
0xFFFFFFFF

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Byt e ordering
• Big Endian
– Least significant byt e has 0x00000000 00
highest address 0x00000001 10
Word address 0x00000000 20
0 00000002
0x00000002
Value: 00102030 30
0x00000003
• Lit t le Endian FF
– Least significant byt e has 0x00000004
FF
lowest address 0x00000005
Word address 0x00000000 FF
0x00000006
Value: 30201000
00
0xFFFFFFFD
00
0xFFFFFFFE 00
0xFFFFFFFF
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ARM programmer model

0x00000000 00
0x00000001 10
R0 R1 R2 R3 20
0x00000002
R4 R5 R6 R7 0x00000003 30
FF
R8 R9 R10 R11 0 00000004
0x00000004
FF
R12 R13 R14 PC 0x00000005
FF
0x00000006

00
0xFFFFFFFD
00
0xFFFFFFFE
0 00
0xFFFFFFFF
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Inst ruct ion set

ARM inst ruct ions
are all 32-bit
32 bit long
(except for
Thumb mode).
mode)
There are 232
possible machine
inst ruct ions.
Fort unat ely
ely, t hey
are st ruct ured.

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Feat ures of ARM inst ruct ion set

• Load-st ore archit ect ure
• 3 dd
3-address iinst ruct iions
• Condit ional execut ion of every inst ruct ion
• Possible t o load/ st ore mult iple regist ers at
once
• Possible t o combine shift and ALU operat ions in
a single inst ruct ion

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Inst ruct ion set

• Dat a processing
• Dat
D a movement
• Flow cont rol

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Dat a processing
• They are move, arit hmet ic, logical, comparison
and mult iply inst ruct ions.
ions
• Most dat a processing inst ruct ions can process
one off t h
heir
i operands
d using
i thhe bbarrell shift
hift er.
• General rules:
– All operands are 32-bit , coming
from regist ers or lit erals.
– The result , if any, is 32-bit and
placed in a regist er (wit h t he
exceptt iion for
f llong
g multlt iiply
l
which produces a 64-bit result )
– 3-address
3 address format

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Inst ruct ion set

MOV<cc><S> Rd, <operands>

MOVCS R0, R1 @ if carry is set

@ then R0:=R1

MOVS R0, #0 @ R0:=0

@ Z=1,
, N=0
@ C, V unaffected

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Condit ional execut ion

• Almost all ARM inst ruct ions have a condit ion
field which allows it t o be execut ed
condit ionally.
movcs R0,0 R1 1

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Regist er movement
immediat e,regist er,shift

• MOV R0, R2 @ R0 = R2
• MVN R0,
0 R22 @ R0
0 = ~R22

move negatt ed
d

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Addressing modes
• Regist er operands
ADD R0
R0, R1
R1, R2

• Immediat e operands
a lit eral; most can be represent ed
by (0..255)x22n 0<n<12
ADD R3
R3, R3
R3, #1 @ R3:=R3+1
AND R8, R7, #0xff @ R8=R7[7:0]

a hexadecimal lit eral

This is assembler dependent synt ax.
ax

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Shift ed regist er operands

• One operand t o ALU is
rout ed t hrough t he Barrel
shift er. Thus, t he operand
can be modified before it
is used. Useful for fast
mult ipliat
p ion and dealing g
wit h list s, t able and ot her
complex dat a st ruct ure.
(similar t o t he
displacement addressing • Some inst ruct ions (e.g.
moded iin C CISC.)
SC MUL CLZ
MUL, CLZ, QADD) do
not read barrel shift er.

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Shift ed regist er operands

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Logical shift left

C regist er 0
MOV R0, R2, LSL #2 @ R0:=R2<<2
@ R2 unchanged
g
Example: 0…0 0011 0000
Before R2=0x00000030
R2 0x00000030
After R0=0x000000C0
R2=0x00000030

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Logical shift right

0 regist er C
MOV R0, R2, LSR #2 @ R0:=R2>>2
@ R2 unchanged
g
Example: 0…0 0011 0000
Before R2=0x00000030
R2 0x00000030
After R0=0x0000000C
R2=0x00000030

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Arit hmet ic shift right

MSB regist er C
MOV R0, R2, ASR #2 @ R0:=R2>>2
@ R2 unchanged
g
Example: 1010 0…0 0011 0000
Before R2=0xA0000030
R2 0xA0000030
After R0=0xE800000C
R2=0xA0000030

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Rot at e right

regist er

MOV R0, R2, ROR #2 @ R0:=R2 rotate

@ R2 unchanged
g
Example: 0…0 0011 0001
Before R2=0x00000031
R2 0x00000031
After R0=0x4000000C
R2=0x00000031

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Rot at e right ext ended

C regist er C
MOV R0, R2, RRX @ R0:=R2 rotate
@ R2 unchanged
g
Example: 0…0 0011 0001
Before R2=0x00000031,
R2 0x00000031, C=1
C 1
After R0=0x80000018, C=1
R2=0x00000031

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Shift ed regist er operands

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Shift ed regist er operands

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Shift ed regist er operands

• It is possible t o use a regist er t o specify t he
number of bit s t o be shift ed; only t he bot t om 8
bit s of t he regist er are significant .
@ array i
index
d calculation
l l ti
ADD R0, R1, R2, LSL R3 @ R0:=R1+R2*2R3

@ fast multiply R2=35xR0

ADD R0, R0, R0, LSL #2 @ R0’=5xR0
RSB R2, R0, R0, LSL #3 @ R2 =7xR0’

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Mult iplicat ion

MOV R1, #35
MUL R2
R2, R0
R0, R1
or
ADD R0,
0 R0,
0 R0,
0 LSL #2 @ R0’=5xR0
0’ 5 0
RSB R2, R0, R0, LSL #3 @ R2 =7xR0’

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Shift ed regist er operands

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Encoding dat a processing inst ruct ions

31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond 00 # opcode S Rn Rd operand 2

destination register
first operand register
set condition codes
arithmetic/logic function

25 11 8 7 0

1 # t
#rot 8 bit iimmediate
8-bit di t

immediate alignment
11 7 6 5 4 3 0

#shift Sh 0 Rm

25 immediate shift length

0 shift
f type
second operand register
11 8 7 6 5 4 3 0

Rs 0 Sh 1 Rm

register shift length

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Arit hmet ic
• Add and subt ract ion

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Arit hmet ic
• ADD R0, R1, R2 @ R0 = R1+R2
• ADC R0
R0, R1
R1, R2 @ R0 = R1+R2+C
R1 R2 C
• SUB R0, R1, R2 @ R0 = R1-R2
• SBC R0, R1, R2 @ R0 = R1-R2-!C
• RSB R0, R1, R2 @ R0 = R2-R1
R2 R1
• RSC R0, R1, R2 @ R0 = R2-R1-!C
-11 -128
128 127 0
-5 3

255 128 127 0

3-5=3+(-5) → sum<=255 → C=0 → borrow
5-3=5+(-3) → sum > 255 → C=1 → no borrow

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Arit hmet ic

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Arit hmet ic

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Set t ing t he condit ion codes

• Any dat a processing inst ruct ion can set t he
condit ion codes if t he programmers wish it t o

64-bit addit ion

R1 R0
ADDS R2, R2, R0
+ R3 R2
ADC R3
R3, R3
R3, R1
R3 R2

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Logical

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Logical
• AND R0, R1, R2 @ R0 = R1 and R2
• ORR R0
R0, R1
R1, R2 @ R0 = R1 or R2
• EOR R0, R1, R2 @ R0 = R1 xor R2
• BIC R0, R1, R2 @ R0 = R1 and (~R2)

bit clear: R2 is a mask ident ifying which

bit s of R1 will be cleared t o zero
R1=0x11111111 R2=0x01100101

BIC R0, R1, R2

R0=0x10011010

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Logical

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Comparison
• These inst ruct ions do not generat e a result , but
set condit ion code bit s (N
(N, Z
Z, C
C, V) in CPSR
CPSR.
Oft en, a branch operat ion follows t o change t he
program flow.
flow

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Comparison
compare
• CMP R1
R1, R2 @ set cc on R1-R2
compare negat ed
• CMN R1
R1, R2 @ set cc on R1+R2
bit t est
• TST R1 R1, R2 @ set cc on R1 and R2
t est equal
• TEQ R1 R1, R2 @ set
t cc on R1 xor R2

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Comparison

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Mult iplicat ion

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Mult iplicat ion

• MUL R0, R1, R2 @ R0 = (R1xR2)[31:0]

• Feat ures:
– Second
S d operand d can’’ t b
be iimmediat
di t e
– The result regist er must be different from
t he first operand
y
– Cycles depends
p on core t yp
ype
– If S bit is set , C flag is meaningless
• See t he reference manual (4.1.33)
(4 1 33)

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Mult iplicat ion

• Mult iply-accumulat e (2D array indexing)
MLA R4 R4, R3
R3, R2
R2, R1 @ R4 = R3xR2+R1

• M
Mult
lt iiply
l wit
it h a constt antt can oft
ft en b
be more
efficient ly implement ed using shift ed regist er
operand
MOV R1, #35
MUL R2 R2, R0
R0, R1
or
ADD R0, R0, R0, LSL #2 @ R0’=5xR0
RSB R2, R0, R0, LSL #3 @ R2 =7xR0’

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Mult iplicat ion

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Mult iplicat ion

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Flow cont rol inst ruct ions

• Det ermine t he inst ruct ion t o be execut ed next

pc-relat ive offset wit hin 32MB

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Flow cont rol inst ruct ions

• Branch inst ruct ion
B l b l
label
…
label: …

• Condit ional branches

MOV R0, #0
loop: …
ADD R0
R0, R0
R0, #1
CMP R0, #10
BNE loop

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Branch condit ions

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Branches

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Branch and link

• BL inst ruct ion save t he ret urn address t o R14
(lr)

BL sub @ call sub

CMP R1, #5 @ return to here
MOVEQ R1, #0
…
sub: … @ sub entry point
…
MOV PC, LR @ return

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Branch and link

BL sub1 @ call sub1
…
use st ack t o save/ rest ore t he ret urn address and regist ers

sub1: STMFD R13!, {R0-R2,R14}

BL sub2
…
LDMFD R13!,
, {
{R0-R2,PC}
, }

sub2: …
…
MOV PC
PC, LR

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Condit ional execut ion

CMP R0, #5
BEQ b
bypass
pass @ if (R0!
(R0!=5)
5) {
ADD R1, R1, R0 @ R1=R1+R0-R2
SUB R1, R1, R2 @ }
bypass: …

CMP R0,, #5 smaller and fast er

ADDNE R1, R1, R0
SUBNE R1
R1, R1
R1, R2

Rule of t humb: if t he condit ional sequence

q is t hree inst ruct ions
or less, it is bet t er t o use condit ional execut ion t han a branch.

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Condit ional execut ion

if ((R0==R1) && (R2==R3)) R4++

CMP R0, R1
BNE skip
CMP R2, R3
BNE skip
ADD R4, R4, #1
skip: …

CMP R0
R0, R1
CMPEQ R2, R3
ADDEQ R4
R4, R4
R4, #1

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Dat a t ransfer inst ruct ions

• Move dat a bet ween regist ers and memory
• Three
Th basic
b i forms
f
– Single regist er load/ st ore
– Mult iple regist er load/ st ore
– Single regist er swap: SWP(B), at omic
inst ruct ion for semaphore

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Single regist er load/ st ore

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Single regist er load/ st ore

No STRSB/STRSH since STRB/STRH st ores bot h

signed/
i d/ unsigned
i d ones

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Single regist er load/ st ore

• The dat a it ems can be a 8-bit byt e, 16-bit half-
word or 32-bit
32 bit word.
word Addresses must be
boundary aligned. (e.g. 4’ s mult iple for
LDR/STR)

LDR R0, [R1] @ R0 := mem32[R1]

STR R0, [R1] @ mem32[R1] := R0

LDR, , LDRB for 32,, 16,, 8 bit s

, LDRH,
STR, STRH, STRB for 32, 16, 8 bit s

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Addressing modes
• Memory is addressed by a regist er and an offset .
LDR R0
R0, [R1] @ mem[R1]
[R1]
• Three ways t o specify offset s:
– Immediat e
LDR R0, [R1, #4] @ mem[R1+4]
– Regist
R i er
LDR R0, [R1, R2] @ mem[R1+R2]
– Scaled regist er @ mem[R1+4*R2]
[R1+4*R2]
LDR R0, [R1, R2, LSL #2]

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Addressing modes
• Pre-index addressing ( LDR R0, [R1, #4])
wit
i h
hout a writ
i eback
b k
• Aut o-indexing addressing ( LDR R0, [R1, #4]!)
Pre-index wit h writ eback
calculat ion before accessing wit h a writ eback
• Post -index addressing ( LDR R0, [R1], #4)
calculat
l l t ion
i aftft er accessing
i witit h a writ
it eback
b k

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Pre-index addressing
LDR R0, [R1, #4] @ R0=mem[R1+4]
@ R1 unchanged
nchanged

LDR R0, [R1, ]

R1 +
R0

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Aut o-indexing addressing

LDR R0, [R1, #4]! @ R0=mem[R1+4]
@ R1
R1=R1+4
R1+4

No ext ra t ime;; Fast ;

LDR R0, [R1, ]!

R1 +
R0

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Post -index addressing

LDR R0, R1, #4 @ R0=mem[R1]
@ R1
R1=R1+4
R1+4

LDR R0,[R1],

R1 R0

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Comparisons
• Pre-indexed addressing
LDR R0
R0, [R1,
[R1 R2] @ R0=mem[R1+R2]
@ R1 unchanged
• Aut o-indexing
o indexing addressing
LDR R0, [R1, R2]! @ R0=mem[R1+R2]
@ R1
R1=R1+R2
R1+R2
• Post -indexed addressing
LDR R0, [R1], R2 @ R0=mem[R1]
@ R1=R1+R2

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Example

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Example

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Example

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Summary of addressing modes

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Summary of addressing modes

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Summary of addressing modes

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Summary of addressing modes

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Load an address int o a regist er

• Not e t hat all addressing modes are regist er-
offset ed
ed. Can we issue LDR R0R0, Table? The
pseudo inst ruct ion ADR loads a regist er wit h an
address
table: .word 10
…
ADR R0, table

• Assembler t ransfer p
pseudo inst ruct ion int o a
sequence of appropriat e inst ruct ions
sub r0 pc
r0, pc, #12

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Applicat ion
ADR R1, table
table
loop
loop: LDR R0
R0, [R1]
R1
ADD R1, R1, #4
@ operations on R0
…

ADR R1,
, table
loop: LDR R0, [R1], #4

@ operations on R0
…

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Mult iple regist er load/ st ore

• Transfer a block of dat a more efficient ly.
• Used
U d forf procedure
d ent ry andd exit
i ffor saving
i
and rest oring workspace regist ers and t he
rett urn address
dd
• For ARM7, 2+Nt cycles (N:#words, t:t ime for a
word for sequent ial access). Increase int errupt
lat ency since it can’ t be int errupt ed.
regist ers are arranged an in increasing order; see manual
LDMIA R1, {R0, R2, R5} @ R0 = mem[R1]
@ R2 = mem[r1+4]
@ R5 = mem[r1+8]

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDM load multiple registers
STM store m
multiple
ltiple registers

suffix meaning
IA increase after
IB increase before
DA decrease after
DB decrease before

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 lOMoARcPSD|27739474

Addressing modes

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDM<mode> Rn, {<registers>}
IA: addr:=Rn
IB: addr:=Rn+4
DA: addr:=Rn-#<registers>*4+4
DB: addr:=Rn-#<registers>*4
#
For each Ri in <registers>
IB: addr:=addr+4
DB: addr:=addr-4
Ri:=M[addr]
IA: addr:=addr+4 Rn
DA: addr:=addr-4 R1
<!>:
! Rn:=addr R2
R3

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDM<mode> Rn, {<registers>}
IA: addr:=Rn
IB: addr:=Rn+4
DA: addr:=Rn-#<registers>*4+4
DB: addr:=Rn-#<registers>*4
#
For each Ri in <registers>
IB: addr:=addr+4
DB: addr:=addr-4
Ri:=M[addr]
IA: addr:=addr+4 Rn
DA: addr:=addr-4
<!>:
! Rn:=addr R1
R2
R3

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDM<mode> Rn, {<registers>}
IA: addr:=Rn
IB: addr:=Rn+4
DA: addr:=Rn-#<registers>*4+4
DB: addr:=Rn-#<registers>*4
#
For each Ri in <registers>
IB: addr:=addr+4 R1
DB: addr:=addr-4 R2
Ri:=M[addr]
R3
IA: addr:=addr+4 Rn
DA: addr:=addr-4
<!>:
! Rn:=addr

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDM<mode> Rn, {<registers>}
IA: addr:=Rn
IB: addr:=Rn+4
DA: addr:=Rn-#<registers>*4+4
DB: addr:=Rn-#<registers>*4
#
For each Ri in <registers> R1
IB: addr:=addr+4 R2
DB: addr:=addr-4 R3
Ri:=M[addr]
IA: addr:=addr+4 Rn
DA: addr:=addr-4
<!>:
! Rn:=addr

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDMIA R0, {R1,R2,R3}
or
LDMIA R0, {R1-R3}
addr dat a
0x010 10
R0
R1: 10 0x014 20
R2: 20 0x018 30
R3: 30 0x01C 40
R0: 0x10 0x020 50
0x024 60

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDMIA R0!, {R1,R2,R3}

addr dat a
0x010 10
R0
R1: 10 0x014 20
R2: 20 0x018 30
R3: 30 0x01C 40
R0: 0x01C 0x020 50
0x024 60

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDMIB R0!, {R1,R2,R3}

addr dat a
0x010 10
R0
R1: 20 0x014 20
R2: 30 0x018 30
R3: 40 0x01C 40
R0: 0x01C 0x020 50
0x024 60

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDMDA R0!, {R1,R2,R3}

addr dat a
0x010 10
R1: 40 0x014 20
R2: 50 0x018 30
R3: 60 0x01C 40
R0: 0x018 0x020 50
R0 0x024 60

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 lOMoARcPSD|27739474

Mult iple load/ st ore regist er

LDMDB R0!, {R1,R2,R3}

addr dat a
0x010 10
R1: 30 0x014 20
R2: 40 0x018 30
R3: 50 0x01C 40
R0: 0x018 0x020 50
R0 0x024 60

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 lOMoARcPSD|27739474

Example

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 lOMoARcPSD|27739474

Example

LDMIA r0!, {r1-r3}

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 lOMoARcPSD|27739474

Example

LDMIB r0!, {r1-r3}

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 lOMoARcPSD|27739474

Applicat ion
• Copy a block of memory
– R9
R9: address
dd off t h
he source
– R10: address of t he dest inat ion
– R11:
R11 endd address
dd off t h
he source

loop: LDMIA R9!, {R0-R7}

STMIA R10!, {R0-R7}
CMP R9, R11
BNE loop

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 lOMoARcPSD|27739474

Applicat ion
• St ack (full: point ing t o t he last used; ascending:
grow t owards increasing memory addresses)
mode POP =LDM PUSH =STM
Full ascending (FA) LDMFA LDMDA STMFA STMIB
Full descending (FD) LDMFD LDMIA STMFD STMDB
Empt y ascending (EA) LDMEA LDMDB STMEA STMIA
E ty d
Empt descending
di ((ED)) LDMED LDMIB STMED STMDA

LDMFD R13!
R13!, {R2
{R2-R9}
R9} @ used for ATPCS
… @ modify R2-R9
STMFD R13!, {R2-R9}

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 lOMoARcPSD|27739474

Example

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 lOMoARcPSD|27739474

Swap inst ruct ion

• Swap bet ween memory and regist er. At omic
operat ion prevent ing any ot her inst ruct ion from
reading/ writ ing t o t hat locat ion unt il it
complet es

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 lOMoARcPSD|27739474

Example

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 lOMoARcPSD|27739474

Applicat ion

Process A OS Process B

While (1) { While (1) {

S=0/ 1
if (s==0)
(s 0) { if (s==0)
(s 0) {
s=1; s=1;
} }
} }
// use the // use the
// resource // resource

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 lOMoARcPSD|27739474

Soft ware int errupt

• A soft ware int errupt inst ruct ion causes a
soft ware int errupt except ion
ion, which provides a
mechanism for applicat ions t o call OS rout ines.

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 lOMoARcPSD|27739474

Example

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 lOMoARcPSD|27739474

Load const ant s

• No ARM inst ruct ion loads a 32-bit const ant int o
a regist er because ARM inst ruct ions are 32-bit
32 bit
long. There is a pseudo code for t his.

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 lOMoARcPSD|27739474

Immediat e numbers
31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond 00 # opcode S Rn Rd operand 2

destination register
first operand register
v=n ror 2r set condition codes
arithmetic/logic function

25 11 r 8 7 n 0

1 # t
#rot 8 bit iimmediate
8-bit di t

immediate alignment
11 7 6 5 4 3 0

#shift Sh 0 Rm

25 immediate shift length

0 shift
f type
second operand register
encoding for 11 8 7 6 5 4 3 0

dat a processing Rs 0 Sh 1 Rm

inst ruct ions register shift length

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 lOMoARcPSD|27739474

Load const ant s

• Assemblers implement t his usually wit h t wo
opt ions depending on t he number you t ry t o
load.

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 lOMoARcPSD|27739474

Load const ant s

• Assume t hat you want t o load 511 int o R0
–CConstt ructt in
i mult
lt iple
i l iinstt ructt iions
mov r0, #256
add
dd r0, 0 #255
– Load from memory; declare L511 .word 511
ldr r0, L511 ldr r0, [pc, #0]#
• Guideline: if you can const ruct it in t wo
inst ruct ions, do it ; ot herwise, load it .
• The assembler decides for you y
ldr r0, =255 mov r0, 255
ldr r0,
, =511 ldr r0,
, [p
[pc,, #4]
]

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 lOMoARcPSD|27739474

PC-relat ive modes

Impossible t o use
direct addressing

encoding for
dat a t ransfer
inst ruct ions
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 lOMoARcPSD|27739474

PC-relat ive addressing

main:
MOV R0, #0
ADR R1, a @ add r1, pc, #4
STR R0
R0, [R1]
PC SWI #11
a: .word
word 100
.end

fet ch decode exec

fet ch decode exec

fet ch decode exec

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 lOMoARcPSD|27739474

Inst ruct ion set

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