TC9400
TC9400
TC9401
TC9402
Voltage-To-Frequency/Frequency-To-Voltage Converters
FEATURES GENERAL DESCRIPTION
Voltage-to-Frequency The TC9400/TC9401/TC9402 are low-cost voltage-to-
frequency (V/F) converters utilizing low power CMOS
■ Choice of Guaranteed Linearity:
technology. The converters accept a variable analog input
TC9401 ......................................................... 0.01%
signal and generate an output pulse train whose frequency
TC9400 ......................................................... 0.05%
is linearly proportional to the input voltage.
TC9402 ......................................................... 0.25%
The devices can also be used as highly-accurate fre-
■ DC to 100 kHz (F/V) or 1Hz to 100kHz (V/F)
quency-to-voltage (F/V) converters, accepting virtually any
■ Low Power Dissipation .......................... 27mW Typ
input frequency waveform and providing a linearly-propor-
■ Single/Dual Supply Operation .................................
tional voltage output.
+ 8V to + 15V or ± 4V to ± 7.5V
A complete V/F or F/V system only requires the addition
■ Gain Temperature Stability ......... ± 25 ppm/°C Typ.
of two capacitors, three resistors, and reference voltage.
■ Programmable Scale Factor
TC9400
Integrator
Capacitor Integrator Threshold One
OpAmp Detector Shot
RIN
Input
Voltage
IIN Pulse Output
IREF
Reference
Voltage
TC9400
TC9401
TC9402
ELECTRICAL CHARACTERISTICS: VDD = +5V, VSS = – 5V, VGND = 0V, VREF = – 5V, RBIAS = 100kΩ,
Full Scale = 10kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified (– 40°C to +85°C
for E device, 0°C to +70°C for C device).
VOLTAGE-TO-FREQUENCY TC9401 TC9400 TC9402
Parameter Definition Min Typ Max Min Typ Max Min Typ Max Unit
Accuracy
Linearity 10 kHz Output Deviation From Straight — 0.004 0.01 — 0.01 0.05 — 0.05 0.25 % Full
Line Between Normalized Zero Scale
and Full-Scale Input
Linearity 100 kHz Output Deviation From Straight — 0.04 0.08 — 0.1 0.25 — 0.25 0.5 % Full
Line Between Normalized Zero Scale
Reading and Full-Scale Input
Gain Temperature Variation in Gain A Due to — ± 25 ± 40 — ± 25 ± 40 — ± 50 ± 100 ppm/°C
Drift (Note 1) Temperature Change Full Scale
Gain Variance Variation From Ideal Accuracy — ± 10 – — ± 10 — — ± 10 – % of
Nominal
Zero Offset (Note 2) Correction at Zero Adjust for Zero — ± 10 ± 50 — ± 10 ± 50 — ± 20 ± 100 mV
Output When Input is Zero
Zero Temperature Variation in Zero Offset Due to — ± 25 ± 50 — ± 25 ± 50 — ± 50 ± 100 µV/°C
Drift (Note 1) Temperature Change
Analog Input
IIN Full Scale Full-Scale Analog Input Current to — 10 — — 10 — 10 — µA
Achieve Specified Accuracy
IIN Overrange Overrange Current — — 50 — — 50 — — 50 µA
Response Time Settling Time to 0.1% Full Scale — 2 — — 2 — — 2 — Cycle
Digital Section
VSAT @ IOL = 10mA Logic "0" Output Voltage (Note 3) — 0.2 0.4 — 0.2 0.4 — 0.2 0.4 V
VOUT Max – VOUT Voltage Range Between Output — — 18 — — 18 — — 18 V
Common (Note 4) and Common
Pulse Frequency — 3 — — 3 — — 3 — µsec
Output Width
TC9400
TC9401
TC9402
ELECTRICAL CHARACTERISTICS: (Cont.) VDD = +5V, VSS = – 5V, VGND = 0, VREF = – 5V, RBIAS = 100kΩ,
Full Scale = 10kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified – 40°C to +85°C for
E device, 0°C to +70°C for C device.
FREQUENCY-TO-VOLTAGE TC9401 TC9400 TC9402
Parameter Definition Min Typ Max Min Typ Max Min Typ Max Unit
Supply Current
IDD Quiescent Current Required From Positive
(Note 5) Supply During Operation — 1.5 6 — 1.5 6 — 3 10 mA
ISS Quiescent Current Required From Negative
(Note 5) Supply During Operation — – 1.5 – 6 — – 1.5 – 6 –3 – 10 mA
VDD Supply Operating Range of Positive Supply 4 — 7.5 4 — 7.5 4 — 7.5 V
VSS Supply Operating Range of Negative Supply –4 — – 7.5 – 4 — – 7.5 –4 — – 7.5 V
Reference Voltage
VREF –VSS Range of Voltage Reference Input – 2.5 — — – 2.5 — — – 2.5 — — V
Accuracy
Nonlinearity (Note 10) Deviation From Ideal Transfer — 0.01 0.02 — 0.02 0.05 — 0.05 0.25 % Full
Function as a Percentage Scale
Full-Scale Voltage
Input Frequency Frequency Range for Specified 10 — 100k 10 — 100k 10 — 100k Hz
Range (Note 7 and 8) Nonlinearity
Frequency Input
Positive Excursion Voltage Required to Turn 0.4 — VDD 0.4 — VDD 0.4 — VDD V
Threshold Detector On
Negative Excursion Voltage Required to Turn – 0.4 – 2 – 0.4 — –2 – 0.4 — –2 V
Threshold Detector Off
Minimum Positive Time Between Threshold — 5 — — 5 — — 5 — µsec
Pulse Width (Note 8) Crossings
Minimum Negative Time Between Threshold — 0.5 — — 0.5 — — 0.5 µsec
Pulse Width (Note 8) Crossings
Input Impedance — 10 — — 10 — — 10 — MΩ
Analog Outputs
Output Voltage Voltage Range of Op Amp Output — VDD – 1 — — VDD – 1 — — VDD – 1 — V
(Note 9) for Specified Nonlinearity
Output Loading Resistive Loading at Output of 2 — — 2 — — 2 — — kΩ
Op Amp
Supply Current
IDD Quiescent Current Required From Positive
(Note 10) Supply During Operation — 1.5 6 — 1.5 6 — 3 10 mA
ISS Quiescent Current Required From Negative
(Note 10) Supply During Operation — – 1.5 – 6 – 1.5 – 6 –3 – 10 mA
VDD Supply Operating Range of Positive Supply 4 — 7.5 4 — 7.5 4 — 7.5 V
VSS Supply Operating Range of Negative Supply –4 — – 7.5 – 4 — – 7.5 –4 — – 7.5 V
Reference Voltage
VREF –VSS Range of Voltage Reference Input – 2.5 — — – 2.5 — — – 2.5 — — V
NOTES: 1. Full temperature range. Guaranteed, Not Tested. 6. 10Hz to 100kHz.; Guaranteed, Not Tested
2. IIN = 0. 7. 5µsec minimum positive pulse width and 0.5 µsec minimum
3. Full temperature range, IOUT = 10mA. negative pulse width.
4. IOUT = 10µA. 8. tR = tF = 20nsec.
5. Threshold Detect = 5V, Amp Out = 0V, Full Temperature Range 9. RL ≥ 2kΩ.; Tested @ 10kΩ
10. Full temperature range, VIN = – 0.1V.
© 2001 Microchip Technology Inc. DS21483A 3 TC9400/1/2-5 11/6/96
Voltage-To-Frequency/Frequency-To-Voltage Converters
TC9400
TC9401
TC9402
PIN CONFIGURATIONS
14-Pin Plastic DIP/CerDIP 14-Pin SOIC (Narrow)
IBIAS 1 IBIAS 14
14 VDD 1 VDD
NC = NO INTERNAL CONNECTION
PIN DESCRIPTIONS
Pin No. Symbol Description
1 IBIAS This pin sets bias current in the TC9400. Connect to VSS through a 100 kΩ resistor.
See text.
2 Zero Adj Low frequency adjustment input. See text.
3 IIN Input current connection for the V/F converter.
4 VSS Negative power supply voltage connection, typically – 5V.
5 VREFOUT Reference capacitor connection.
6 GND Analog ground.
7 VREF Voltage reference input, typically – 5V.
8 Pulse Freq Out Frequency output. This open drain output will pulse LOW each time the Freq
threshold detector limit is reached. The pulse rate is proportional to input voltage.
9 Output Common Source connection for the open drain output FETs. See text.
10 Freq/2 Out This open drain output is a square wave at one half the frequency of the pulse
output (pin 8). Output transitions of this pin occur on the rising edge of pin 8.
11 Threshold Detect Input to the threshold detector. This pin is the frequency input during F/V operation.
12 Amplifier Out Output of the integrator amplifier.
13 NC No internal connection
14 VDD Positive power supply connection, typically +5V.
TC9400
TC9401
TC9402
+5V
+5V
14
VDD RL
10kΩ
THRESHOLD fOUT 8
11 DETECT 3µsec
DELAY
+5V
THRESHOLD
DETECTOR
RL
10kΩ
fOUT/2 10
SELF- ÷2
START 9
–3V OUTPUT
COMMON
12 AMP OUT
VREF OUT
5
OFFSET 1 4 7 6
10kΩ
ADJUST RBIAS
100kΩ
REFERENCE
VOLTAGE
(TYPICALLY –5V)
–5V
VOLTAGE-TO-FREQUENCY (V/F)
CIRCUIT DESCRIPTION
The TC9400 V/F converter operates on the principal At the end of the charging period, CREF is shorted out.
of charge balancing. The operation of the TC9400 is easily This dissipates the charge stored on the reference capaci-
understood by referring to Figure 1. The input voltage (VIN) tor, so that when the output again crosses zero the system
is converted to a current (IIN) by the input resistor. This is ready to recycle. In this manner, the continued discharg-
current is then converted to a charge on the integrating ing of the integrating capacitor by the input is balanced out
capacitor and shows up as a linearly decreasing voltage at by fixed charges from the reference voltage. As the input
the output of the op amp. The lower limit of the output voltage is increased, the number of reference pulses re-
swing is set by the threshold detector, which causes the quired to maintain balance increases, which causes the
reference voltage to be applied to the reference capacitor output frequency to also increase. Since each charge in-
for a time period long enough to charge the capacitor to crement is fixed, the increase in frequency with voltage is
the reference voltage. This action reduces the charge on linear. In addition, the accuracy of the output pulse width
the integrating capacitor by a fixed amount (q = CREF × does not directly affect the linearity of the V/F. The pulse
VREF), causing the op amp output to step up a finite must simply be long enough for full charge transfer to take
amount. place.
TC9400
TC9401
TC9402
3 µsec
TYP
fOUT
fOUT/2 1/f
CREF
VREF
CINT
AMP 0V
OUT
NOTES: 1. To adjust fMIN, set VIN = 10mV and adjust the 50kΩ offset for 10Hz output.
2. To adjust fMAX, set VIN = 10V and adjust RIN or VREF for 10 kHz output.
3. To increase fOUT MAX to 100kHz, change CREF to 2pF and CINT to 75pF.
4. For high-performance applications, use high-stability components for RIN, CREF, VREF (metal film
resistors and glass capacitors). Also, separate output ground (pin 9) from input ground (pin 6).
TC9400
TC9401
TC9402
TC9400
TC9401
TC9402
500
VDD = +5V
VSS = – 5V
400 RIN = 1MΩ
VIN = +10V
CREF (pF) +12pF
TA = +25°C
300
1 kHz
200
100
100kHz
0 –1 –2 –3 –4 –5 –6 –7
VREF (V)
TC9400
TC9401
TC9402
+
V = 8V TO 15V (FIXED)
R2
14 10kΩ
V2
0.9 2
R1 5V
6 8 fOUT
GAIN 8.2 0.01
ADJUST kΩ µF
10kΩ
7 10 fOUT/2
2 VREF
kΩ 0.01 11
µF
OFFSET
ADJUST 0.2
R1 12 TC9400
5
RIN 820
pF 180
1MΩ pF 3
VIN IIN
0V–10V IIN 1 4 9
100 kΩ
V+ R1 R2 1
fOUT = IIN ×
10V 1 MΩ 10kΩ (V2–V7) (CREF)
12V 1.4 MΩ 14kΩ
15V 2 MΩ 20kΩ (VIN–V2) (V+–V2)
IIN = +
RIN (0.9 R1+0.2 R1)
+12 to +15V
1.2k*
14
VDD
1µF
11 THRESHOLD
R1 R4 DETECT
CINT 12 AMP OUT 10k 10k
910k 100k D2
5.1VZ CREF 5 CREF
R3
GAIN TC9400
3 IIN fOUT 8
2 ZERO
ADJUST
100k 6 GND 10 OUTPUT
fOUT/2
FREQUENCY
R2 R5
910k 91k D1
0.1µ OUTPUT 9
5.1VZ
COMMON
7 V
REF
INPUT Rp 1 I
OFFSET BIAS
VOLTAGE 100k VSS
(0 to 10V) 20k DIGITAL
4
GROUND
ANALOG GROUND
COMPONENT SELECTION
F/S FREQ. CREF CINT
1 kHz 2200pF 4700pF
10 kHz 180pF 470pF
100 kHz 27pF 75pF
TC9400
TC9401
TC9402
+8V to +5V
+5V
14 14
VDD VDD
10k
TC9400 TC9400
Frequency 0.01µF Frequency 33k 0.01µF
33k 11 11
Input Input DET
DET
+5V IN914
+5V IN914 1.0M 1.0M
0V 0V
–5V
TC9400
TC9401
TC9402
+5V
V+
14
VDD
*
fOUT/2 10
TC9400A
2
TC9401A
TC9402A
OUTPUT V+
COMMON 9 *
THRESHOLD
DETECT *
SEE 11 3 µsec fOUT 8
fIN FIGURE DELAY
6 * OPTIONAL
THRESHOLD IF BUFFER
DETECTOR IS NEEDED
VREF
OUT 5
CREF SEE
12pF 56 pF EQUATION,
IIN 3 PAGE 12
OFFSET
ADJUST
RINT CINT
+5V 60pF 1 MΩ + 1000pF
– AMP
OP OUT 12
100kΩ AMP VO
2 ZERO ADJUST +
2 kΩ
2.2kΩ IBIAS VSS VREF GND
1 4 7 6
10 kΩ
VREF
–5V
(TYPICALLY –5V)
Input Buffer
fOUT and fOUT/2 are not used in the F/V mode. However,
0.5µsec 5.0µsec
MIN MIN these outputs may be useful for some applications, such as
a buffer to feed additional circuitry. Then, fOUT will follow the
input frequency waveform, except that fOUT will go high
INPUT 3µsec after fIN goes high; fOUT/2 will be squarewave with a
frequency of one-half fOUT.
fOUT
If these outputs are not used, pins 8, 9 and 10 should be
connected to ground.
DELAY = 3µsec
fOUT/2
TC9400
TC9401
TC9402
V+ = 10V to 15V
14
10k VDD
6 GND
6.2V .01µF
10k TC9400
5
VREFOUT
500k
2 ZERO
100k ADJUST 47pF
V+ IIN 3
Offset
Adjust .001µF
1M
1.0k AMP OUT 12
33k 0.01µF
Frequency 11 DET VOUT
Input 6
GND
IN914 IBIAS
1.0M VREF VSS
7 4
0.1µF
1.0k
100k
Note: The output is referenced to pin 6, which is at 6.2V (Vz). For frequency meter applications,
a 1 mA meter with a series-scaling resistor can be placed across pins 6 and 12.
Output Filtering
The output of the TC9400 has a sawtooth ripple super-
VREFOUT 5
imposed on a DC level. The ripple will be rejected if the
47pF
TC9400 output is converted to a digital value by an integrat-
IIN 3
ing analog to digital converter, such as the TC7107 or
TC9400
TC7109. The ripple can also be reduced by increasing the 1M .001µF
value of the integrating capacitor, although this will reduce 200
AMP OUT 12
the response time of the F/V converter.
The sawtooth ripple on the output of an F/V can be
.01µF 1M 0.1µF
eliminated without affecting the F/V's response time by GND
using the circuit in Figure 10. The circuit is a capacitance 6 +5
VOUT
multiplier, where the output coupling capacitor is multiplied 2
–
7
6
by the AC gain of the op amp. A moderately fast op amp, 3 TL071
+
such as the TL071, should be used. 1M 4
–5
TC9400
TC9401
TC9402
F/V POWER-ON RESET In some cases, however, the TC9400 output must be
zero at power-on without a frequency input. In such cases,
In F/V mode, the TC9400 output voltage will occasion-
a capacitor connected from pin 11 to VDD will usually be
ally be at its maximum value when power is first applied. This
sufficient to pulse the TC9400 and provide a power-on reset
condition remains until the first pulse is applied to fIN. In most
(see Figure 11A). Where predictable power-on operation is
frequency-measurement applications this is not a problem,
critical, a more complicated circuit, such as Figure 11B, may
because proper operation begins as soon as the frequency
be required.
input is applied.
VDD
14
1000pF
1kΩ THRESHOLD
11
fIN DETECTOR
(A)
TC9400
VDD
(B)
16 5 2 1
VCC B R C
3
CLRA
100kΩ CD4538
6
Q
4 To TC 9400
A
1µF VSS
fIN
8
TC9400
TC9401
TC9402
PACKAGE DIMENSIONS
14-Pin CerDIP
PIN 1
.300 (7.62)
.230 (5.84)
.040 (1.02)
.200 (5.08) .020 (0.51)
.160 (4.06)
.015 (0.38) 3° MIN.
.200 (5.08) .150 (3.81) .008 (0.20)
.125 (3.18) MIN.
.400 (10.16)
.320 (8.13)
.020 (0.51)
.110 (2.79) .065 (1.65) .016 (0.41)
.090 (2.29) .045 (1.14)
14-Pin Plastic DIP
PIN 1
.260 (6.60)
.240 (6.10)
.310 (7.87)
.770 (19.56) .290 (7.37)
.745 (18.92)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51) .015 (0.38)
3° MIN.
.150 (3.81) .008 (0.20)
.115 (2.92)
.400 (10.16)
.310 (7.87)
.110 (2.79) .070 (1.78) .022 (0.56) Dimensions: inches (mm)
.090 (2.29) .045 (1.14) .015 (0.38) 14
TC9400
TC9401
TC9402
.344 (8.74)
.337 (8.56)
.069 (1.75)
.053 (1.35) .010 (0.25)
8° MAX.
.007 (0.18)
Dimensions: inches (mm)
.010 (0.25) .050 (1.27)
.018 (0.46)
.004 (0.10) .016 (0.40)
.014 (0.36)
TC9400
TC9401
TC9402
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01/09/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 1/01 Printed on recycled paper.
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16