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TD3 Memory

The document discusses various aspects of computer memory, including calculations for screen page size, RAM bandwidth, and memory chip requirements. It also covers PROM space management, cache memory organization, and address mapping for different cache types. Additionally, it addresses set-associative cache configurations and memory address formats.

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15 views2 pages

TD3 Memory

The document discusses various aspects of computer memory, including calculations for screen page size, RAM bandwidth, and memory chip requirements. It also covers PROM space management, cache memory organization, and address mapping for different cache types. Additionally, it addresses set-associative cache configurations and memory address formats.

Uploaded by

dghanem188
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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TD3 Memory (RAM, ROM, cache)

I. A computer has a screen with a resolution of 1280 x 1024 pixels capable of


displaying 65,536 colors. What memory size (in megabytes) occupies a screen page?

II. A memory RAM is connected to a processor, the cycle time for the first access is
20 ns and 10 ns for the following three access which are accelerated. Each access
retrieves 8 bytes.
What is the bandwidth of the transfer of information between memory and the processor?
Hint: The bandwidth is measured by the number of bytes transferred between the CPU
and RAM per second.

III. Memory RAM:


a. How many 128x8 RAM chips are needed to provide a memory capacity of 2048
bytes?
b. How many lines of the address bus must be used to access 2048 bytes of
memory?

IV. A 16K PROM contains three contiguous programs of sizes 1FD4, 826 and FFE
(all three numbers are hexadecimal).
a) Calculate the total available space in the PROM
b) A new program, which is to be added to the PROM, is 910 (hexadecimal) bytes
in size.
By how many bytes must this new program be reduced in order to make it fit the
available space?

V. Consider a machine with a byte addressable main memory of 216 bytes and block
size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with
this machine.
a. How is a 16-bit memory address divided into tag, line number, and byte
number?
b. Into what line would bytes with each of the following addresses be stored?
0001 0001 0001 1011
1100 0011 0011 0100
1101 0000 0001 1101
1010 1010 1010 1010
c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache.
What are the addresses of the other bytes stored along with it?
d. How many total bytes of memory can be stored in the cache?
e. Why the tag is also stored in the cache?
VI. For the hexadecimal main memory addresses 111111, 666666,BBBBBB, show
the following information, in hexadecimal format:
a. Tag, Line, and Word values for a direct-mapped cache, using the format :

b. Tag and Word values for an associative cache, using the format:

c. Tag, Set, and Word values for a two-way set-associative cache, using the
format:

VII. A set-associative cache consists of 64 lines, or slots, divided into four-line sets.
Main memory contains 4K blocks of 128 words each. Show the format of main memory
addresses.

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