EHB 322E

Digital Electronic Circuits

Asst. Prof. Sheida Faraji

Lecture 10 – Sequential Logic

Week 10 (5th May 2025)

Spring 2025
Lecture Outline

• Review on sequential logics

• Dynamic latches and registers

2
Sequential Logic
• Sequential logics using a clock signal for synchronization are dependent upon the frequency and
therefore the clock pulse width to activate their switching action.
• Registers are positive edge-triggered (input data
copied on positive edge of clock) or negative edge-
triggered (input is copied on clock negative edge).
• Individual Sequential Logic circuits is used to build
more complex circuits, e.g. Multivibrators, Shift
Registers, Latches and Memories.

• Active High: state changes from low to high on the clock’s

rising edge.
• Active Low: state changes from high to low on the clock’s
falling edge.
• Clock width: time during which the value of clock signal is
equal to a logic ‘1’ or high.
Clock signal waveform • Duty cycle: ratio of the clock width to the clock period.
Timing Metrics for Sequential Circuit/Register
• The set-up time (tsu) is the time that the data inputs (D input) must be valid before the clock
transition (i.e. 0 to 1 transition for a positive edge-triggered register).
• The hold time (thold) is the time the data input must remain valid after the clock edge.
• If set-up and hold-times are met, the data at the D input is copied to the Q output after a worst-case
propagation delay (with reference to the clock edge) denoted by tc-q.

4
Flip-Flops
• The latch together with the triggering circuitry forms a flip-flop.
• Flip-flop has 2 bistable operating states and stores 1 bit of data.

Different types of flip-flop exist:

• SR flip-flop
• JK flip-flop
• D-type
• Toggle type

5
SR Flip-Flop/latch
• NOR Gate SR Flip-flop:

Reset →Q=0
Set →Q=1 memory
SR Flip-Flop/latch
NAND Gate SR Flip-flop: ത
Reset →𝑄=0
Set → 𝑄ത =1
Memory (previous state)

Metastable
Clocked/gated SR Flip-Flop
SR latch NAND gate
S*

R*

CLK is 0 then S*=1 and R*=1

CLK is 1 then S*=𝑺ഥ and R∗= 𝑹

ഥ
Clocked/gated SR Flip-Flop
Edge-triggered Excitation table
Min inputs to excite or trigger
S* FF to go from present state to
the next state

R*

Truth table Characteristic table of SR flip-flop (CLK=1)

Clocked/gated SR Flip-Flop

A simpler version of clocked SR flip-flop using pass-transistor

logic. This circuit is used as a memory cell in SRAM.

The SR flip-flop can be directly implemented in CMOS by

replacing each NOR gates with its CMOS circuit.
JK Flip-Flop
• Despite its advantages, basic SR NAND flip-flop circuit suffers from two basic switching problems:
• 1. the Set = 1 and Reset = 1 condition (S = R = 1) must always be avoided.
• 2. if Set or Reset change state while the enable CLK is high the correct latching action may not occur.

• The JK flip flop is basically a gated SR flip-flop with the

addition of a clock input circuitry that prevents the
illegal or invalid output condition that can occur when
both inputs S and R are equal to logic level “1”.
JK Flip-Flop
ത
If CLK=1, J=1, K=1 and (old state) Q=1 and 𝑄=0 ത
(New state) Q=0 and 𝑄=1 Toggled or
𝒎𝒆𝒎𝒐𝒓𝒚

0
1 1
1

1 0 0
1

• The JK flip flop is basically a gated SR flip-flop with the

addition of a clock input circuitry that prevents the
illegal or invalid output condition that can occur when
both inputs S and R are equal to logic level “1”.
JK Flip-Flop

Truth table

Next state
Characteristic table of JK flip-flop

Excitation table Excitation table

of JK flip-flop of SR flip-flop
Master-Slave JK Flip-flop
• One flip-flop acts as the “Master” circuit, which triggers on the rising edge of the clock pulse while
the other acts as the “Slave” circuit, which triggers on the falling edge of the clock pulse.
• Hence, the master and slave are enabled during opposite half-cycles of the clock signal.

• J and K are connected to the gated “master” SR flip flop which “locks” the input condition while CLK
is “HIGH” at logic level “1”. As the clock input of the “slave” flip flop is the inverse (complement) of
the “master” clock input, the “slave” SR flip flop does not toggle.
• The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.
D Flip-Flop
• Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop.
• The D-type Flip-flop overcomes one of the main disadvantages of the basic SR NAND Gate
Bistable when condition of SET = “1” and RESET = “1” is forbidden.
• By adding an inverter (NOT gate) between the Set and Reset inputs, the S and R inputs become
complements of each other ensuring that the two inputs S and R are never equal (0 or 1) at the
same time allowing to control the toggle action of the flip-flop using one single D input.

D flip-flop is a variation of a clocked SR flip-flop

constructed using either NAND or NOR gates.
D Flip-Flop

SR flip-flop Truth table

Qn+1= D

D flip-flop Truth table Characteristic table

Excitation table
The Master-Slave D Flip-Flop Circuit

• On the rising edge of the clock signal (LOW-to-HIGH): the “master” is ON latches the input condition
at D, while the output stage is deactivated.
• On the falling edge of the clock signal (HIGH-to-LOW): “slave” stage is ON, latching on to the output
from the first master circuit. Then the output stage appears to be triggered on the negative edge of the
clock pulse.
D Flip Flop Circuit-Divide-by-2 Counter

• One main use of a D-type flip flop is as a Frequency

Divider.

• If the Q output on a D-type flip-flop is connected

directly to the D input giving the device closed loop
“feedback”, successive clock pulses will make the
bistable “toggle” once every two clock cycles (the
output has half the frequency of the clock pulses).

• By placing a feedback loop around the D-type flip

flop another type of flip-flop circuit can be
constructed called a T-type flip-flop or more
commonly a T-type bistable, that can be used as a
divide-by-two circuit in binary counters.
Toggle Flip-Flop
• T flip-flop is a variation of the clocked JK flip-flop.
• T-type flip-flop means its outputs Q and Q invert
from their previous state as it toggles back and
forth every time it is triggered (T = 1).

edge-triggered

Truth table

Excitation
table
Next state
Characteristic table
Multivibrator
• Multivibrators (MV) are sequential logic circuits that oscillates between two distinct states
of HIGH and LOW producing a continuous output.
• Multivibrator are hence single pulse generator circuits.
• Clock pulse generation circuits can be a combination of analogue and digital circuits that
produce a continuous series of pulses (these are called Astable multivibrators) or a pulse of
a specific duration (these are called Monostable multivibrators).
• Combining two or more multivibrator circuit provides generation of a desired pattern of
pulses (including pulse width, time between pulses and frequency of pulses).
• There are basically three types of clock pulse generation circuits/multivibrator:
• Astable: has NO stable states but switches continuously between two states producing a
train of square wave pulses.
• Monostable: a one-shot MV that has only ONE stable state which once externally triggered
returns to its first stable state.
• Bistable: a flip-flop with TWO stable states producing a single pulse either HIGH or LOW.
Monostable Multivibrator

Time constant
Dynamic Latches and Registers

• A stored value in a static sequential circuit remains valid as long as the supply
voltage is applied to the circuit, hence the name static.
• The major disadvantage of the static gate is its complexity.
• Static is preferred when updates are infrequent (clock gating).
• Dynamic (latches and registers) stores state temporarily on parasitic capacitors
only for a limited amount of time, typically in the range of milliseconds.
• In this idea, the absence of charge denotes a 0, while its presence stands for a
stored 1.
• If one wants to preserve signal integrity, a periodic refresh of its value is necessary.
Hence the name dynamic storage.

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Non-ideal clock signals
• In real scenario we cannot assume that 𝐶𝐿𝐾 is a perfect inversion of CLK that delay of the generating
inverter is zero.
• Variations can exist in the wires used to route the two clock signals, or the load capacitances can vary
based on data stored in the connecting latches.
• This effect, known as clock skew is a major problem, and causes the two clock signals to overlap.
Clock-overlap can cause failure for the NMOS-only negative master-slave register.
Non-ideal clock signals
• At clock ‘high’, the slave stage should stop sampling the master stage output and go into a hold mode.
• However, since CLK and 𝐶𝐿𝐾 are both high for a short period of time (the overlap period), both
sampling pass transistors conduct and there is a direct path from the D input to the Q output.
• As a result, data at the output can change on the rising edge of the clock, which is undesired for a
negative edge triggered register.
• The is called ‘RACE’ condition, as in dynamic logics case, where the value of the output Q is a function
of whether the input D arrives at node X before or after the falling edge of CLK.
• If there is clock overlap between CLK and 𝐶𝐿𝐾, node A can be driven by both D and B, resulting in an
undefined state.

Overlapping clock pairs

Pseudo-static Two-phase register
To solve non-idea/overlapping clocks and RACE condition:

• Using two non-overlapping clocks PHI1 and PHI2 instead and keeping the nonoverlap time tnon_overlap
between the clocks large enough so no overlap occurs even in the presence of clock-routing delays.
• During the nonoverlap time, register is in the high-impedance state (hold)—the feedback loop is
open, the loop gain is zero, and the input is disconnected.
• Leakage will destroy the state if this condition holds for too long a time.
• Hence the name pseudo-static register: the register employs a combination of static and dynamic
storage approaches depending upon the state of the clock.

Pseudo-static two-phase D register Two-phase non-overlapping clocks

Dynamic Transmission-Gate Edge-triggered Register
• A fully dynamic positive edge-triggered register based on the master-slave concept (8 transistors).
• CLK = 0: the input data is sampled on storage node 1, with equivalent capacitance of C1 consisting of
gate capacitance of I1, the junction capacitance of T1, and the overlap gate capacitance of T1.
• In this period, slave stage is in hold (memory) mode, with node 2 in a high-impedance (floating) state.

• On the rising edge of clock, T2 turns TG

on, and the value sampled on node
1 right before the rising edge
propagates to the output Q.

• Clock overlap is an important concern

for this register. During the 0-0
overlap period, the NMOS of T1 and
the PMOS of T2 are simultaneously
‘ON’, creating a direct path for data to
flow from the D input of the register
to the Q output (Race condition).
Dynamic Transmission-Gate Edge-triggered Register
• The same is true for the 1-1 overlap region,
where an input-output path exists through the
PMOS of T1 and the NMOS of T2.
• The output Q can change on the falling edge if
the overlap period is large which is undesirable
a positive edge-triggered register.

• A simple solution to overlapping clocks and race issue is to make

the circuit pseudo-static by adding this logic to all dynamic latches.
C2MOS - A Clock-Skew Insensitive Approach

• The circuit is an ingenious positive

edge-triggered register, based on a
master-slave concept insensitive to
clock overlap.

• This circuit is called the C2MOS

(Clocked CMOS) register.
C2MOS - A Clock-Skew Insensitive Approach

1. CLK = 0 (𝐶𝐿𝐾 = 1): The first tri-state driver is

‘ON’, the master stage acts as an inverter
sampling the inverted version of D on the
internal node X. The master stage is in the
evaluation mode. The slave section is in a
high-impedance mode, or in a hold mode.

2. The roles are reversed when CLK = 1: The

master stage section is in hold mode (M3-
M4 OFF), while the second section evaluates
(M7-M8 ‘ON’). The value stored on CL1
propagates to the output node through the
slave stage which acts as an inverter.

positive edge-triggered master-slave register

C2MOS - A Clock-Skew Insensitive Approach
• A C2MOS register with CLK-𝐶𝐿𝐾 clocking is insensitive to overlap, as long as the rise and fall times of
the clock edges are sufficiently small.
• Races are just not possible in a C2MOS register since the overlaps activate either the pull-up or the
pull-down networks but never both simultaneously.
• The inverters force 0-1 and 1-0 propagation modes only.

Positive-edge Negative-edge
triggered triggered
Dual-edge Registers
• It is possible to design sequential circuits that sample the input on
both edges. The advantage is that a lower frequency clock (half of
the original rate) is distributed for the same functional throughput,
resulting in power savings in the clock distribution network.
• The circuit is a modification of the C2MOS register consisting of
two parallel master slave-based edge-triggered registers, whose
outputs are multiplexed using the tri-state drivers.
• CLK=high: positive latch of transistors M1 to M4 samples the
inverted D input on node X. Node Y is held stable, since devices M9
and M10 are turned off.
• Falling edge of clock: the top slave latch M5 -M8 turns ON and
drives the inverted value of X to the Q output.
• CLK=low: the bottom master latch (M1 , M4 , M9 , M10) is turned
ON, sampling the inverted D input on node Y. On the rising edge,
the bottom slave latch conducts, and drives the inverted version of
Y on node Q. Data hence changes on both edges.
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True Single-Phase Clocked Register (TSPCR)
• While the C2MOS provides a skew-tolerant solution, it is possible to design registers that only use a
single-phase clock.
• The True Single-Phase Clocked Register (TSPCR), uses a single clock.

• For the positive latch, when CLK is high, the latch is in the transparent mode.
• when CLK = 0, both inverters are disabled, and the latch is in hold-mode. Only the pull-up
networks are still active, while the pull-down circuits are deactivated.
Dynamic Latches
• A register can be constructed by cascading positive and negative latches.
• The main advantage is the use of a single clock phase.
• The disadvantage is the slight increase in the number of transistors.
• TSPC offers an additional advantage: the possibility of embedding logic functionality into the latches.
• For example, a positive latch implementing AND of In1 and In2 is added to the latching function.
Pulsed Latches
• For, we have used the master-slave configuration to create an edge-triggered register.
• A different approach is to use a short pulse (glitch) around the rising (or falling) edge of the clock
which acts as the clock input to a latch, sampling the input only in a short window.

• Race condition is avoided

by keeping the opening
time (transparent period)
of the latch very short.

• The combination of the

glitch generation circuitry
and the latch is a positive
edge-triggered register.
Pulsed Latches
• CLK = 0: node X is charged up to VDD (MN is off since CLKG is low). On the rising edge of the clock,
there is a short period of time when both inputs of the AND gate are high, causing CLKG to go high.
• This activates MN , pulling X and eventually CLKG low.
Pipelining: Optimizing sequential circuits
• Pipelining is used to accelerate the operation of the datapaths in digital processors.
• The goal of this circuit is to compute log(|a - b|), where both a and b represent streams of numbers.

Reference circuit

• The minimal clock period Tmin necessary to ensure correct evaluation is given as:

• tc-q and tsu are the propagation delay and the set-up time of the register.
• tpd,logic stands for the worst-case delay path through the combinational network, which consists of the
adder, absolute value, and logarithm functions.
Pipelining: Optimizing sequential circuits
• Assume that each logic module has an equal propagation delay.

• Each logic module is then active for only 1/3 of the clock period, it won’t do any useful computation
during the other 2/3 of the period.

• Pipelining is a technique to improve the resource utilization and increase the functional throughput.
Assume that we introduce registers between the logic blocks, as shown below.

Pipelined circuit
Pipelining: Optimizing sequential circuits
• This causes the computation for one set of input data to spread over a number of clock periods.

• The computation is performed in an assembly-line fashion, hence the name pipeline.

• The advantage of pipelined operation becomes apparent when examining the minimum clock period
of the modified circuit. The combinational circuit block has been partitioned into three sections,
each of which has a smaller propagation delay than the original function. This effectively reduces the
value of the minimum allowable clock period:
Non-Bistable Sequential Circuits

• The most important property of a latch circuit is that it

has two stable states and is hence called bistable.

• Other regenerative circuits can be catalogued as astable

and monostable.

• Another interesting regenerative circuit is the Schmitt

trigger: its switching threshold is variable and depends
upon the direction of the transition (low-to-high or
high-to-low). This peculiar feature can come in handy in
noisy environments.
The Schmitt Trigger
A Schmitt trigger is a device with two important properties:

• It responds to a slowly changing input waveform with a fast transition time at the output.
• The VTC of the device displays different switching thresholds for positive- and negative-going input
signals. The switching thresholds for the low-to-high and high-to-low transitions are called VM+ and
VM-, respectively. The hysteresis voltage is defined as the difference between the two.
The Schmitt Trigger
• One of the main uses of the Schmitt trigger is to turn a noisy or slowly varying input signal into a
clean digital output signal.

The “secret” behind the Schmitt trigger concept is the use of positive feedback.
CMOS Implementation of the Schmitt Trigger
• One possible CMOS implementation of the Schmitt trigger is shown below:

The switching threshold of a CMOS

inverter is determined by the (kn/kp) ratio
between the NMOS and PMOS transistors.

Increasing the ratio results in a reduction

of the threshold, while decreasing it
results in an increase in VM.
CMOS Implementation of the Schmitt Trigger
• Vin is initially equal to 0, so that Vout = 0 as well.

• The feedback loop biases the PMOS transistor M4 in the

conductive mode while M3 is off. The input signal connects
to an inverter consisting of two PMOS transistors in parallel
(M2 and M4) as a pull-up network, and a single NMOS
transistor (M1) in the pull-down chain.

• This modifies the effective transistor ratio of the inverter to

kM1/(kM2+kM4), which moves switching threshold upwards.

• Once the inverter switches, the feedback loop turns off M4, and the NMOS device M3 is activated. This
extra pull-down device speeds up the transition and produces a clean output signal with steep slopes.

• A similar behavior can be observed for the high-to-low transition. In this case, the pull-down network
originally consists of M1 and M3 in parallel, while the pull-up network is formed by M2. This reduces the
value of the switching threshold to VM–.
Monostable Sequential Circuits
• A monostable circuit generates a pulse of a predetermined width every time the quiescent circuit is
triggered by a pulse or transition event. It is called monostable because it has only one stable state
(the quiescent one).
• An example is the address transition detection (ATD) circuit, used for the timing generation in static
memories. This circuit detects a change in a signal or group of signals and produces a pulse to
initialize the subsequent circuitry.
• The most common approach to the implementation of one-shots is the use of a simple delay element
to control the duration of the pulse. In the quiescent state, both inputs to the XOR are identical, and
the output is low. A transition on the input causes the XOR inputs to differ temporarily and the
output to go high. After a delay td (of the delay element), this disruption is removed, and the output
goes low again. A pulse of length td is created.
 Astable Circuits
• An astable circuit has no stable states.
• The output oscillates back and forth between two quasi-stable states with a period determined by the
circuit topology and parameters (delay, power supply, etc.).
• The ring oscillator is a simple, example of an astable circuit. It consists of an odd number of inverters
connected in a circular chain.
• Due to the odd number of inversions, no stable operation point exists, and the circuit oscillates with a
period (T)=2 × tp × N, with N the number of inverters and tp the propagation delay of each inverter.
Astable Circuits (voltage-controlled oscillator)
• The ring produces a waveform with a fixed oscillating frequency determined by the delay of an inverter
in the CMOS process. In many applications, it is necessary to control the frequency of the oscillator.
• An example of such a circuit is the voltage-controlled oscillator (VCO), whose oscillation frequency is a
function (typically non-linear) of a control voltage.

• The standard ring oscillator can be modified into a

VCO by replacing the standard inverter with a
current-starved inverter.
• The mechanism for controlling the delay of each
inverter is to limit the current available to
discharge the load capacitance of the gate.
• M3 is controlled by an analog control voltage Vcntl.
Lowering Vcntl reduces the discharge current and,
hence, increases tpHL. The ability to alter the
propagation delay per stage allows to control the Voltage-controlled oscillator based
frequency of the ring structure. on current-starved inverters
Example 1.
Consider the following edge-triggered register. Assume that the clock inputs CLK and 𝐶𝐿𝐾 have a 0V to
VDD swing. Also assume (for parts a-c) that there is no skew between CLK and 𝐶𝐿𝐾 (i.e., the inverter
delay to derive CLK from CLK is zero). Assume that the rise/fall times on all signals are zero.

a) What type of register is

this? (Positive Edge-Triggered
Register or Negative Edge-
Triggered Register). Explain.

Negative Edge-Triggered.
Master is transparent and slave
is holding when CLK=1.
Slave is transparent and master
is holding when CLK=0.
Example 1.
b) Assume that the propagation delay of each clocked inverter (e.g., M1 -M4) is TCK_INV and the delay of
inverters I1 and I2 is TINV. Derive the expression for the set-up time (tsu), the propagation delay (tc-q)
and the hold time (th) in terms of the above parameters. Explain your results.

Setup: Data must go through

1st clocked inverter and I1 so
tsu = Tck_inv + Tinv.

Propagation delay: Q becomes

valid when the data passes
through the second clocked
inverter so tc-q = Tck_inv.

Hold time: When CLK goes 1

to 0, the first clocked inverter
is already off, so tH = 0.
Example 1.
c) What is the function of transistors M5 -M8 and M13 -M16? Is this circuit Ratioed?
These FETs implement two clocked inverters. Each clocked inverter is on when its respective stage is
holding, so they complete a back-to-back inverter pair that makes the circuit static.

The circuit is not ratioed

because the inverters turn off
during the sample operation,
so there is never a fight.
Example 2.
Consider the circuit below. Assume the inverter switches ideally at VDD/2, neglect body effect, channel
length modulation and all parasitic capacitance throughout this problem.
a) What is the logic function of performed by
this circuit? A NAND gate
b) Does this circuit have static dissipation? Why?

When A=B= VDD, the voltage at node x is

VX=VDD-VtN. This causes static power
dissipation at the inverter the pass transistor
network is driving.

c) Using only just 1 transistor, design The size of Mr should be chosen so

a fix so that there will not be any that if one of the inputs A or B equals
static power dissipation. Explain how 0, either Mn1 or Mn2, would be able
you chose the size of the transistor. to pull node X to VDD/2 or less (turn
inverter on).
Example 2.
d) Implement the same circuit using transmission gates.

e) Replace the pass-transistor network in the original

circuit with a pass transistor network that computes
the following function: x = ABC at the node x.
Assume you have the true and complementary
versions of the three inputs A,B and C
Example 3.
Transmission Gate XOR

two-to-one multiplexer
Example 4.
Sketch a complementary (differential) pass transistors (CPL), implementing 𝑌 =
𝐴𝐵ത + 𝐴𝐵ҧ and 𝑌ത = 𝐴𝐵 + 𝐴ҧ𝐵.
ത Use the left-hand CPL as your guide.
Example 5.
Consider an OAI432 gate whose logic function is:

Assume that only A,E and H inputs are HIGH, the rest of inputs are
LOW. Other parameters are:
a) Draw a full CMOS circuit diagram.
Example 5.
Consider an OAI432 gate whose logic function is:
Assume that only A,E and H inputs are HIGH, the rest of inputs are LOW.
b) Draw a domino CMOS implementation whose output is 𝑍.ҧ
c) Draw an equivalent circuit using equivalent transistor sizes
with W/L=30/2 for both NMOS and PMOS.
Example 5.
d) Assuming total parasitic capacitances at the precharging node and the output nodes are 20pF and
VDD=5 V, calculate the delay from the end of precharging (rectangle pulse CLK), to the point at which
output reaches 2.5 V.
i. Delay calculation for node X to fall from 5 V to 2.5 V, where VOH=VDD
and VOL=0

ii. Delay calculation for node X to rise from 0 to 2.5 V:

For midterm2, practice exercises and problems in
Sedra’s chapters 13 and 14 (14.1, 14.2 and 14.3)
and 15 (15.1) and Kang’s chapters 7,8 and 9.
Next week (20th May) we will study
memory devices.