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Recent Advances in GaN-Based Power HEMT Devices

Jiaqi He, Wei-Chih Cheng, Qing Wang, Kai Cheng, Hongyu Yu,* and Yang Chai*

1. Introduction
The ever-increasing power density and operation frequency in electrical
Electricity consumption is expected to
power conversion systems require the development of power devices that can
occupy about 60% of the used energy
outperform conventional Si-based devices. Gallium nitride (GaN) has been in the next 20 years.[1] Silicon (Si)-based
regarded as the candidate for next-generation power devices to improve the power electronic devices, such as insu-
conversion efficiency in high-power electric systems. GaN-based high elec- lated gate bipolar transistors (IGBTs) and
tron mobility transistors (HEMTs) with normally-off operation is an important superjunction metal oxide semiconductor
device structure for different application scenarios. In this review, an overview field effect transistors (MOSFETs), have
played dominating roles in controlling
of a series of effective approaches to improve the performance of GaN-based
the electric power.[2,3] With the continuous
power HEMT devices is given. Modified epistructures are presented to sup- demand of high-power density capability,
press defects and current leakage, and low-damage recess-free processes are high frequency converters with improved
discussed in fabricating normally-off HEMTs. Possible effects of dielectrics efficiency, as well as the need of small size
on a metal–insulator–semiconductor (MIS) structure are also intensively and low cost for the future power elec-
tronics applications, conventional Si-based
introduced. Metal/semiconductor contact engineering is investigated, and
devices are running into their physical
fabrication of Au-free ohmic contact and graphene insertion layer to enhance limits.
the device performance is emphasized. Finally, the effects of field plates are Gallium nitride (GaN) and related wide
studied through the use of simulated and fabricated devices. bandgap semiconducting alloys have been
regarded as the candidate materials for
the next-generation of high-power and
high-frequency electronic devices.[4–6] Compared with Si coun-
terparts, the higher breakdown field and drift velocity of GaN-
J. He based devices can produce lower losses at high voltage and
Department of Electronic and Information Engineering temperature.[7,8] The superior performances are not only origi-
The Hong Kong Polytechnic University nated from these inherent material properties of GaN itself, but
Hong Kong 999077, China also related to the device technology based on AlGaN/GaN het-
J. He, W.-C. Cheng erostructures. Owing to the high mobility of 2D electron gas
School of Microelectronics
Southern University of Science and Technology
(2DEG) formed at the AlGaN/GaN interface, a lateral device
Shenzhen, Guangdong 518055, China called heterojunction field-effect transistor (HFET), also known
W.-C. Cheng as high electron mobility transistor (HEMT), offers tremen-
Department of Electronic and Computer Engineering dous potential to the power switching and radio frequency (RF)
The Hong Kong University of Science and Technology applications.[9–11] To date, GaN-based materials are generally
Hong Kong 999077, China heteroepitaxial grown on the foreign substrates of Si, sapphire,
Dr. Q. Wang, Prof. H. Yu and silicon carbide (SiC) by metal-organic chemical vapor depo-
School of Microelectronics
Engineering Research Center of Integrated Circuits for Next-Generation sition (MOCVD).[12–16] For power electronic applications, GaN
Communications HEMTs fabricated on Si substrate are the most usual structures
Ministry of Education, Southern University of Science and Technology owing to their cost-effective large-size wafer and conductive
Shenzhen, Guangdong 518055, China properties.[17–20] In addition, the GaN-on-Si devices can tape-out
E-mail: yuhy@sustech.edu.cn
compatibly with the matured Si CMOS process flows to reduce
Dr. K. Cheng
Enkris Semiconductor
the processing cost further for mass production.
Suzhou, Jiangsu 215028, China There are multiple parameters to evaluate the device quality
Prof. Y. Chai of GaN-based HEMTs, such as breakdown voltage (VBD),
Department of Applied Physics threshold voltage (Vth), and on-state resistance (Ron).[21–24] In
The Hong Kong Polytechnic University this paper, we will review a series of effective technical means
Hong Kong 999077, China that can improve the critical device characteristics of GaN power
E-mail: ychai@polyu.edu.hk
HEMTs, and focus on the recently innovative device structures
The ORCID identification number(s) for the author(s) of this article
can be found under https://doi.org/10.1002/aelm.202001045.
and technologies. In Section 2, we provide a brief introduction
on the conventional normally-on GaN HEMT structure, and
DOI: 10.1002/aelm.202001045 illustrate several effective approaches to achieve normally-off

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GaN HEMTs. In Section 3, we present the modified buffer (recessed-gate).[5] All the schematic structures of normally-off
layers to improve the electrical properties of GaN channel. In GaN HEMT are shown in Figure 1b–g without electrode pads.
Section 4, several low-damage processes to fabricate normally- As demonstrated in Figure 1b, a Mg-doped p-type GaN or
off HEMTs are introduced in details. In Section 5, the impact of AlGaN is deposited on the gate region. The higher Fermi level
different insulating layers for passivation and gate dielectric for of p-GaN lifts the conduction band up, thus resulting in the
metal-insulator-semiconductor HEMTs (MIS-HEMTs) are dis- depletion of 2DEG channel beneath the Schottky gate. The
cussed. We also show innovative drain/source/gate metal fab- device switches on with a positive gate voltage (Vg > Vth > 0)
ricating methods to strengthen the breakdown, electric leakage, that forms a “real” normally-off GaN HEMT.[30–35] While the
and contact properties in Section 6. The simulation and fabrica- p-AlGaN gate is applied, a gate injection transistor (GIT) is fab-
tion of field plates are studied in Section 7. ricated to reduce the Ron as the gate current increases.[36–38] In
fact, the high acceptor concentrations of p-GaN and p-AlGaN
are necessary to keep a diode-like gate characteristic, which can
2. GaN-Based HEMT Power Device be also achieved by introducing a NiOx-based interlayer below
the gate.[39–41]
Structures—Normally-On and Normally-Off
When the thickness of AlGaN barrier beneath the gate
Naturally, a normally-on switching is achieved owing to the electrode is reduced to a low value, the 2DEG at the interface
2DEG generated at AlGaN/GaN interface, making the threshold region will be depleted owing to the lower Fermi level than the
voltage of HEMT device negative (Vth < 0). However, the high- conduction band.[42,43] Furthermore, the polarization-induced
power electronic systems prefer the normally-off (Vth > 0) charges will be eliminated when the AlGaN barrier under the
operation because of the suppression of static power consump- gate region is fully removed. The barrier removing process can
tion and safety concerns, in which the gate region is required introduce extra etching damage and surface states. Therefore,
to be modified by band engineering or neutralization of bound gate dielectric is significant for the recessed-gate structure
charges. that can decrease off-state gate leakage and driver losses.[44–46]
Figure 1c,d shows two recessed-gate normally-off HEMT sche-
matics. One is the partially recessed-gate MIS-HEMT structure
2.1. Normally-On GaN HEMT Structure with a residual thin AlGaN barrier under the gate dielectric.[47,48]
Another is the fully recessed-gate MIS-FET structure, also
Figure 1a shows an isolated normally-on GaN HEMT struc- called a hybrid MOS-HFET, since the 2DEG will penetrate the
ture, which is also called depletion mode (D-mode) structure. dielectric to connect either side of the recess when the device
From bottom to top, a 1–5 µm buffer layer is deposited on Si turns on.[49,50] As a result, the Vth and Ron of the MIS-FET are
substrates to compensate the lattice mismatch stress. Then, both higher than the MIS-HEMT structure.[51,52]
an unintentional doped (UID) GaN layer, a 0.7–1.2 nm AlN Figure 1e shows a special normally-off HEMT model com-
spacer layer and a 15–30 nm AlxGa1-xN barrier are successively bining low-voltage normally-off Si MOSFET with high-voltage
deposited to form a heterojunction. The thickness and Al molar normally-on GaN HEMT in a cascode configuration.[53,54]
fraction x of the AlxGa1-xN (generally from 0.15 to 0.4) are mod- When the system is given a positive gate-drain voltage above
ulated to maintain an appreciate quantity of electric charges the Vth of Si MOSFET, the gate-source voltage of GaN HEMT
under the critical thickness of relaxation. Owing to the polari- is 0 V, leading to the open of normally-on GaN HEMT. On
zation effect and bandgap offset of AlGaN/GaN, the energy the other hand, switching the Si MOSFET off will result in a
bands of heterojunction are bended downward to form a sharp large negative gate-source voltage of GaN HEMT, correspond-
quantum well, where the high-intensity electrons are trapped at ingly pinching off the 2DEG channel. Obviously, the cascode
AlGaN/GaN interface.[25,26] The 2DEG channel is generated on configuration provides a positive Vth to control the switch of
the top of UID-GaN layer that forms high-density current from normally-on GaN HEMT, but it is still seriously limited by
the Ohmic-contact source to drain.[5] As a result, a Schottky gate the package parasitic and high temperature stability of Si
is required to pinch off the normally-on 2DEG channel. When MOSFET.[55,56]
the device gate is given enough negative voltages, the Schottky Except these most popular technologies, fluorine gate and
barrier height is enlarged to lift the conduction band under the thin/ultrathin-barrier GaN HEMT structure can also achieve
gate region of AlGaN barrier, correspondingly turns the HEMT the normally-off devices without etching processes. Figure 1f
off. Finally, passivating layers (usually the SiO2 or SiNx) are shows the negatively charged F− ions injection beneath the gate
indispensable for the protection of device surface.[27–29] metal. The negative fixed charges can lift the conduction band
bending of AlGaN and further pitch off the 2DEG channel.[57,58]
Similarly, the thin/ultrathin-barrier GaN HEMT structure can
2.2. Normally-Off GaN HEMT Structures also deplete the 2DEG by modulating the height of AlGaN con-
duction band.[59,60] Generally, the thickness of barrier lower than
Due to reliability and safety concerns, normally-on HEMTs are 5 nm combined with normal Al content is named ultrathin-
less desirable in power switch system. To solve this problem, barrier (UTB), while the barrier as about 10 nm needs the Al
a few epistructures and technology are developed to fabricate content lower than 10% to maintain the appropriate 2DEG
normally-off (enhanced mode, E-mode) HEMTs and applied density. As demonstrated in Figure 1g, like the recessed-gate
by several leading companies, such as EPC (p-GaN gate), structure, the Vth will shift to the negative bias when the thick-
Panasonic (p-AlGaN gate), Transphorm (cascode), and NEC ness of AlGaN barrier below critical value (ignoring the effect

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Figure 1. a) Schematic device structure of normally-on GaN HEMT structure. Methods to achieve normally-off GaN HEMTs: b) p-(Al)GaN gate. c)
Recessed-gate MIS-HEMT. d) Recessed-gate MIS-FET. e) Cascode configuration. f) Fluorine gate. g) Thin/ultrathin-barrier HEMT structure.

of dielectric). However, these two structures are all limited by modified buffer structures are introduced, further improve the
some application problems, such as the reproducibility of the HEMT device performance.
injection process for fluorine gate and the low output current Power electronic applications require GaN HEMTs with
for thin barrier HEMT structures.[59,61] high vertical VBD that mainly depends on the epitaxial thick-
ness, but the serious wafer bow and cracks usually appear in
the thick and overstrained epistructures. To solve this problem,
3. Modified Buffer Structures the structure and growth conditions of buffer layers are opti-
mized to improve the quality of following epilayers. First, AlN
Most of GaN HEMT structures are heteroepitaxial grown on initial nucleation layer is deposited on the Si substrate to sup-
foreign substrates. As a result, high-density dislocations, pits, press the melt-back etching effect induced by Ga atoms.[62,63]
and cracks will be generated owing to the large materials dif- After that, the most important step is to compensate the lattice
ference between GaN and foreign substrates. In order to mismatch stress during the deposition procedure and thermal
grow high-quality GaN HEMT structures by MOCVD, several mismatch stress generated at the cooling process. Generally,

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Figure 2. a) Cross-sectional TEM images of buffer layers in GaN HEMT

structure, b) partially enlarged STEM image of the AlGaN step-graded
layers.

AlxGa1-xN/AlyGa1-yN (x > y) step-graded and GaN/AlN super-

lattices (SLs) strained layers are applied to prevent cracking
and yielding a flat wafer.[64–68] In addition, these buffer layers
play significant roles in blocking the treading dislocations
formed during the initial growth stage of the buffer, which can
remarkably increase the crystalline quality of GaN bulks.[69–72]
Figure 2a,b demonstrates the transmission electron microscopy
(TEM) image of typical buffer layers. Based on the optimized
growth temperature, pressure, V/III ratio and buffer structures,
Wakejima’s group achieved the total thickness of 8 µm for the
AlGaN/GaN HEMT epi-structure on 6” Si substrate.[73] The
normal thicknesses of GaN-based HEMT ranges from 2 to 6 µm Figure 3. Schematic structure of GaN HEMT with a) acceptor-doping
with the vertical breakdown field strengths of 1.5–2.72 MV cm-2, buffer and back barrier, b) LSR technology.
which can be realized via a series of buffer design works[74–78]
and approach the theoretical limit of GaN (3 MV cm-1). How-
ever, both the increasing thickness and lowering treading dislo- dynamic resistance (Ron, dynamic).[84,85] As a result, an AlGaN back
cations hardly contribute to the enhancement of the lateral VBD barrier is introduced to space the doping region from the active
of GaN HEMTs. access to avoid the charge trapping, as schematically demon-
Owing to the precursor-induced donor impurities and N strated in Figure 3a. The thickness and Al fraction of AlGaN
atoms vacancy, GaN bulks are normally n-type that delivers back barrier can be optimized to further suppress the off-state
high off-state leakage and low lateral VBD.[79] In this context, the leakage and CC.[86,87] Some recent literature data on the buffer
iron (Fe) or carbon (C) doping are applied to fabricate a semi- structure and leakage properties of GaN devices are reported in
insulating buffer layer. Iron and carbon primarily incorporate Table 1.
substitutionally on the nitrogen site as deep acceptor traps, As can be seen, several buffer designs are applied to fur-
increasing buffer resistivity and suppressing leakage and punch ther suppress the off-state current leakage. Mayank et al.
through of GaN-based HEMT devices.[80,81] However, the partial reported the profile of Si & C codoping in GaN buffer that the
channel electrons tend to be trapped by the surface or interface Si-doping is determined to compensate the acceptor traps.[88]
states near the 2DEG channel under low drain voltage. Fur- One of the highest VBD values of 2900 V was achieved by Lee
ther, more channel electrons will be trapped in the deep level group using the modulated C-doped GaN buffer and AlGaN
defects on the doping buffer under a high off-state drain bias. back barrier. They also proved that the CC of GaN HEMT
All these defect levels result in the decrease of output current increased from 35% to 45% when carbon atoms was doped
when the HEMT switched to on-state, so-called current collapse into the GaN buffer, while it decreased to 18% with an opti-
(CC) phenomenon.[82,83] The electrons trapping and detrapping mized AlGaN back barrier.[87] In addition, the AlGaN back
processes also lead to a Vth hysteresis behavior, which is usu- barriers doped with Si are applied to mitigate the decrease
ally observed in the MIS-HEMT devices due to the near-surface in channel conductivity resulting from C-doping semi-insu-
traps on the gate dielectrics. lating GaN buffer in Hao’s work. The maximum output cur-
The CC can be carried out by double pulsed I–V rent increased from 412 to 720 mA mm-1 with a low CC of
measurements: 7.8%.[86] The combination of SLs and doping in the buffer
structure can both enhance the vertical and lateral VBD in the
CC = (1 − I DS [VGS,Q ,VDS,Q ]/I DS @DC) × 100% (1) GaN HEMTs.[77]
In addition, the high VBD can be achieved by the local
where the quiescent bias conditions [VGS, Q, VDS, Q ] are based removal of substrate (LSR), because the breakdown field
at the Vth and a relatively higher drain bias, respectively. The strength of Si (0.3 MV cm-1) is far lower than the III-nitrides.
current collapse phenomenon could be also represented by the Srivastava’s group reported a series of works on the Si

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Table 1. Survey of literature data on GaN HEMTs using different doping buffer structures.

Doping buffer structure VBD [V] Off-state source–drain (Ioff) or buffer leakage current (Ib) @ VBD/2, Refs.
[mA mm-1)], CC or Rdynamic/Rstatic
2 µm GaN multiple-layers of C-GaN (12 nm)/UID-GaN (50 nm), 660 Ioff ≈ 1 × 10−2, CC ≈ 55% [89]
NA:C = 4.5 × 1018 cm−3
1.8 µm Al0.07Ga0.93N, NA:C = 6 × 1018 cm−3 871 Ioff ≈ 7 × 10−3 [21]
0.4 µm GaN, NA:C = 8 × 1017 cm−3 170 Ib ≈ 1.5 × 10−4, CC ≈ 38% [90]
3 µm GaN, NA:C = 4 × 1019 cm−3, NA:Si = 5 × 1017 cm−3 1500 Ioff ≈ 3 × 10−5 [88]
−3
2 µm GaN, NA:C = 1 × 10 cm , 3 nm Al0.05Ga0.95N back barrier −5
18 2900 Ioff ≈ 8 × 10 , CC ≈ 18% [87]
1.5 µm GaN, NA:C ≈ 1019 cm−3
15 nm Al0.1Ga0.9N back barrier, NA:Si = 1 × 1019 cm−3 780 Ioff ≈ 10−4, CC ≈ 7.8% [86]
3 µm AlGaN/AlN SLs, NA: C = 7 × 1017 cm−3 1.5 µm UID-GaN/C-GaN 2283 Rdynamic/Rstatic ≈ 1.15 [77]

substrate engineering.[91–93] The VBD of GaN double-hetero- Based on the thermal oxidation and oxide-wet-etching
structure field-effect transistors (DHFET) after removing the method,[103–105] a low-damage and self-limiting method called
substrate exhibits the enhancement of more than three times digital etching was developed to solve the etching damage
than the device with Si. The parasitic current conduction problem. As simplified depicted in Figure 4, the digital etching
across the nucleation AlN/Si interface was interrupted without processes for recessed-gate (a) and p-GaN gate (b) structures all
any impact on the 2DEG properties. Medjdoub et al. developed consist of five steps. First, a 100 nm SiO2 is deposited on the
a back-side LSR technology (Figure 3b) to etch the substrate top surface by PECVD. Then, the SiO2 on the gate region is
up to the buffer all around the drain of the HEMT, where the scaled for the recessed-gate structure to be a hard mask, while
VBD of 2500 V was achieved at 600 K, showing the potential the remaining region of p-GaN gate structure is reversed. One
of high-voltage power electronic devices for the harsh environ- etching cycle includes two steps: oxidation and oxide removal.
ment applications.[94,95] The VBD was further improved to more The chemical reactions for the oxidation of GaN and AlGaN are
than 3000 V after the LSR by applying the thick backside AlN described as:
and Cu depositions.[96]
4GaN + 3O2 → 2Ga 2O3 + 2N2 (2)

4. Low-Damage HEMT Fabrication Technology 2AlGaN + 3O2 → Ga 2O3 + Al 2O3 + N 2 (3)

Semiconductor fabricating processes generally more or less The III-oxide will act as the oxidation self-limiting layer
compromise GaN devices’ performance, especially the GaN or to block the increase in oxidation depth, then the oxide layer
AlGaN etching processes. In order to minimize the process- can be removed with the following diluted 20% HCl solution,
induced damage and impurities, various low-damage fabrica- and the treatment time is usually more than 90s to eliminate
tion technologies are developed. Most of these approaches focus the oxide completely. During the process, the etching cycle
on realizing the high-performance normally-off GaN HEMTs. will be repeated several times until the p-GaN or AlGaN is
fully removed. Finally, the SiO2 mask is etched away by BOE
solution.
4.1. Digital Etch Process In order to further realize the mechanism for oxidation of
III-nitride, Yu et al. reported digital etching processes with an
After the growth of GaN-based epilayers, a crucial process is oxidation-avoid layer.[106] In this work, several digital etching
removing the undesired layer and remaining the necessary cycles with 3-min oxidation time by ICP, 40W RF power and
region to form a HEMT structure, which called the selective 1.5 min wet etching time are applied to remove the III-oxides.
etching. In fact, the selective etching of p-GaN and AlGaN When the etching reached the AlN interlayer, the increase in
have received great attentions in fabricating the p-type gate etching depth nearly stopped. As plotted in Figure 5, the X-ray
and recessed-gate HEMTs in the last decades, respectively. photoelectron spectroscopy (XPS) of oxidation products proved
The oxygen is inclined to react with Al atoms,[97] while AlClx Al2O3 is the dominating oxide in this etching cycle. This phe-
complexes have lower volatility with respect to the Ga counter- nomenon revealed that the oxygen ion can hardly penetrate the
part.[98,99] As a result, the etching process based on the chlo- Al2O3 to oxidize the following GaN layer. Meanwhile, the wet-
rine- or oxygen-based gas as main etching agent by inductively etching process is too hard to remove the pure Al2O3 within
coupled plasma (ICP) or reactive ion etching (RIE), such as Cl2/ a short period. As a result, AlN interlayer really operated the
Ar,[100] Cl2/O2/N2,[101] and BCl3/SF6.[102] However, these etching etch-stop function on protecting the underneath GaN even the
processes will seriously affect the uniformity and surface mor- thickness is only 0.8 nm.
phology, resulting in under- or overetch phenomena and poor On the other hand, Yu et al. also studied an oxygen-based
contact characteristics. p-GaN digital etching procedure.[107] By applying different ICP

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Figure 4. Simplified diagrams showing the cross sections of the digital etching process: a) recessed-gate structure, b) p-GaN gate structure.

power, RF power, O2 flow of the ICP plasma oxidation, the depth is limited for 3.62 nm, consist with the STEM and energy
p-GaN etching depth in one cycle hardly increased when the disperse spectroscopy (EDS) mapping. In addition, the O atoms
O2 flow exceed 40 sccm and ICP power exceed 100 W, indi- distribution at p-GaN surface for different steps are demon-
cating that the concentration of O2 is saturated for oxidizing strated in details by combining XPS with EDS results, revealing
the p-GaN. Meanwhile, the etching depth enhanced more than the oxidation mechanism of p-GaN. This technique has been
two times when the RF power raised from 40 to 75 W, which revealed to accurately modulate the etching depth and surface
will result in more etching damage and instability. Per etching morphology of p-GaN/AlGaN structure.

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GaN HEMTs,[108,109] which generally feature excellent on-state

performance and dynamic characteristics because the possible
damage caused by etching is avoided.
The Vth of a Schottky gate can be expressed as:[110]

qN d d σ
Vth = ϕ m − ∆E c − − d (4)
2ε ε

where φm is the Schottky barrier height, and ΔEc is the conduc-

tion band offset between barrier and channel layer. Nd, d, and ε
are the doping concentration, thickness, and dielectric permit-
tivity of the barrier. σ is the total sheet charge density at the
AlGaN/GaN heterojunction induced by polarization. According
to Equation (4), either increasing the work function of gate
metal[111] or reducing the barrier doping,[112] thickness,[113] and
polarization charges can increase the Vth. Besides, according to
the piezoelectric effect of GaN-based semiconductors, applying
foreign strain to the devices can build up a polarization field in
the semiconductor and hence modulate the threshold voltage,
as the Ppe,ext shown in Figure 6a. SiNx stress liners have been
used to introduce external strain to different electronic devices
for electric performance modulating.[114,115] As a result, the
normally-off GaN HEMTs can be also realized by using SiNx
stress liner. Figure 6b demonstrates the edge force model that
a compression is built in the gate region after etching the com-
pressive SiNx.[116] The compression translating to the polariza-
tion charge can lift the conduction band and deplete the 2DEG,
further realizing the normally-off operation (Figure 6c).

Figure 5. XPS measurement of oxidation products after a,b) the oxidation

for AlGaN and c,d) for the AlN/GaN structure before the wet etching. 4.3. Selective Area Growth
Reproduced with permission.[106] Copyright 2019, American Vacuum
Society. As mentioned above, normally-off GaN HEMTs are achieved
by reducing the 2DEG density at the gate region of heteroint-
4.2. Strained Engineering erface. The Vth modulated by strain engineering can be hardly
more than 1 V, while the etching process will unavoidably intro-
Even though oxygen-based digital etch guarantees excellent duce the physical damages to the active region, further influ-
surface morphology and accurate etching depth, it is hard to encing the reliability and stability of device.[117,118] In order to
be put on mass production applications. Regarding that, strain solve this problem, a regrown-barrier based on thin-barrier
engineering is developed to conduct a recess-free normally-off structure is applied to achieve a recess-free normally-off GaN

Figure 6. a) Directions of spontaneous (Psp) and piezoelectric (Ppe) polarization in metal-face AlGaN/GaN heterostructures. The piezoelectric polari-
zation induced by external strain (Ppe,ext) is also plotted. b) Conduction band diagram at the dash line of gate area on an AlGaN/GaN HEMT with
compressive SiNx stress liner. The stress liner creates a compression in the gate region and lifts the conduction band. c) Transfer curves of AlGaN/
GaN HEMTs applying SiNx stress liner (strained device) and nonstressed SiNx (baseline). The device with stress liner shows one-volt higher Vth and
normally-off characteristics (inset). Reproduced with permission.[109] Copyright 2020, IEEE.

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Figure 7. Fabrication process of regrown-barrier normally-off GaN HEMTs.

HEMT fabrication process.[119–121] The process flow is dem- where gm is the maximum transconductance of HEMT device,
onstrated in the Figure 7, which also called the selective area C is the unit dielectric capacitance, Lg and Wg represent the
growth (SAG) process. length and width of recessed region. It is used to describe
SiO2 is deposited on the thin-barrier surface by PECVD and the channel transport property of recessed-gate HEMT. Liu
selective removed by BOE solution as a regrown mask on the et al. reported a normally-off GaN HEMT with Vth = 2.5 V
gate region. Then, the regrown-barrier is selective grown on by applying a 20 nm regrown Al0.3Ga0.7N barrier, which also
the access region to form a recessed-gate structure without achieved the highest μFE of 2033 cm2 V-1 s-1 for the recessed-
etching process. Especially, the Al fraction y of regrown-bar- gate GaN HEMT with an Al2O3 gate dielectric.[128] Meanwhile,
rier is equal or higher than the counterpart x of the thin-bar- Lau et al. reported the similar regrown-barrier structure
rier to maintain the high conductivity transport property of with a high-k gate dielectric ZrO2 that the high-quality gate
2DEG channel. Finally, the SiO2 mask is removed by BOE, the stack results in a highly uniform and small hysteresis in the
source/drain metal, gate dielectric and gate metal are succes- recessed-gate MIS-HEMTs.[127] Especially, regrown-AlGaN on
sively deposited to fabricate a normally-off GaN-HEMTs.[122,123] dry-etching GaN surface were also studied by Kuzuhara et al.
Due to the absence of etching process on the recess region, to achieve a high Vth of 5 V.[129]
the lattice damage and interface traps are greatly reduced, In addition to the regrown-AlGaN barrier, another etch-free
which contributes to enhance the channel conduction. Recent method to recover 2DEG in the channel is to deposit passiva-
works of the regrown-barrier GaN HEMTs are summarized in tion layers with high-density positive fixed charges on ultrathin-
Table 2. barrier heterostructures.[130,131] Meanwhile, the passivation
The parameter μFE is the denotation of “field-effect mobility”, layers on the gate region are replaced by other dielectrics which
expressed as: positive fixed charges density are lower than the polarization
charges of GaN to maintain a high Vth.[132,133] The effect of fixed
µFE = Lg /(WgVDSC ) × g m (5) charges is detailly discussed in the next section.

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Table 2. Survey of literature data on regrown-barrier structure.

Barrier structure Vth [V] Ron [Ω mm] μFE [cm2 V-1 s-1] Dielectric Refs.
10 nm Al0.25Ga0.75N, 15 nm regrown Al0.25Ga0.75N 0.4 10.6 703 Non [120]
1.5 nm AlN + 1 nm GaN, 20 nm regrown AlGaN 0.2 3.6 880 7 nm Al2O3 [124]
80 nm regrown GaN, 0.5 nm regrown AlN, 30 nm regrown AlGaN 2.5 9.6 192 30 nm Al2O3 [125]
5 nm Al0.2Ga0.8N, 40 nm regrown Al0.2Ga0.8N 1.7 – – 20 nm Al2O3 [126]
6 nm Al0.2Ga0.8N, 20 nm regrown Al0.3Ga0.7N 2.19 9.2 850 23 nm ZrO2 [127]
5 nm Al0.2Ga0.8N, 20 nm regrown Al0.3Ga0.7N 2.5 6.8 2033 25 nm Al2O3 [128]
25 nm recess-GaN, 3 nm regrown Al0.25Ga0.75N 5.0 12.9 – 25 nm Al2O3 [129]

5. MIS Structure gate structure, the leakage current can be well suppressed if
the conduction band offset (ΔEc) of metal/dielectric (reverse
Initially, the MIS structure was an intuitive method on bias) and semiconductor/dielectric (forward bias) are large
reducing the gate leakage of GaN-based HEMTs. The gate enough.
leakage of HEMTs can be discussed separately in the reverse MIS gate structure is then generally mandatory for most
bias region and forward bias region. Figure 8a,b shows the normally-off devices, such as gate-recessed HEMTs,[43,136] fluo-
TCAD simulated transfer curves of Schottky gate HEMTs and rine treated HEMTs,[61,137] selective regrowth,[127] thin-barrier
MIS HEMT together with their band diagrams under positive heterostructure,[138] and strain engineered devices.[139] Other-
and negative bias conditions. For the Schottky gate under a wise, the Schottky gate will be turned on at approximately Vg =
negative bias, the electrons are revealed to inject through 2 V,[61,137,139] limiting the gate overdrive voltage and hence the
the triangular barrier with Fowler-Nordheim (FN) tunneling, output performance. Figure 8c shows the output characteristics
Poole-Frenkel (PF) emission, trap-assisted tunneling (TAT), or of a novel normally-off HEMT using strain engineering with
their combination, depending on the epitaxial structure and the Schottky gate.[139] The severe gate leakage appears when Vg
quality.[134,135] In the forward region, the electrons in the 2DEG over 1.5 V, limiting the overdrive Vg. As a result, the output per-
conducting channel spill over to the gate electrode at approxi- formance, including Ron and output current, is corrspandingly
mately Vg = 2 V, causing a severe gate leakage. For the MIS limited by the maximum gate bias (Vgm).

Figure 8. Simulated transfer characteristics of a) Schottky gate HEMTs. b) MIS-HEMTs. c) Output characteristics of the normally-off HEMT using strain
engineering lacking MIS structure (Vg sweeping from 0 to 2.5 V). d) Band offsets between the common dielectrics and (Al)GaN.

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Table 3. Survey of literature data on MIS gate structure.

Gate region structure Deposition methods PDA On/off ratio Vgm [V] Remark Refs.
HfO2/GaN/Al0.25GaN (20 nm/2 nm/20 nm) ALD 600 °C/60s/N2 2.1 × 10 9 0 O3 precursor [142]
Al2O3/Al0.24GaN (8 nm/20 nm) ALD 300 °C/600s/N2 7 × 1010 4 O3 precursor/ pretreatment [143]
Al2O3/Al0.3GaN (4.1 nm/20 nm) Thermal oxidation – 5.1 × 109 5 – [144]
Al2O3/Gain/Al0.2GaN (10 nm/1 nm/25 nm) ALD 400 °C/ -/O2 1× 1010 8 O2 plasma precursor [145]
Al2O3/Al0.26GaN/Alyn (20 nm/25 nm/1 nm) ALD 700 °C/ 60 s/N2 – – H2O/O3 precursor [146]
Al2O3 (18 nm) ALD 400 °C/ 600 s/N2 ≈108 14 Fully recessed [147]
Al2O3/GaN/Al0.2GaN (25nm/-/-) ALD 500 °C/-/O2 ≈1010 6 N2 plasma pre-treatment [148]
TiO2/Al0.3GaN (3.4 nm/20 nm) Thermal oxidation - 2.3 × 108 5 – [144]
SiNx/Al0.23GaN (30 nm/2 nm) PEALD /ICP-CVD 500 °C/ 600 s/N2 – 9 Partially recessed [149]
SiNx (30 nm) PEALD /ICP-CVD 500 °C/ 600 s/N2 – 9 Fully recessed [149]
SiNx/AlGaN/AlN (20 nm/20 nm/1 nm) LPCVD – 1 × 109 20 GaN cap removed [28]
SiNx/AlGaN/AlN (20 nm/20 nm/1 nm) PECVD – 1× 107 10 GaN cap removed [28]
SiNx (30 nm) PEALD /ICP-CVD 500 °C/ 600 s/- 1 × 107 10 Fully recessed [150]
SiNx (15 nm) LPCVD – ≈109 15 Oxidation interlayer [151]
LaO/Al0.3GaN (5 nm/24 nm) E-beam evaporator 500 °C/ -/N2:H2 2 × 10 4 0 – [152]
LaHfO/Al0.22GaN (8 nm/25 nm) MBD 600 °C/ -/- 3 × 106 6 LaO/HfO multi layer [153]
LaLuO3/GaN/Al0.26GaN (16 nm/2 nm/18 nm) MBD 400 °C/ 600 s/O2 – 3 F− implantation [154]
Ta2O5/In0.17AlN/AlN (24 nm/10 nm/1 nm) Sputter 500–700 °C /600 s/FG ≈107 2 – [132]

The MIS gate structure enables the devices to operate with overdriven with as high Vg as possible for demonstrating output
a higher gate swing and the lower gate leakage than the p-GaN performances.
gate HEMTs. However, the MIS structure introduces other chal- The strength of dielectrics is generally represented in their
lenges on the Vth stability, mainly caused by the fixed charges breakdown electric field (MV cm-1). For an atomic-layer depos-
or the traps at the semiconductor/dielectric interface. In this ited (ALD) Al2O3 with optimized deposition and postdeposition
section, the primary challenges and the efforts being made in annealing (PDA) conditions, the breakdown electric field attains
the pursuit of the high-performance MIS gate structure are >9 MV cm-1.[155] Equivalently, every one-nanometer Al2O3 can
reviewed. endure every 0.9 V Vg bias. Therefore, to design MIS HEMTs,
the dielectrics are generally thicker than 12 nm to attain >10 V
gate swing, consistent with the survey summarized in Table 3.
5.1. Gate Dielectric Candidates Regarding the Ion/Ioff ratio, the MIS HEMTs generally attain
over 108, indicating the well-suppressed gate leakage. Besides
Factors affecting tunneling gate leakage include conduc- the dielectric thickness and band offset, the gate leakage is
tion band offset for electrons, the effective mass of electrons also dominated by the dielectric/semiconductor interface and
in dielectrics, and dielectric thickness. The band diagram dielectric quality. The poor quality of interface also leads to the
between (Al)GaN and common dielectrics are summarized in instability of Vth.
Figure 8d.[140] From experiences in CMOS technology, the tun-
neling leakage can be well controlled when the conduction
band offset is larger than 1 eV.[141] With this criterion, most 5.2. Interface Engineering
of the listed dielectrics shown in Figure 8d can be candidates
except for TiO2. During the testing of transfer characteristics, the Vg sweeps
Table 3 summarizes the MIS gate options in the literature, from low bias (device off) to high bias (device on), and then
together with the Ion/Ioff ratio and Vgm of devices. The Ion/Ioff from high bias back to low bias, turning out two transfer curves.
ratio is an indicator of the ability of gate dielectrics to sup- The Vth difference between the two transfer curves is known
press gate leakage. When the MIS gate of HEMTs are positively as the hysteresis. As mentioned at the beginning of this sec-
biased, the gate voltage almost drops on the dielectrics, so we tion, the free electrons spillover to the dielectric/semiconductor
can test the strength of the dielectrics by positively biasing interface when the gate is forward biased, as the condition of
Vg, regardless of the barrier structure. It should be noted that Vg = 2 in Figure 8b. Then, the electrons are trapped at the inter-
the Vgm highlighted here represents the highest gate voltage face states, inducing an electric field when the Vg sweep back
the devices operate in the articles, not the gate VBD. Even so, to the subthreshold region, leading to the Vth hysteresis.[156] In
to a certain extent, the Vgm in Table 3 can be an indicator of contrast, the device would not show severe hysteresis if the gate
the strength of the dielectrics because the devices are generally is reversed biased throughout the test, because the electrons

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can hardly reach the dielectric/semiconductor interface. There-

fore, the hysteresis is a challenge mainly for the normally-off
devices.
The hysteresis is a result of the traps at the dielectric/semi-
conductor interface. Therefore, the efforts have been made
to reduce the interface traps. The surface oxidation and nitri-
dation have been widely studied to improve the dielectric/
semiconductor interface quality and reduce the hysteresis.
ALD in-situ ozone pretreatment before gate oxide deposition
was proved to be capable of decreasing the off-current and
reducing the hysteresis for Al2O3.[143] The ozone treatment
creates a Ga2O3 interlayer, shifting the Ga 3d peak to higher
binding energy.[143] Hua et al. implemented oxygen plasma
treatment before LPCVD gate dielectric deposition, creating
a GaON interlayer.[151,157] The GaON layer can prevent the
GaN from degradation (e.g., Ga or N vacancy) during high-
temperature dielectric deposition. Besides, the GaON layer
crystallized during 780 °C LPCVD SiNx deposition. The hys-
teresis behavior, output characteristics, and Vth stability are
improved with the GaON interlayer. Furthermore, due to the
ΔEv between GaN and GaON, the additional hole barrier can
be formed in the gate region, suppressing the hole-induced
dielectric degradation. Figure 9. a) Charge distribution in the MIS and heterojunction interfaces
Ga dangling bonds and nitrogen vacancies are known as the at the flat-band condition. Polarization charges (Qp) include the charges
main defects of the Ga-face wurtzite GaN after high-tempera- caused by piezoelectric and spontaneous polarization. b) A typical
ture processes such as Ohmin contact annealing.[158,159] Hence, example of positive fixed charges reduction by implementing post-gate
annealing (PGA) or post-deposition annealing (PDA). Reproduced with
interface engineering has been aimed to passivate Ga dangling
permission.[147] Copyright 2017, IEEE.
bonds and compensate N vacancies, which was implemented
by applying in situ NH3/Ar/N2 remote plasma pretreatment
(RPP) in a plasma-enhanced atomic layer deposition (PEALD) the suppressed hysteresis, improved output performance, off-
system.[148,159,160] A crystalline AlN was observed when the NH3/ state characteristics, and dynamic characteristics.
Ar/N2 RPP was implemented before Al2O3 deposition. The As summarized in Table 3, postdeposition annealing (PDA)
AlN interlayer not only provides superior passivation quality is mandatory for dielectrics with low deposition temperatures,
but also prevent the GaN oxidation during Al2O3 deposition. such as ALD and evaporator. An optimized PDA process is
The introduction of NH3/Ar/N2 RPP suppresses the hysteresis useful for relieving the hysteresis and gate leakage.[146,165] How-
and improve the output performances. A similar result can be ever, the metal oxide may crystallize under the temperature
realized by depositing a thin AlN layer using PEALD to form over 600 °C and become leaky.[146] Therefore, the common PDA
the AlN/Al2O3 dual-layer gate dielectrics.[161] Besides, AlN was temperature is controlled below 600 °C. The PDA temperature
proved to provide excellent passivation quality to the GaN sur- over 600 °C is used only with short PDA time.
face.[162] However, due to the small ΔEc between AlN and GaN,
the use of AlN alone as the gate dielectric cannot well suppress
gate leakage.[163] 5.3. Fixed Charge Engineering
ALD is generally used to prepare the gate dielectrics, and
the dielectric/semiconductor quality was observed to be influ- The MIS structure is mandatory for normally-off HEMTs.
enced by the precursor kinds. Compared with the Al-rich Al2O3 However, it was generally observed that the Vth decreases after
prepared using ALD with H2O as the precursor, using O3 as introducing the gate dielectrics. The Vth decrease is believed to
precursor can reduce the defective bonds (such as AlAl and be a result of the positive fixed charge between gate dielectric
AlOH bond) and increase AlO bond compared by using and GaN-based compound.[166,167] Figure 9a shows the charge
H2O, and the composition can be close to Al:O = 2:3.[164] distribution in the MIS and heterojunction interfaces for the
Besides, compared with O2 plasma as a precursor, O3 cause Ga-face AlGaN/GaN system.[168–170] Qp1 and Qp2 represent the
less surface damage. With the Al2O3 deposited with O3, the charges caused by both piezoelectric and spontaneous polari-
devices attain a lower Ioff and hysteresis compared with H2O zation. Qf is the fixed charge at the dielectrics/semiconductor
as the precursor. Similar results are also observed on ALD interface. In Figure 9a, the bulk charges in the dielectrics are
HfO2. The double pulse for oxidation periods also leads to neglected for simplification. Based on the model, the Vth dif-
the different dielectric characteristics, implying that the oxi- ference (ΔVth) between MIS HEMTs and Schottky gate HEMTs
dation level matters to the film quality.[142] Another oxidant to can be expressed as:
increase the oxidation level is the remote oxygen plasma.[145]
By inserting an oxygen plasma after each H2O oxidation, the  Q p2 Q f 
∆Vth = Vth _ MIS − Vth _Schottky = −  + (6)
AlAl and AlOH bonds are well eliminated, projecting to  C ox C ox 

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where Cox is the capacitance of the dielectrics layer. For the Ga- to form low-resistance metallic or semimetallic compounds,
face system, Qp2 is generally negative. Hence, the positive fixed such as TiN and TaN, lowering the Schottky barrier height of
charges Qf with a magnitude larger than -Qp2 lead to the nega- metal/semiconductor interface. Meanwhile, with the extraction
tive ΔVth. The positive fixed charge exist between GaN and ALD of N atoms by bottom metals, high-density vacancy of N (VN)
Al2O3,[147,171,172] CVD SiO2,[173] CVD SiNx,[173] Sputtered Ta2O5,[132] is remained in the AlGaN, which can act as shallow donors to
and in situ MOCVD SiNx.[174] The positive fixed charges facilitate Ohmic contacts.[177] The second layer Al is an excellent
decrease the Vth, and make it harder to realize normally-off coating metal to promote the solid-phase reaction of metal/GaN
operation. and tend to form compacted alloys with low work-function.[178]
Generally, the positive fixed charge was reduced via PDA The third high-melting metal is applied to block the inward
process. Figure 9b shows a typical example of fixed charge diffusion of Au,[179] such as nickel (Ni), Ti, platinum (Pt), palla-
reduction.[147] Because of the high positive fixed charge, the dium (Pd), molybdenum (Mo), rhenium (Re), and iridium (Ir).
device was still normally-on even though the barrier layer was The top Au layer is a protecting metal to prevent the electrode
fully recessed. Supported by the first principle calculation, oxidation. Otherwise, Liu et al. reported that part of bottom
Zhou et al. explained that the positive fixed charges are a result metal atoms can flow upwards and contacts the Au layer
of N vacancy defects and GaO bonds caused during etching to form binary alloys during the annealing process, further
and ALD processes, respectively, and they act as positive charge reducing the resistance.[180] In fact, the TiN generated at special
centers.[147,175] The charged defects can be restored by incorpo- temperature in the Ti/Al/Ti/Au can partially penetrate inward
rating N during N2 PDA or PMA, and the Vth increases to attain the AlGaN barrier, even directly contact with the 2DEG on the
the normally-off operation. Similar phenomena and explana- AlGaN/GaN interface, resulting in an ultralow contact resist-
tions were also reported for Ta2O5/InAlN systems.[132] A posi- ance (Rc).[181] Furthermore, Nam et al. applied the thermionic
tive move of Vth after N2 PDA was also reported for the SiON/ field emission (TFE) model to explain the reduction in Rc when
Al2O3/AlGaN system.[176] Sun et al. also claimed the negative the distance between metal complexes and 2DEG channel con-
fixed charge at the Al2O3/AlGaN.[176] However, the charges are stantly decreased.[182] The electrons can tunnel from TiN/AlGaN
measured and extracted on the SiON/Al2O3/Si sample instead interface to the 2DEG when the thickness of residual AlGaN
of SiON/Al2O3/GaN system, making the data less convincing. between channel and TiN is ultrathin. As a result, it has been
The negative fixed charges after forming gas (N2:H2 = 97%:3%) confirmed that the annealing temperature, thickness of AlGaN
were reported in the La2O3/AlGaN system, but the mechanism barrier and each metal layer can be optimized to achieve a spe-
behind that was not discussed.[152] In contrast to N2 PDA, Hung cific contact resistivity of 10−6–10−7 Ω cm2.[179,183]
et al. used O2-plasma pretreatment combined with PMA, and Though the Au top layer can promote the downward penetra-
the positive fixed charge is also reduced.[171] tion of TiN to contact with 2DEG, there are still a lot of limita-
Replacing H2O by O3 as the ALD precursors for either tions due to the high diffusivity of Au and irregular extension
Al2O3 or HfO2 also leads to a positive Vth shift.[142,143] It can be of TiN, such as the unstable resistance and rough electrode
assumed that the use of O3 as the precursor may reduce the surface.[178,184–186] Furthermore, considering the compatible fab-
positive fixed charge, but the Vth and fixed charges change were rication on mature Si-based production line, it is necessary to
not discussed in the corresponding articles. develop the Au-free Ohmic contact technology.
Generally, the Au-free metals based on the Ti/Al or Ta/Al
stack with TiN or wolfram (W) cap layers, which can also create
6. Metal/Semiconductor Contacts inward TiN or TaN compounds and plenty of VN in AlGaN
during the annealing process to form Ohmic contact. Owing to
The electrodes of GaN-based HEMT usually employ the metal the lack of Au, the TiN or TaN can uniformly distribute on the
materials. The metal/semiconductor contact characteristic acts metal/AlGaN interface, and the electrode surface is relatively
a significant role in the electrical characteristics of GaN HEMT, smooth. Shriki et al. reported that the thickness of TiN in the
such as the gate VBD, Ron, and output current. Generally, the metal/GaN interface increased with the annealing temperature
gate electrode form a Schottky contact with rectification prop- lifted, further reducing the Rc to 0.2 Ω mm when the tempera-
erties, while the Ohmic contact is applied on the source and ture reached up to 930 °C.[186] Li et al. introduced complex Ta/Si/
drain regions. In this section, several innovative technologies Ti/Al/Ni/Ta multiple metals to achieve a low Rc of 0.22 Ω mm
to improve the metal/semiconductor contact characteristics and by utilizing the low work-function of Ti/Si/Ta compounds.[187]
device performance are discussed. According to the TFE model mentioned above, decreasing the
distance between 2DEG and metal contributes to lower the
Ohmic Rc, which were also verified by using a recessed struc-
6.1. Low-Resistance Ohmic Contact ture with Ti/Al/W (Rc = 0.49 Ω mm, fully-recessed) and Ti/Al/
Ti/TiN (Rc = 0.21 Ω mm, partially recessed).[179,188] The 2DEG in
Owing to the wide bandgap of GaN-based materials, it is chal- the fully recessed structure directly contacts with the side wall
lenging to make good Ohmic contacts using single metal layer. of metal electrodes. The optimized etching level is necessary to
For the Ohmic contact with AlGaN, the most popular metals keep good Ohmic contact properties.[177,189,190]
multilayers are X/Al/Y/Au, where X is usually the titanium (Ti) As mentioned in previous section, various practical prob-
or tantalum (Ta) and Y is usually the high-melting metal. The lems, in terms of the time cost and rough contact surface,
bottom metal X directly contacts with AlGaN, in which the low increased the difficulty on achieving the recessed Ohmic con-
work-function is necessary to conduct a solid-phase reaction tact. In this context, Yu’s group developed novel procedures

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probability of injected electrons. It was explained that the Rc of

Ti5Al1 alloys rapidly deteriorated under the annealing temper-
ature of 950 °C. In contrast with the low-Ti-ratio TixAly alloys
(x < y), the migration of Al atoms in the Ti5Al1 alloys can be
enhanced at a higher temperature atmosphere. The excess out-
diffusion of Al atoms could decrease the polarization charges
density and degraded the heterostructure quality, further
increase the Rc.
As observed in the EDS analysis results, the out-diffusion of
N atoms was mainly consistent with Ti profile. It is revealed
that the vacancy of N, which can provide extra donor impuri-
ties, dominantly results from the extraction effect of Ti. In
addition, the contact interface of Ti5Al1 is flatter than the other
alloys, indicating the effective suppression of interfacial ele-
ment mixing, which also promotes the formation of excellent
Ohmic contact. This work revealed a novel method to achieve
the world’s lowest Au-free Ohmic contact resistance of 0.063 Ω
mm, as compared with other Au-free Ohmic contact works on
AlxGa1-xN (x ≈ 0.25) in Table 4.
In addition, another low-resistance Ohmic contact was
achieved by Yu’s group using the TaxAly/Au stacks.[202] Unlike
TixAly alloys, the extraction of N atoms was not suppressed
owing to the little formation of Ta-nitride. Meanwhile, the
Ta–Al–Au system mixed more uniformly with each other than
the Ti–Al–Au, indicating that the Au atoms can penetrate the
AlGaN barrier without spike-like electron tunnels to contact the
2DEG. As a result, the Rc was effectively reduced by the recess-
like contact mechanism. The role of Ta in TaxAly/Au stacks was
clearly revealed and the process of alloy diffusion can be further
applied to the GaN-based HEMTs.

6.2. Graphene Insertion Layer

Figure 10. The EDS analysis, TEM and content mapping images of TixAly/
AlGaN structures for a) Ti1Al5, b) Ti1Al1, c) Ti5Al1. Reproduced with per-
Among many options of normally-off HEMTs, p-GaN gate
mission.[191] Copyright 2020, IEEE.
structures are regarded as the most suitable method to achieve
the large-scale commercial application.[203,204] However, due to
of Ti–Al alloys instead of Ti/Al multilayers as contact metals the lack of gate dielectric in metal/p-GaN structure, the gate
to form Au-free Ohmic contact on nonrecessed AlGaN/GaN leakage current will rise rapidly when the gate forward voltage
heterostructure.[191] Compared with the Ti/Al/TiN stacks become higher, limiting the voltage swing. Meanwhile, the neg-
(minimum Rc = 0.4 Ω mm) deposited by magnetron sput- ative bias induced leakage current will cause the consumption
tering, the TixAly alloy grown on the same condition shows of electrical energy when the device is turn-off.[205] The gate VBD
a lower Ohmic Rc of 0.063 Ω mm. In order to reveal the of metal/p-GaN structure is also lower than the GaN HEMTs
mechanism of Rc reduction, Yu’s group fabricated a series with insulated gate, which brings serious burden to the driver
of TixAly alloys on the AlGaN/GaN surface with varied ratios design.[206]
of Ti and annealing conditions. The Rc decreases gradually In order to improve the contact properties of noninsulated
as the alloy proportion of Ti increased under the optimized metal/GaN structure, 2D materials, especially the graphene
annealing temperature. (Gr), have been introduced to overcome these limitations. It
As shown in Figure 10, the out-diffusion of Al atoms was has reported inserting Gr on barrier surface before depositing
effectively suppressed, while the Ti atoms diffused strongly the gate metals can improve the contact properties.[207,208] The
into the AlGaN barrier. With the Ti content in the TixAly alloy Schottky barrier height (SBH, ΦB) can be lower to 0.4–0.6 eV
increased, the depth and area of Ti in-diffusion constantly with different metal work functions. The chromium (Cr)/gra-
enlarged and more N atoms are extracted into the alloy layer. phene composite electrode was applied to simply make Ohmic
These phenomena indicated that the application of high-Ti- contacts on AlGaN/GaN heterostructures, while single Cr and
ratio TixAly alloys contribute to formatting a n-type AlGaN con- Gr still lead to Schottky contacts.[209] It was revealed that Cr/
tact area and the deep penetration of TiN, further resulting in Gr/AlGaN composite layers shows the similar energy band
an ultralow Ohmic Rc. Meanwhile, a limited Al out-diffusion structure with underlying GaN, where the strong interaction
(Figure 10c) in the Ti5Al1 alloys is beneficial to lower the AlGaN between Cr and graphene makes it behave like a semiconductor
bandgap, leaning to an increase in the tunneling transmission with wide band gap.[210]

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Table 4. Survey of literature data on Au-free Ohmic contact.

Structure Metal stack [nm] PDA Rc [Ω mm] Refs.

Nonrecessed Ti/Al (70/180) Ar/500 °C 3 min/800 °C 30 s 1 [192]
Ti/Al/Ni/Pt (20/60/40/50) N2/975 °C/30 s 0.57 [193]
Ta/Al/Ta (20/280/20) N2/600 °C/60 s 1.45 [194]
Ta/Al/Ta (10/140/20) N2/550 °C/60 s 0.54
Ta/Al/Ta (10/70/20) N2/575 °C/60 s 0.47
Ta/Al/Ta (10/210/20) N2/600 °C/60 s 0.42
Ta/Al/Ta (10/280/20) N2/600 °C/60 s 0.28
Ti/Al/Ti/TiN (25/120/20/20) N2/850 °C/45 s 1.07 [195]
Ti0.16Al0.84/TiN N2/600 °C/90 s 0.9 [196]
Ti0.27Al0.73/TiN N2/850 °C/90 s 0.75
Ti/Al/W (40/100/60) N2/850 °C/30 s 0.93 [197]
Ta/Si/Ti/Al/Ni/ N2/850 °C/30 s 0.22 [187]
Ta (5/5/20/120/40/30)
Ti/Al/Ti/TiN (20/100/20/60) N2/900 °C/60 s 0.2 [186]
Recessed Ti/Al/Ti/TiN (20/100/20/60) N2/550 °C/90 s 1.25 [186]
Ti/Al/Ti/W (20/120/20/30) N2/600 °C/120 s 1.12 [198]
Ti/Al/W (20/100/20) N2/600 °C/60 s 0.65 [199]
Ti0.05Al0.95/TiN (60) N2/550 °C/90 s 0.62 [200]
Ti/Al/W (60/100/30) N2/870 °C/30 s 0.49 [188]
Ti/Al/Ti/TiN (2.5/100/20/60) N2/550 °C/90 s 0.21 [201]
Ti5Al1/TiN (60/60) FGA/900 °C/60 s 0.205 [191]
Ti5Al1/TiN (60/60) FGA/880 °C/60 s 0.063

In addition to the reduction in ΦB, combined graphene GaN.[215] In addition, the remote surface scattering induced by
with AlGaN containing in situ generated V-shaped defects on graphene on AlGaN/GaN heterostructures was discussed by
the surface is easier to form Ohmic contact.[211] This V-shaped Lu’s work.[218] The remote scattering caused by surface rough-
defects naturally reduced the AlGaN thickness at pits regions, ness and interfacial charge are reduced, as the dangling bonds
providing preferential electron injecting track to the 2DEG and defects on surface can be compensated by applying the gra-
channel, as shown in Figure 11. Meanwhile, the wrinkles of phene passivation.
single graphene also become high-conductive paths to enhance Yu et al. reported the effectiveness of intrinsic and fluori-
the Ohmic characteristics, while the counterpart of defect- nated graphene (I-Gr and F-Gr) in p-GaN HEMTs.[219] As
free area typically exhibited Schottky behavior.[212] Cho et al. shown in Figure 12a, the p-GaN HEMT structures consist of
reported that the extracted ΦB of the Gr/AlGaN/GaN structure 100 nm p-GaN/15 nm Al0.2Ga0.8N/0.7 nm AlN/300 nm GaN
raised as the Al composition of barrier increasing. It was also channel/4.2 µm AlGaN buffer/Si substrate. Before depositing
revealed the ΦB will saturate with higher Al contents due to the Ti/Au gate electrodes, the transformation of a graphene
rising reverse leakage current, which is affected by the pinning monolayer on p-GaN surface was conducted by the “polymeth-
of Fermi level on AlGaN barrier.[213] ylmethacrylate (PMMA)-mediated” wet transferring method.[220]
The graphene acted as a passivation layer on AlGaN/GaN The Gr-deposited p-GaN HEMTs have higher Vth of 1.86 V
heterojunction was studied by Cheng’s group.[214,215] Prior to with I-Gr and 1.82 V for F-Gr compared with the baseline
transferring the graphene, they found that the Gr monolayer device, where the increase should be attributed to higher ΦB
insulated by fluoridation (existence of bandgap) could effec-
tively reduce the leakage paths on the AlGaN surface at reverse
and low forward bias. On the other hand, an intrinsic graphene
inserting between the Schottky gate and barrier contributed to
the suppression of gate current leakage and providing a posi-
tive shift on flat-band voltage.[214] It is speculated that the pris-
tine graphene was strongly bonded via sp2 hexagonal hybridi-
zation with a radius of 0.71 Å, which helped to suppress the
atom diffusing.[216,217] As a result, the graphene can act as a Figure 11. Energy band schematic of a) defect-free Au/AlGaN, b) Au/
diffusion-prevention layer to compensate the surface donor-like Gr/AlGaN (solid line) on defect-free and V-defect (dashed line) regions.
traps, preventing the oxidization and N atoms out-diffusion of Reproduced with permission.[211] Copyright 2014, AIP Publishing.

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Figure 12. a) P-GaN gate HEMTs schematic with I-Gr/F-Gr insertion layer. Cross-sectional STEM images b) without Gr and c) with I-Gr, EDS results
of d) voids and e) TiN at baseline interface, f) TiN at Gr-inserted interface, g) IG versus VG and gate VBD properties before and after annealing. h)
Benchmark for p-GaN gate HEMTs of Vth and gate VBD. Reproduced with permission.[219] Copyright 2020, IEEE.

of the metal/Gr/GaN structure. Additionally, the Ion/Ioff ratio The variation of gate current leakage and VBD characteristics
increased more than ten times after applying the graphene is presented in Figure 12g. When the positive VG increased, the
insertion layers. The device reliability was improved without any IG was correspondingly raised due to the decrease in ΦB at the
degeneration of output characteristics, and the similar device gate interface.[219] In the case of p-GaN HEMTs with Gr, the
performance inserting the two types of graphene revealed that IG was lower one order of magnitude than the baseline device
the bandgap and electroconductibility of graphene have little under a forward VG, as well the counterpart of reverse bias
impact on the electrical properties of p-GaN gate HEMTs. decreased more than 50 times. Meanwhile, the Schottky gate of
Figure 12b–f demonstrates the STEM and EDS results. There the devices were all broken down at about 12 V and maintained
are many voids (Figure 12d) and small TiN regions (Figure 12e) unchanged after 350 °C 5 min annealing except the HEMT
indicated by the yellow arrows on Ti/ GaN interface. By con- without Gr protection (9.80 V). It was proved that the higher ΦB
trast, inserting a monolayer Gr spaced the Ti from the under- and better interface quality, resulting from the insertion of Gr,
lying AlGaN to suppress the formation of TiN, and the interface all contribute to improving the device performance. The Bench-
voids were also avoided (Figure 12f). Thus, the interface quality mark of p-GaN gate HEMTs including the Vth and gate VBD are
was effectively improved with the application of Gr. summarized in Figure 12h.[101,221–227] In fact, these Gr-induced

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improvements can play significant roles in power switching depleted, creating a short depletion region. Figure 13a shows a
system based on p-GaN gate HEMTs. TCAD-simulated potential distribution of a normally-on HEMT
under off-state and Vd = 250 V. The electron concentration is
lower near the drain-side gate edge, suggesting the creation of
7. Electric Field Manipulation the depletion region. Most of the Vgd drop in the short deple-
tion region and result in a strong electric field. The electric field
For power switching applications, the GaN HEMTs generally peak at the drain-side gate edge may cause device breakdown.
operate in the first quadrant (positive bias and positive current) Thus, a field plate can extend the depletion region toward the
and third quadrant (negative bias and negative current).[228] drain and create another electric field peak at the edge of the
In the first quadrant operation, the device is expected to block field plate, reshaping the electric field distribution (Figure 13b).
high drain bias (e.g., 600 V for an adaptor for consumer elec- As a result, the VBD increases because the Vgd drops over a
tronics devices) during the off-state period and show low resist- larger region, and the electric field peak is also lower.
ance during the on-state period. Based on the experiences on The field plates can be connected to the gate electrode (gate
GaAs HEMTs, the high electric field at the drain-side gate edge FP, G-FP) or the source electrode (source FP, S-FP), sharing the
is the main cause of the off-state breakdown and current col- bias of the electrodes,[234,235] as shown in Figure 14a. Besides,
lapse.[229–231] Hence, researchers engineer the electric field multiple FPs with the same or different bias have been intro-
during the blocking period to manipulate electric fields, such as duced to GaN HEMTs and effectively increase the VBD.[236,237]
local fluoride plasma treatment[232] and local p-type doping.[233] Generally, each FP creates an additional electric field peak.
The field plates (FPs) are still the primary approaches. Therefore, the VBD increases with the extensive total depletion
For a conventional GaN HEMT, when the drain bias region by applying multiple FPs.[238] The electric field manipu-
increases, the 2DEG near the drain-side gate edge starts to be lation of FP depends on the layout of the whole device. Besides,

Figure 13. Potential contours and electron concentrations and electric field distribution over the conducting channel of a GaN HEMT a) without FP
and b) with a 1.3 µm G-FP under 250 V blocking condition. A larger depletion region and lower electric field peak are observed in the device with FP.

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Figure 14. a) Device structure of the p-GaN HEMT for testing. b) Off-state breakdown characteristics of devices with different FP configurations. c)
Dynamic Ron of devices with different FP configurations after off-state stress voltage. The optimized combination of S-FP and G-FP increase VBD and
decrease dynamic Ron at the same time. Reproduced with permission.[240,243] Copyright 2020, IEEE.

the thicknesses and dielectrics constants of each layer of passi- cooling procedures. After that, the doping buffer layer, AlGaN
vation layers also affect electric field distribution.[239] Therefore, back barrier and LSR technology were applied to enhance the
it is hard to give a universal rule for designing a field plate con- materials VBD and decrease the buffer leakage current. Digital
figuration. Optimizing FP configuration relies on engineering etching, strain engineering and selective area growth pro-
experiments or TCAD.[240] cesses were developed to fabricate normally-off HEMTs without
The electric field manipulation of FP also helps sup- plasm damages. GaN MIS-HEMTs was detaily discussed on
press the current collapse, or the increased dynamic Ron, the interface and fixed charge engineering with various dielec-
when the HEMTs are switched to on-state with a high voltage tric candidates, to modulate the Vth and gate control abilities.
blocking.[241–243] During the high voltage blocking, the strong Importantly, ultralow Ohmic contact resistance was achieved by
electric field accelerates the electrons towards the semicon- applying the TixAly or TaxAly alloy electrodes, revealing a novel
ductor surface. The electrons are trapped thereafter and create method to fabricate low Ron GaN HEMT devices. The metal/
an additional electric field, depleting the 2DEG during the Gr/GaN Schottky gate were intensively studied, as the gate VBD
conducting period. Together with the better passivation layer was enhanced by inserting a graphene singer layer between the
and GaN cap, FPs can decrease the electric field and avoid p-GaN and gate metal, keeping a relative high Vth and low gate
the electrons from acceleration. Generally, an optimized FP leakage current. Finally, various field plate shapes and distribu-
configuration for increasing VBD also works for suppressing tions were simulated and comparably studied with the fabri-
current collapse. Figure 14b,c shows a p-GaN HEMT with its cated device, which can effectively enhance the device VBD and
off-state breakdown characteristics and dynamic Ron after high suppress the current collapse.
voltage blocking. The optimized combination of G-FP and S-FP In addition to these lateral GaN power HEMT technolo-
can simultaneously increase VBD and suppress the current gies, the vertical GaN structures were also considered as the
collapse.[243,244] power device candidates. Because most of the vertical GaN
While manipulating the electric field, implementing FPs also power devices need back drain electrodes to build the vertical
introduces parasitic capacitance (e.g., CGD and CDS), which may current path, the high VBD and working current are naturally
compromise the high frequency and switching performance achieved by increasing the device thickness without enlarging
of the device.[245] Therefore, a few unique FP structures were the chip size.[249] The reliability and thermal management of
proposed, such as floating grating FPs[246] and air-bridge FP,[247] vertical GaN devices are also superior by moving the peak
to reduce the parasitic capacitance. A slant-shaped FP was also electric field away from the surface into bulk. The high-
applied to smoothen the electric field profile and increase the mobility GaN drift regions are usually grown on the high con-
device VBD.[248] ductivity substrates, such as freestanding n+-GaN[250–253] and
n+-Si.[254–256] The fully vertical drift regions can also directly
contact to the electrodes after the selective removal of the sub-
8. Outlook strates and buffer layers, followed by a wafer-bonding transfer
procedure.[257–259] For the cost and process-simplifying consid-
In this paper, conventional normally-on GaN-based HEMTs eration, several quasivertical GaN power diodes and transis-
and several approaches to achieve normally-off operation have tors on the foreign substrates were developed, which consist
been briefly introduced. Normally-off GaN HEMTs with p-(Al) of the vertical drift region and lateral spreading layers.[260–264]
GaN gate, recessed-gate and cascode configuration are the In particular, the current aperture vertical electron transistor
most widely used devices. After illustrating the device opera- (CAVET)[265–268] and trench CAVET[269–271] can operate the
tion principle, a series of recent progresses on the device per- device by controlling the 2DEG channel, similarly to the lat-
formance of GaN-based HEMTs were demonstrated, including eral GaN HEMTs. Recently, the advanced vertical and quasi-
the materials epitaxy and device fabrication technologies. From vertical GaN Schottky barrier diodes (SBDs),[253,272,273] junction
bottom to top, AlGaN step-graded and AlN/GaN SLs buffer barrier Schottky diodes,[274] fin MOSFETs,[275] trench MOS-
layers were successively deposited to increase the crystalline FETs,[276] superjunction diodes[277] and PN diodes[278–280] have
quality and compensate the wafer strain during the heating and successively raised the VBD from 600 to 4000 V with low Ron.

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Table 5. Advantages and shortages of advanced approaches described in previous sections.

Approaches Advantages Shortages

Digital etching - Accurately control etching depth - Complicated processes
- Improve surface morphology -Not suitable for mass production
Strain engineering - Low process damage - Limited positive Vth shift
- Superior on-state performance - Limited Vgm for large current application
Selective area growth - Etching-free recessed-gate structure - Optimization of regrowth parameter needed for great barrier and
- High Vth and low Ron interface quality
Fixed charge engineering - Well-controlled electrical properties for gate and access regions - Limited chosen for suitable band offset and bound charge density of
- Easy to monolithic integration dielectrics
Alloy electrodes - Ultralow Rc without recessed structure - Limited process windows
- Compatible with Si-CMOS process - High temperature needed for alloys annealing
Graphene insertion - High Vgm and Ion/Ioff - Stable graphene transformation needed for mass production
- Improve contact properties
Field plates - High device VBD - Limited frequency and switching performances by parasitic
- Excellent dynamic performance capacitance
Vertical structure - High VBD and large current level - High cost and complicated fabricating processes
-Superior device reliability and easy thermal management

The roadmap of high-performance vertical GaN power devices Keywords

is to realize the low-cost layer transfer and homoepitaxy tech-
field plates, gallium nitride, graphene insertion, high electron mobility
nologies, while the lateral GaN power HEMT applications
transistors, normally-off operation, Ohmic contacts
focus on the device reliability and the compatibility with the
matured Si-CMOS lines. Received: October 27, 2020
Though some of these advanced approaches have been Revised: December 25, 2020
proposed to improve the device performance of GaN HEMTs, Published online: January 29, 2021
there are still some limitations on the actual producing circum-
stances. The advantages and shortages of these methods are
summarized on Table 5, in terms of the fabrication process and
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Jiaqi He received an M.S. degree in optical engineering from the Southeast University, Nanjing,
China. He is currently a joint Ph.D. student at the Hong Kong Polytechnic University, Hong Kong,
and Southern University of Science and Technology, Shenzhen, China. His research interests
include the epitaxial growth of III-nitride materials and the fabrication of GaN-based high-electron
mobility transistors.

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Wei-Chih Cheng received a B.S. degree in physics from National Central University, Taoyuan,
Taiwan, and an M.Sc. degree in photonics from National Cheng Kung University, Tainan, Taiwan.
From 2015 to 2017, he worked for United Microelectronics Corporation as a process integration
engineer. He is currently pursuing a Ph.D. degree in the Department of Electronic and Computer
Engineering, the Hong Kong University of Science and Technology (HKUST), Hong Kong. He is
also in a joint Ph.D. program between HKUST and SUSTech (Southern University of Science and
Technology, Shenzhen, China), working on GaN-based HEMTs for power switch and RF power
amplifier applications.

Qing Wang is working as a research associate professor at School of Microelectronics, Southern

University of Science and Technology, China. She received her Ph.D. degree in materials science
and engineering from South China University of Technology in 2013. Later she worked at Sino
Nitride Semiconductor Co., Ltd for 6 years. Her major research is on GaN power devices and RF
devices for power adapter, smart grid, and 5G communication applications.

Hongyu Yu received his B.Sc., M.Sc., and Ph.D. from Tsinghua University, University of Toronto,
and National University of Singapore, respectively. He is currently the professor and dean of the
School of Microelectronics, Southern University of Science and Technology, Shenzhen, China. His
current research interests include integrated circuit technology and devices, CMOS, new ultra-
high density memory, GaN devices, and system integration (GaN HEMT).

Yang Chai is an associate professor at the Hong Kong Polytechnic University, a member of the
Hong Kong Young Academy of Sciences, and an IEEE distinguished lecturer in the Electron Device
Society. His research interest is emerging electron devices.

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