Unit - I Number Systems

SUMMER 2023
2 MARKS
a) State the base of following number system: Decimal, binary,
octal, hexadecimal
c) Give any two applications of comparator.
4 MARKS
a) Convert the given binary into decimal, octal, hexadecimal
and gray code: (10110101)2
c) Define PLA. Draw its block diagram.
b) Draw the block diagram of digital comparator IC 7485 and
explain with the help of truth table.
6 MARKS
a) Design nod-6 counter using IC 7490 and explain its design
with working.
c) i) State the rules of BCD addition. ii) Perform BCD addition
of : (972)10 + (348)10
WINTER 2023
2 MARKS
a) List the octal and hexadecimal numbers for decimal number
0 to 15.
b) Convert (159)10 = ( ? )8 Convert (380)10 = ( ? )16
4 MARKS
a) Perform the subtraction using 2’s complement methods. (10110)2
– (11010)2
a) Convert (53)10 = (BCD) (34)10 = (Excess-3) (100111)2 = (Gray)
(11010)2 = (2’s complement)
f) Draw and explain the block diagram of Programmable Logic Array
(PLA).
 6 MARKS

SUMMER 2022
2 MARKS
a) Convert (1101011)2 = ( (1111011)2 = ( )16 and )8
4 MARKS
a) Convert (43)10 = (BCD) (34)10 = (Excess-3) (110111)2 = (Gray)
(11101)2 = (2’s complement)
c) Draw the block diagram of programmable logic Array with proper
labels.
b) Design 4 bit binary to gray code converter. Using truth table.
6 MARKS
c) Subtract following using Two’s complement method. (15)10 –
(32)10
a) Design MOD-12 ripple counter. Write its truth table with
waveform.
WINTER 2019
2 MARKS
a) Convert (D8F)16 into binary and octal.
4 MARKS
a) Perform the subtraction using 2'S Complement methods. (52)10 –
(65)10
b) Draw binary to gray converter and write its truth table.
c) Draw block diagram of programmable logic Array.
 6 MARKS
a) (i) Convert the following binary number (11001101)2 into Gray
Code and Excess-3 Code. (ii) ( iii) Perform the BCD Addition. (17)10 +
(57)10 Perform the binary addition. (10110 • 110)2 + (1001 • 10)2

SUMMER 2019
2 MARKS
a) List the binary, octal and hexadecimal numbers for decimal
no. 0 to 15.
e) Write the gray code to given no. (⊥⊥0⊥)2 = (?) Gray.

4 MARKS
a) Convert: (i) (AD92 . BC A)16 = (?)10 = (?)8 = (?)2
a) Subtract the given number using 2’s complement method: (i)
(⊥⊥0⊥⊥)2 – (⊥⊥⊥00)2 (ii) (⊥0⊥0)2 – (⊥0⊥)2
6 MARKS

WINTER 2018
2 MARKS
a) Write the radix of binary, octal, decimal and hexadecimal
number system.
4 MARKS
a) Draw the block diagram of Programmable Logic Array.
b) Convert (i) (ii) (255)10 = ( ? )16 = ( ? )8 (157)10 = ( ? )BCD = (? )
Excess3
 6 MARKS

a) Subtract using 2’s compliment method Marks 12 (35)10 – (5)10

a) Design 4 bit Binary to Gray code converter.
 Unit - II Logic Gates and Boolean Algebra
SUMMER 2023
2 MARKS

4 MARKS
a) Draw the OR gate and NOR gate using NAND gate only.
b) Compare TTL, ECL and CMOS logic families. (any four points)
a) Define following terms : i) Fan-in ii) iii) iv) Fan-out Power
dissipation Noise margin

6 MARKS
c) Reduce following boolean expressions using boolean laws. i)
Y = AB + AB + AB + A B ii) iii) Y = ABC + ABC + ABC Y = ABC + ABC
+ ABC
WINTER 2023
2 MARKS
c) Draw symbol, truth table of NAND gate
4 MARKS
b) Explain the following characteristics with respect to logic families i)
ii) iii) iv) Power dissipation Fan-in and fan-out Noise margin Speed of
operation
b) State and explain De-Morgan’s theorems.
6 MARKS
a) Design basic logic gates using NAND and NOR gate.
SUMMER 2022
2 MARKS

4 MARKS
a) State and prove two De-Morgan’s Theorems.
b) Draw basic gates AND, OR and NOT using NAND gate only.
a) Realize given boolean expression using basic gates and simplify
same. y = AB + BC (B + C)

6 MARKS
c) Compare TTL and CMOS with following points. (i) Fan IN (ii) FAN
OUT (iii) Propogation delay (iv) Power dissipation
WINTER 2019
2 MARKS
b) Draw Symbol, Truth Table and logic equation of Ex-OR gate.
c) State the DeMorgan's Theorems.
4 MARKS
b) Simplify the following Boolean Expression and Implement using
logic gate. + + + ABC D ABCD ABCD ABCD
a) Realize the following logic expressions using only NAND gates. (i)
(ii) AND (iii) NOT
6 MARKS
a) Compare TTL, CMOS and ECL logic family on the following points.
(i) (ii) Basic Gates Propogation delay (iii) Fan out (iv) Power
Dissipation (v) Noise immunity (vi) Speed Power Product.

SUMMER 2019
2 MARKS
 b) Define fan-in and fan-out of a gate.
g) Draw the logical symbol of EX-OR and EX-NOR gate.
4 MARKS
b) Simplify the following and realize it Y = A + A BC + A B C + ABC + A
B
c) Explain the flowing characteristics w.r.t logic families: (i) Noise
margin (ii) Power dissipation (iii) Figure of merit (iv) Speed of
operation
b) State De-Morgan’s theorem and prove any one.

6 MARKS
c) Design basic logic gates using NAND and NOR gate.
WINTER 2018
2 MARKS
b) Draw the circuit diagram for AND and OR gates using diodes.
4 MARKS
c) Draw the symbol, truth table and logic expression of any one
universal logic gate. Write reason why it is called universal gate.
a) Compare TTL and CMOS logic families on the basis of following: (i)
(ii) Propagation delay Power Dissipation (iii) Fan-out (iv) Basic gate
c) Realize the basic logic gates, NOT, OR and AND gates using NOR
gates only.
d) State De Morgan’s theorem and prove any one.
6 MARKS
 Unit - III Combinational Logic Circuits
SUMMER 2023
2 MARKS
f) Define and draw logic symbol of demultiplexer
4 MARKS
b) Draw the block diagram of BCD to 7 segment decoder using
IC 7447. Write truth table of it
d) Implement full adder using two half adder.
d) A combinational circuit is defined as F1 = ∑m (3, 5, 7) and F2
= ∑m (4, 5, 7). Implement the circuit with a PLA having 3 inputs,
3 product terms and 2 outputs.
c) Design 32 : 1 multiplexer using 8 : 1 multiplexer.
6 MARKS
b) i) Minimize the following expression using K-map. Y = ∑m (0,
2, 5, 7, 8, 10, 13, 15) ii) Realize the minimized expression using
basic gates.

WINTER 2023
2 MARKS
d) Define min-term and max-term with respect to K-map
4 MARKS
c) Draw logic diagram of half adder using K-map simplification and
write truth table.
c) Draw 16 : 1 mux tree using 4 : 1 mux.
6 MARKS
a) Design 1 : 8 demultiplexer using 1 : 4 demultiplexer. Also write
truth table.
b) Minimize the following expression using K-map. f (A, B, C, D) = ∑ m
(0, 1, 2, 4, 5, 7, 8, 9, 10) Also explain SOP and POS form.
SUMMER 2022
2 MARKS
c) Define Minterm and Maxterm w.r.t. K-map.
f) Draw logical circuit diagram of half adder circuit.
4 MARKS
b) Draw logical diagram of full adder using K-map simplification and
write truth table.
d) Draw the circuit diagram of BCD to 7 - segment decoder and write
truth table.
c) Realize given expression using K-map f (A, B, C, D = Σ m (3, 5, 7, 8,
10, 11, 12, 13)
6 MARKS
b) Design 16:1 MUX using 4:1 MUX.

WINTER 2019
2 MARKS
d) Convert the following expression into standard SOP form. Y =
AB + A C + BC
4 MARKS
c) Minimize the four variable logic function using K map. f(A,B,C,D) =
∑m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)
d) Implement the following functions using demultiplexer. f1 = ∑m (0,
2, 4, 6) f2 = ∑m (1, 3, 5)
a) Design a full Adder using Truth Table and K-map.

6 MARKS
b) Design a BCD adder using IC 7483.

SUMMER 2019
2 MARKS
f) Define encoder, write the IC number of IC used as decimal to
BCD encoder.
4 MARKS
d) Draw logic diagram of half adder circuit.
d) Reduce the following expression using K-map and implement it F
(A, B, C, D) = p M (1,3,5,7,8,10,14)

6 MARKS
a) Design BCD to seven segment decoder using IC 7447 with its truth
table.
b) Design ⊥:8 demultiplexer using 1:4 demultiplexer.
WINTER 2018
2 MARKS
 c) Write simple examples of boolean expression for SOP and
POS.
d) State the necessity of multiplexer.
4 MARKS
d) Minimize the following expression using K-Map. f (A, B, C, D) = Σm
(0, 1, 2, 4, 5, 7, 8, 9, 10)
b) Describe the function of Full Adder Circuit using its truth table, K-
Map simplification and logic diagram.
b) Draw 16:1 MUX tree using 4:1 MUX.
e) Design one digit BCD Adder using IC 7483.
6 MARKS
 Unit - IV Sequential Logic Circuits
SUMMER 2023
2 MARKS
b) Define counter.
d) Draw the symbol of D flipflop and write its truth table.
g) List the basic types of shift register.

4 MARKS
c) Draw 4 bit twisted ring counter and explain working with
truth table and waveforms.
d) Explain the working of master salve JK flipflop with truth
table and logic diagram.
6 MARKS
a) Design synchronous decade counter using D’ flipflop.
WINTER 2023
2 MARKS

4 MARKS
d) Describe the working of J-K flip-flop and state the race around
condition.
d) Describe the operation of R-S flip-flop using NAND gate.
e) Describe the operation of 4 bit serial in serial out shift register.

6 MARKS
b) Explain the role of counters in digital circuits and design Mod - >
counter using IC 7490.
c) Draw and explain 4-bit universal shift register. Also explain the
necessity of register in digital circuits.
SUMMER 2022
2 MARKS
b) List triggering methods used for triggering flip flops.
d) Define shift register and list its types.
g) Write truth table of D type flip-flop.

4 MARKS
c) Draw 4 bit ring counter with truth table and its waveform.
d) Draw JK master slave flip flop and explain its operations.
6 MARKS
a) Draw and explain operation 4 bit universal shift register. Draw
necessary waveforms.

WINTER 2019
2 MARKS
e) Draw symbol and write truth table of D and T Flip Flop.
f) Write down number of flip flops are required to count 16
clock pulses.

4 MARKS
c) Describe the working of JK flip flop with truth table and logic
diagram.
d) Describe the working of 4 bit SISO (serial in serial out) Shift
Register with diagram and waveform if input is 01101
b) Describe the working of ring counter using D flip flop with diagram
and waveforms.
 6 MARKS
b) Design a 4bit ripple counter using JK flip flop, with truth table and
waveforms.
c) Design a 3 bit synchronous counter using JK FlipFlop.

SUMMER 2019
2 MARKS
c) Compare between synchronous and asynchronous counter
(any two points).
4 MARKS
b) Describe the operation of R-5 flip-flop using NAND gates only.
d) State the applications of shift register.
6 MARKS
b) Describe the working of 4 bit universal shift register
a) Design a mod-6 Asynchronous counter with truth-table and logic.
WINTER 2018
2 MARKS
e) Draw logic diagram of T flip-flop and give its truth table.
f) Define modulus of a counter. Write the numbers of flip flops
required for Mod-6 counter.
g) State function of preset and clear in flip flop.
4 MARKS
d) Describe the working of JK flip-flop with its truth table and logic
diagram.
a) Draw and explain working of 4 bit serial Input parallel Output shift
register.
6 MARKS
b) Design a 4 bit synchronous counter and draw its logic diagram.

c) Give block schematic of decade counter IC 7490. Design Mod-7

counter using this IC.

Unit - V Data Converters and Memories

SUMMER 2023
2 MARKS
e) Name the types of RAM
4 MARKS
e) Write applications of ADC and DAC.
6 MARKS
b) Explain classification of memories. What is flash memory?
WINTER 2023
2 MARKS
e) List the types of DAC
f) State two features of ADC IC0809
g) List the types of semiconductor memories.
4 MARKS
e) Give classification of memory and compare RAM and ROM. (Any
four points)
6 MARKS
c) Draw and explain the block diagram of dual slope ADC. Also write
it’s specifications.
SUMMER 2022
2 MARKS
e) List any two specifications of IC-DAC 0808.

4 MARKS
d) Compare the following: (Any two points each) (i) Volatile - Non
volatile memory (ii) SRAM - DRAM memory
e) Calculate analog o/p of 4 bit DAC for digital input is 1100. Assume
VFS = 5 V
6 MARKS
b) Draw block diagram of Dual slope ADC and explain its working.

WINTER 2019
2 MARKS
g) List the types of DAC
4 MARKS
d) Compare the following: (i) Volatile with Non Volatile. (ii) EPROM
with EEPROM.
e) Describe the working principle of successive approximation ADC.
6 MARKS
c) Calculate the analog output for 4 bit weighted register type DAC
for inputs (i) (ii) 1011 1001 Assume (Vfs) full scale range of voltage is
5V

SUMMER 2019
2 MARKS
d) State two specification of DAC
4 MARKS
a) Draw the circuit of successive approximation type ADC and explain
it’s working.
c) Give classification of memory and compare RAM and ROM (any
four points).
c) Compare between PLA and PAL.
6 MARKS
c) Draw the circuit diagram of 4 bit R-2R ladder DAC and obtain its
output voltage expression.
WINTER 2018
2 MARKS

4 MARKS
c) Calculate analog output of 4 bit DAC for digital input 1101. Assume
VFS = 5V.
6 MARKS

c) Describe the working of successive Approximation ADC. Define

Resolution and conversion time associated with ADC.
b) Compare the following (Any three points) (i) Volatile with Non-
volatile memory (ii) SRAM with DRAM memory