EExamination Paper Analysis

Topic MAY-2023 DEC-2022 MAY. 2022

Topic
No. Marks
Question Marks Question Marks Question

1 (a) 02 1 (a) 02 1 (a) 02

Number 2 (a) 04 1 (e) 02 2 (a) 04
1 5 (c) 06 5 (c) 06 5 (c) 06
system
Total 12 Total 10 Total 12
3 (a) 04 2 (a) 04 3 (a) 04
3 (b) 04 3 (a) 04 3 (b) 04
Logic Gates
2 and logic 4 (a) 04 4 (a) 04 4 (a) 04
families 6 (c) 06 6 (c) 06 6 (c) 06
Total 18 Total 18 Total 18

1 (b) 02 1 (c) 02
1 (c) 02
1 (g) 02 1 (f) 02
1 (f) 02
2 (b) 04 2 (b) 04
2 (b) 04
2 (d) 04 2 (d) 04
2 (d) 04
Combinational 4 (b) 04 4 (b) 04
3 4 (b) 04
Logic Circuits 4 (c) 04 4 (c) 04
4 (c) 04
6 (b) 06 6 (b) 06
6 (b) 06

Total 28 Total 26 Total

26
1 (b) 02 1 (c) 02 1 (b) 02
1 (d) 02 1 (d) 02 1 (d) 02
1 (g) 02 3 (b) 04 1 (g) 02
Sequential 3 (c) 04 3 (d) 04 3 (c) 04
4 4 (d) 04 4 (d) 04 4 (d) 04
Logic circuit
5 (a) 06 5 (a) 06 5 (a) 06
6 (a) 06 6 (a) 06 6 (a) 06
Total 26 Total 28 Total 26
1 (e) 02 1 (f) 02 1 (e) 02
2 (c) 04 2 (c) 04 2 (c) 04
Data 4 (e) 04 3 (c) 04 3 (d) 04
5 converters 5 (b) 06 4 (e) 04 4 (e) 04
and PLD
5 (b) 06 5 (b) 06
Total 16 Total 20 Total 20



 37 
Exam Unit Question no. as per MSBTE Marks
Year No
and
Name
Summer Unit 1a. State the base of the following number system 02
2023 1 Decimal, Binary, Octal, Hexadecimal
Ans
Decimal has base : 10
Binary has base: 2
Octal has base : 8
Hexadecimal has base : 16

2a. Convert the given binary into decimal, octal, 04

hexadecimal and gray code.
(10110101)2

i) (10110101)2 = (?)10
=1*27+0*26+1*25+1*24+0*23+1*22+0*21+1*20
= 128 + 0 + 32 + 16 + 0 + 4 + 0 + 1
= (181)10
ii) (10110101)2 = (?)8
Step 1: Write down the binary number
(10110101)2
Group all the digits in sets of three starting from the LSB (far
right). Add zeros to the left of the last digit if there aren't
enough digits to make a set of three.
010 110 101
Step 2: Convert each set of three into an octal digit. In this
case,
010=2, 110=6, 101=5.
So, the number 265 is the octal equivalent to 10110101 in
binary.
1 1 0 1 0 1 = (265)8
iii) (10110101)2 = (?)16
Step 1: Write down the binary number: (10110101)2
Step 2: Group all the digits in sets of four starting from the
LSB (far right). Add zeros to the left of the last digit if there
aren't enough digits to make a set of four:
1011 0101
Step 3: Write decimal equivalent of each group
1011 = (B )16
0101=(5)16
Vidyalankar : B.E.  Microwave

1 0 1 1 0 1 0 1 = (B5) 16

iv) (10110101)2 = (?)gray

(1 1 1 0 1 1 1 1)gray

5c. i) State the rules of BCD addition

Rules of BCD Addition:
1. If sum is less than or equal to 9 with carry equal to 0, then 06
the sum is in proper BCD
form and requires no correction.
2. If sum is greater than 9 but carry equal to 0, then it’s an
invalid BCD. Then we have
to add decimal 6 or BCD 0110 to get the correct BCD.
3. If sum is less than or equal to 9 but carry equal to 1, then
too it’s an invalid BCD. Then we have to add decimal 6 or
BCD 0110 to the sum to get the correct BCD

ii) Perform BCD addition of

(972)10 + (348)10

Winter Unit 1a. Write radix of binary, octal, hexadecimal number 02

2022 1 system.
Ans:
Number System Radix
Binary 2
Octal 8
Hexadecimal 16

39
 1e. Write gray code to given number. 02
(11111)2 = (?)Gray
Ans:
(11111)2 = (10000)

5c. Convert the following.

i) (6AC)16 = (?)10 06
6∙162+10∙161+12∙160
= 6∙256+10∙16+12∙1
= 1536+160+12
= (1708)10

ii) (2003)10 = (?)16

Operation Quotient Remainder
2003/16 125 3
125/16 7 13
7/16 0 7
2003)10 = (7C3)16

iii) (228)10 = (?)BCD

= 0010 0010 1000
Summer Unit 1a. Convert (1101011)2 = ( ) 16 and 02
2022 1 (1111011)2 = ( ) 8
Ans:
Step 1: Write down the binary number:
1101011
Step 2: Group all the digits in sets of four starting from the
LSB (far right). Add zeros to the left of the last digit if there
aren't enough digits to make a set of four:
0110 1011
Step 3: Write decimal equivalent of each group
0110 = 6, 1011 = B
Ans: (1101011)2 =(6B)16

ii) (1111011)2 = ( ) 8
Step 1: Write down the binary number
(1111011)2
Group all the digits in sets of three starting from the LSB (far
right). Add zeros to the left of the last digit if there aren't
enough digits to make a set of three.
001 111 011
Step 2: Convert each set of three into an octal digit. In this
case,
001=1, 111=7, 011=3.
Vidyalankar : B.E.  Microwave
So, the number 1111011 in binary is equivalent to 173 in
octal.
Ans: (1111011)2 =(173)8

2a. Convert 04
(43)10 = (BCD)
(34)10 = (Excess-3)
(110111)2 = (Gray)
(11101)2 = (2’s complement)

Ans: i) (43)10 =(0100 0011 ) (BCD)

ii) (34)10 = (Excess-3)

Ans: (34)10 =0110 0111 (Excess-3)

iii) (110111)2 = (Gray)

Gray Code :10110

i) (11101)2 = (2’s complement)
1’s complement of given number = 00010
2’s complement = add 1 to 1’s complement
= 00010 +1 = 00011
Ans: 00011
5c. Subtract following using Two’s complement method.
(15)10 – (32)10 06
Ans:

41
Summer Unit 3a. Draw OR gate and NOR gate using NAND only. 04
2023 2 Ans: NAND and NOR gates are universal gates. All basic
gates can be designed by using these gates.

1. OR gate using NAND gate:

2. NOR gate using NAND gate :

Vidyalankar : B.E.  Microwave

04
3b. Compare TTL, CMOS, ECL Logic families (any 4
points)

Ans:
Parameters TTL CMOS ECL

Basic gate NAND NOR or OR/NOR

NAND
Fan Out 10 50 25
Propagatio 10ns 70-105ns 2ns
n Delay
Power 10 mW 1.01 mW 40-55 mW
dissipation 04

4a. Define the following terms:

i. Fan-in
The Fan-in of a logic gate is the number of inputs
that a gate can handle.
Eg.: 2 input gate will have a fan-in =2

ii. Fan-out:
Fan-out is defined as the number of gates that the
output of a gate can drive without disturbing
normal operation.
Eg: Fan-out 4 means that the gate can drive 4
inputs of the same IC family.

iii. Power dissipation:

The power dissipated by a logic circuit is defined
as the power required for the logic gate to operate
with 50% duty cycle at the specified frequency.

iv. Noise margin:

Noise margin is a quantitative measure of noise
immunity. It is defined as the difference between
operating input voltage level and the input
voltage level at which the circuit changes from
one state to another.
06

43
 6c. Reduce the following Boolean expression using
Boolean laws.
i) Y= AB +A B +AB +A B

Ans:

ii) Y = A B C+ A B C + ABC
Ans:

iii) Y = A B C+A B C + A B C
Ans:

Winter Unit 2a. Sketch the given Boolean expression; use one AND 04
2022 2 gate one OR gate only Y = AB + AC.
Ans:
Vidyalankar : B.E.  Microwave

3a. Realize the following logic operation using only NOR 04

gates: AND, OR, NOT.

Ans:
1. AND gate using NOR gate

2. OR gate using NOR gate

3. NOT gate using NOR gate

4a. Draw symbol, truth table and logical output equation

of OR and EX-OR gate.
Ans: 04
1. OR gate

a. Symbol

45
 b. Truth table of OR gate

Logical expression: Y=A+B

6c. Draw the circuit and explain the principle of TTL gate
with totem pole output. 06
Ans:
Vidyalankar : B.E.  Microwave

Summer Unit 3a. State and prove two De-Morgan’s Theorems. 04

2022 2 Ans:
De Morgan´s 1st Theorem: It states that the compliment of
sum is equal to the product of the compliment of individual
variables.

47
Statement: Compliment of product is equal to sum of the
compliments

3b. Draw basic gates AND, OR and NOT using NAND 04

gate only.
Ans:

NOT gate using NAND

04
Vidyalankar : B.E.  Microwave
4a. Realize given Boolean expression using basic gates and
simplify same.
y = AB + BC (B+C)

Ans:

6c. Compare TTL and CMOS with the following points. 06

(i) Fan IN (ii) FAN OUT (iii) Propagation delay (iv)
Power dissipation
Ans:
i. Fan-in
The Fan-in of a logic gate is the number of inputs
that a gate can handle.
Eg.: 2 input gate will have a fan-in =2
ii. Fan-out:
Fan-out is defined as the number of gates that the
output of a gate can drive without disturbing
normal operation.
Eg: Fan-out 4 means that the gate can drive 4
inputs of the same IC family.
iii. Power dissipation:
The power dissipated by a logic circuit is defined
as the power required for the logic gate to operate
with 50% duty cycle at the specified frequency.
iv. Propagation delay:
The delay between the instant of application of an
input signal and occurrence of the corresponding
output signal is known as Propagation delay.
Summer Unit 1c. Give any two applications of comparator. 02
2023 3 Ans:
1. Comparators are used in first central processing unit and

49
micro controllers.
2. Ti is used in ADC to major digitize analog signals.

1f. Define and draw logic symbol of demultiplexer. 02

Ans:
Demultiplexer is combinational logic circuit and it does
exactly the opposite to that of a Multiplexer.
OR
Demux is a one-to-many circuit.
OR
A Demultiplexer is a combinational logic circuit that
receives the information on a single input line and transmits
the same information over one of ‘n’ possible output lines.

2b. Draw the block diagram of BCD to 7-segment decoder

04
using IC 7447. Write truth table of it.
Ans:
Vidyalankar : B.E.  Microwave

2d. Implement Full adder using two half adder. 04

Ans:

4b. Draw the block diagram of digital comparator 7485

and explain with the help of truth table. 04
Ans:

51
4c. Design 32:1 multiplexer using 8:1 multiplexer.
Ans: 04
Vidyalankar : B.E.  Microwave

6b. i) Minimize the following expression using K-map

Y=∑m (0,2,5,7,8,10,13,15) 06
Ans:

ii) Realize the minimized expression using basic gates.

Ans:

Winter Unit 1b. State necessity of demultiplexer 02

2022 3 Ans:
1.De-multiplexers are used in applications where there is a
necessity of connecting single source to several
destinations.
2. Used in memory decoding.
3. Data Routing

53
4. Serial to Parallel converter
5. Communication in TDM, FDM.

1g. Draw four variable K-map. 02

Ans:

2b. Draw circuit diagram of BCD to seven segment

decoder and write its truth table 04
Ans:
Vidyalankar : B.E.  Microwave
2d. Minimize the following expression using K-map. f(A, 04
B,C,D) = Σm (1,5,6,7,11,12,13,15)
Ans:

4b. Describe function of full adder circuit with its truth

table and logical diagram. 04
Ans:

55
Vidyalankar : B.E.  Microwave

4c. Design 16:1 multiplexer using 4:1 multiplexer.

Ans: 04

57
6b. Design a four bit BCD adder using IC-7483 and
NAND gate only 06
Ans:
Vidyalankar : B.E.  Microwave

Summer Unit 1c. Define Minterm and Maxterm w.r.t. K-map. 02

2022 3 Ans:
Each individual term in standard SOP form is called as
Minterm.
Each individual term in standard POS form is called as
Minterm.

1f. Draw logical circuit diagram of half adder circuit. 02

Ans:

2b. Draw logical diagram of full adder using K-map 04

simplification and write truth table.
Ans:

59
Vidyalankar : B.E.  Microwave

2d. Draw the circuit diagram of BCD to 7 - segment 04

decoder and write truth table.

Ans:

61
4b. Design 4 bit binary to gray code converter. Using
truth table.
04

04

06
Vidyalankar : B.E.  Microwave

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Vidyalankar : B.E.  Microwave

65
4c. Realize given expression using K-map f(A, B, C, D =
Σ m(3, 5, 7, 8, 10, 11, 12, 13)

6b. Design 16:1 MUX using 4:1 MUX.

Vidyalankar : B.E.  Microwave

Summer Unit 1b. Define Counter. 02

2023 4 Ans:
Counter is a sequential circuit consisting of a set of flip-flops
which can go through sequence of states. It is used to count
the number of clock cycles. Since the clock pulses occur at
known intervals, the counter can be used for measuring time
such as period or frequency

1d. Draw the symbol of D flip-flop and write its truth 02

table.
Ans:
Symbol:

67
Truth table of D Flip-Flop:

INPUT OUTPUT
Clock
D Q Q’

LOW x 0 1
02

HIGH 0 0 1

HIGH 1 1 0

1g. List the basic types of truth table.

Ans:
Basic shift registers are classified as:
1. Left shift Register,
2. Right shift register,
3. Universal shift register 04
4. Bidirectional shift register

OR
1. Serial-in/serial-out.
2. Parallel-in/serial-out.
3. Serial-in/parallel-out.
4. Parallel-in/parallel-out

3c. Draw 4-bit twisted ring counter and explain its

working with truth table and waveform
Ans:
Vidyalankar : B.E.  Microwave
The Twisted Ring Counter refers to as a switch-tail ring
Counter. The complimented output of last flip flop is
connected to the input of first flip-flop

A 4-bit Johnson ring counter passes blocks of four logic “0”

and then four logic “1” thereby producing an 8-bit pattern. As
the inverted output Q is connected to the input D this 8-bit
pattern continually repeats. For example, “1000”, “1100”,
“1110”, “1111”, “0111”, “0011”, “0001”, “0000” .

69
4d. Explain the working of master slave JK flipflop with 04
truth table and logic diagram.
Ans:
The Master-Slave JK Flip Flop

The input signals J and K are connected to the gated

“master” SR flip flop which “locks” the input condition while
the clock (Clk) input is “HIGH” at logic level “1”. As the
clock input of the “slave” flip flop is the inverse
(complement) of the “master” clock input, the “slave” SR flip
flop does not toggle. The outputs from the “master” flip flop
are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip
flop are latched and any additional changes to its inputs are
ignored. The gated “slave” flip flop now responds to the state
of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the
inputs of the “master” flip flop are fed through to the gated
inputs of the “slave” flip flop and on the “High-to-Low”
transition the same inputs are reflected on the output of the
“slave” making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is
“HIGH” and passes the data to the output on the falling-edge
of the clock signal. In other words, the Master-Slave JK Flip
Vidyalankar : B.E.  Microwave
flop is a “Synchronous” device as it only passes data with the
timing of the clock signal.
The input signals J and K are connected to the gated “master”
SR flip flop which “locks” the input condition while the clock
(Clk) input is “HIGH” at logic level “1”. As the clock input
of the “slave” flip flop is the inverse (complement) of the
“master” clock input, the “slave” SR flip flop does not toggle.
The outputs from the “master” flip flop are only “seen” by
the gated “slave” flip flop when the clock input goes “LOW”
to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip
flop are latched and any additional changes to its inputs are
ignored. The gated “slave” flip flop now responds to the state
of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the
inputs of the “master” flip flop are fed through to the gated
inputs of the “slave” flip flop and on the “High-to-Low”
transition the same inputs are reflected on the output of the
“slave” making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is
“HIGH”, and passes the data to the output on the falling-edge
of the clock signal. In other words, the Master-Slave JK Flip
flop is a “Synchronous” device as it only passes data with the
timing of the clock signal.

06
5a. Design Mod-6 counter using IC 7490 and explain its
design with working.
Ans:
Clock is given to clock input A. Output QA is connected to
clock input B. To reset the counter after counting the first six
states from 0 to 5, the counter outputs Qc and QB should be
connected to the reset inputs.

71
6a. Design synchronous decade counter using D flipflop
Ans:
Step 1: Find the number of Flip-flops needed
The number of Flip-flops required can be determined by
using the following equation:

M ≤ 2N

where, M is the MOD number and N is the number of 06

required flip-flops.
Here, MOD number is equal to 10. i.e., M = 10
Therefore, 10 ≤ 2N
=> N = 4

Therefore, to design a MOD 10 or Decade Counter, 4 flip-

flops will be required.
Step 2: Write the excitation table of the flip-flop
Vidyalankar : B.E.  Microwave
Excitation table of D flip-flop is:
QN QN+1 D
0 0 0
0 1 1
1 0 0
1 1 1

Step 3: Write the circuit state table by using excitation

table
Circuit state table for designing MOD 10 Synchronous
Counter using D Flip-flop will be

Step 4: Prepare K Map for each flip-flop input in terms of

flip-flop outputs as the input variables
In this case inputs of the flip-flops are: DA, DB, DC & DD

K Map for DA :

Therefore,

Q A QB QC QD QA+ QB+ QC+ QD+ DA DB DC D

1 1 1 1 D

0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1 0 0 1 1
0 0 1 1 0 1 0 0 0 1 0 0
0 1 0 0 0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0 0 1 1 0
0 1 1 0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 0 1 0 0 0
73
1 0 0 0 1 0 0 1 1 0 0 1
Winter Unit 1c. Draw symbol and write the truth table for T-flipflop. 02
2022 4 Ans:
Symbol:

1d. Compare between synchronous and asynchronous

counter.
Ans: 02

3b. Describe the operation of 4 bit serial in serial out shift 04

register.
Ans:
Diagram:(use SR or JK or D type flip flop)

Working:
The DATA leaves the shift register one bit at a time in a
serial pattern, hence the name Serial-in to Serial-Out Shift
Register or SISO.
The SISO shift register is one of the simplest of the four
configurations as it has only three connections, the serial
input (SI) which determines what enters the left hand flip-
flop, the serial output (SO) which is taken from the output of
the right hand flip-flop and the sequencing clock signal (Clk).
The logic circuit diagram below shows a generalized serial in
serial-out shift register, Output of FFA is Q4,FFB Q3,FFC
Q2 and FFD is Q1
Vidyalankar : B.E.  Microwave
Waveform:(Input is 01101)

3d. Describe the working of SR flipflop with its truth

table and logic diagram.
Ans: 04

75
 04

06

4d. Describe the working of Master-slave JK flipflop with

truth table and logic diagram.

5a. Explain 3-bit asynchronous counter with output

waveforms.
Ans:
In asynchronous counter, a clock pulse drives FF0. Output of
FF0 drives FF1 which then drives the FF2 flip flop. All J and
K inputs are connected to Logic 1. Therefore, each flip flop
Vidyalankar : B.E.  Microwave
will toggle with negative transition at its clock input.

The 3 bit MOD-8 asynchronous counter consists of 3 JK

flip/flops. Overall propagation delay time is the sum of
individual delays. Initially all flip flops are reset to produce 0.
The output conditions is Q2Q1Q0 = 000.
When the first clock pulse is applied, the FF0 changes state
on its negative edge. Therefore, Q2Q1Q0 = 001. On the
negative egde of second clock pulse flip flop FF0 toggles. Its
output changes from 1 to 0. This being negative change, FF1
changes state. Therefore, Q2Q1Q0 = 010. Similarly, the
output of flipflop FF2 changes only when there is negative
transition at its input when fourth clock pulse is applied.

The output of the flip flops is a binary number equivalent to

the number of clock pulses received. The output conditions
are as shown in the truth table.

06

6a. Give the block schematic of decade counter IC 7490.

Design mod-7 counter using IC.

77
Ans:
Block schematic of decade counter IC 7490

Mod-7 means states are from o,1,2,3,4,5,6,0

Therefore we have to reset counter IC 7490 when
QD,QC,QB,QA=0111
Design reset logic:
Output of reset circuit should be HIGH because R0(1) and
R0(2) are active high inputs.
Therefore reset logic output should be low for states 0 to 6.
Output should be HIGH for states 7 onwards.
Truth table & K-map:

Expression for Y:
Y= QC QB QA + QD
Vidyalankar : B.E.  Microwave
Circuit is-

Summer Unit 1b. List triggering methods used for triggering flip flops. 02
2022 4 Ans:
: Triggering methods used for triggering flip flops:
 Negative edge triggering.
 Positive edge triggering.
 Positive level triggering.
 Negative level triggering.

1d. Define shift register and list its types. 02

Shift Register is a group of flip flops used to store multiple
bits of data. The bits stored in such registers can be made to
move within the registers and in/out of the registers by
applying clock pulses.
shift registers are classified as:
1. Serial-in/serial-out.
2. Parallel-in/serial-out.
3. Serial-in/parallel-out.
4. Parallel-in/parallel-out.
OR
1. Left shift Register,
2. Right shift register,
3. Universal shift register
4. Bidirectional shift register

1g. Write truth table of D type flip-flop.

Ans: 02

79
 04

04

06

Truth table of D Flip-Flop:

3c. Draw a 4-bit ring counter with truth table and its
waveform.
Vidyalankar : B.E.  Microwave
06

Working: The ring counter is a cascaded connection of

flip flops, in which the output of last flip flop is
connected to input of first flip flop. In ring counter if the
output of any stage is 1, then its reminder is 0. The Ring
counters transfers the same output throughout the
circuit. That means if the output of the first flip flop is 1,
then this is transferred to its next stage i.e. 2nd flip flop.
By transferring the output to its next stage, the output of
first flip flop becomes 0. And this process continues for
all the stages of a ring counter. If we use n flip flops in
the ring counter, the „1‟ is circulated for every n clock
cycles.

81
4d. Draw JK master slave flip flop and explain its
operations.
Please refer S-23 Q 4(d)
5a. Draw and explain operation 4-bit universal shift
register. Draw necessary waveforms.
Ans:
4-bit universal shift register

Working:
1. PARALLEL LOAD: When mode control (M) is
connected to logic 1, AND gates 2, 4, 6, 8 will be enables and
AND gates 1, 3,5,7, will be disabled . The 4-bit binary data
will be loaded
parallel. The clock-2 input will be applied to the flip-flops ,
since M= 1, AND gates -10 is enabled and gate-9 is disabled.
Input will transfer parallel data to QA to QD outputs.
2. SHIFT RIGHT: When mode control (M) is connected to
logic 0, AND gates 1,3,5,7 will be enabled and gates 2, 4,,6,
8,will be disabled. The data will be shifted serially. The clock
-1, input will be applied to the flip-flops, Since M = 0, AND
gates - 9 is enabled, and gates -10 is disabled. The data is
shifted serially to right from QA to QD.
3. SHIFT LEFT: When mode control (M) is connected to
logic 1, AND gates 2,4,6,8 will be enabled. This mode
permits parallel loading of the resister and shift -left
operation. The shift -left operation can be accomplished by
connecting the output of each flip flop to the parallel input of
the previous flip- flop and serial input is applied at the input.

6a. Design MOD-12 ripple counter. Write its truth table

with waveform.
Ans:
Vidyalankar : B.E.  Microwave

Summer Unit 1e. Name the types of RAM. 02

2023 5 Ans:
There are two main types of RAM:
1. Dynamic RAM (DRAM)
2. Static RAM (SRAM)

2c. Define PLA and draw its block diagram. 04

Ans:
Programmable Logic Array PLA: PLA is a programmable
logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD.
The block diagram of PLA is shown in the following figure

83
Here, the inputs of AND gates are programmable. That
means each AND gate has both normal and complemented
inputs of variables. So, based on the requirement, we can
program any of those inputs. So, we can generate only the
required product terms by using these AND gates. Here, the
inputs of OR gates are also programmable. So, we can
program any number of required product terms, since all the
outputs of AND gates are applied as inputs to each OR gate. 04
Therefore, the outputs of PLA will be in the form of sum of
products form.

4e. Write applications od ADC and DAC

Ans:
Applications of ADC converter
● They are used in Audio/Video devices.
● They are used in Cell Phones.
● They are used in Digital Multimeters, PLC’s
(Programming Logic Controllers).
● They are used in RADAR processing, digital
oscilloscopes
. ● They are widely used in CMOS Image sensors for
mobile applications.
● They are used in Medical Instrumentation and medical
imaging
Applications of DAC converter
● To convert digital command signal into analog
example motor speed control 06
● As counter ADC or successive approximation type
ADC

5b. Explain the classification of memories. What is flash

memory.
Ans:
Vidyalankar : B.E.  Microwave

Winter Unit 1f. State two features of ADC IC0809. 02

2023 5 Ans:

2c. Draw the block diagram of programmable array logic.

Ans: 04

3c. Calculate the analog output of 4 bit DAC if the digital 04

input is 1101. Assume VFS = 5V
Ans:

85
 04

4e. Compare between R-2R ladder DAC and weighted

resistor DAC (Four points).
Ans:

06

5b. Compare following (Any three points)

i) RAM with ROM memory.
ii) EPROM with EEPROM memory

Ans:
Vidyalankar : B.E.  Microwave

Summer Unit 1e. List any two specifications of IC-DAC 0808. 02

2022 5 Ans:
1. It has a parallel digital input that takes 8-bit data and

87
 gives output with relative accuracy at the highest
error of ±0.19%.
2. The power supply used should be in a range of ±4.5V
to ±18V.
3. The settling time is 150 ns which is very fast.
4. DAC0808 provides features of low power
consumption. The maximum power it can dissipate is
1000mW. For a supply voltage of ±5V, it utilizes
only 33 mW power.
5. The inputs are CMOS and TTL compatible.

2c. Draw the block diagram of programmable logic Array 04

with proper labels.
Ans:

3d. Compare the following: (Any two points each) 04

(i) Volatile - Nonvolatile memory
Ans :

(ii) SRAM - DRAM memory

Vidyalankar : B.E.  Microwave
4e. Calculate analog o/p of 4 bit DAC for digital input is 04
1100. Assume VFS = 5V.
VR = Vfs = 5V
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 ) 06
1. 1100
Vo = VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4)
= 5 (1*1/2 + 1*1/22 + 0+0 )
= 5 (1*1/2 + 1*1/4 + 0+0)
= 5 (0.5 + 0..25 + 0+0) = 3.75V

5b. Draw block diagram of Dual slope ADC and explain

its working.

Here, an electronic switch is employed to transfer the desired

analog input signal to an integrator, also called a ramp
generator.
This ramp generator may be in the form of a capacitor
charged with a constant current for generating the linear
ramp.
The control logic resets the counter and enables the clock
signal generator in order to send the clock pulses to the
counter, when it is received the start commanding signal.
The output of the integrator is connected to one of the two
inputs of the comparator and the other input of comparator is
connected to ground
Comparator compares the output of the integrator with zero
volts (ground) and produces an output, which is applied to
the control logic.
The counter gets incremented by one for every clock pulse
and its value will be in binary (digital) format. It produces an

89
overflow signal to the control logic, when it is incremented
after reaching the maximum count value. At this instant, all
the bits of counter will be having zeros only.
Now, the control logic pushes the switch sw to connect to the
negative reference voltage −Vref. This negative reference
voltage is applied to an integrator. It removes the charge
stored in the capacitor until it becomes zero.
At this instant, both the inputs of a comparator are having
zero volts. So, comparator sends a signal to the control logic.
Now, the control logic disables the clock signal generator
and retains (holds) the counter value. The counter value is
proportional to the external analog input voltage.
At this instant, the output of the counter will be displayed as
the digital output. It is almost equivalent to the
corresponding external analog input value Vi.
The dual slope ADC is used in the applications,
where accuracy is more important while converting analog
input into its equivalent digital (binary) data