3.
1 Challenges in Multi-Voltage Designs Even the simplest multi-voltage
design presents the designer with some basic chal lenges: • Level shifters.
Signals that go between blocks that use different power rails often require
level shifters – buffers that translate the signal from one voltage swing to
another. • Characterization and STA. With a single supply for the entire chip,
timing analysis can be done at a single performance point. The libraries are
characterized for this point, and the tools perform the analysis in a straight-
forward manner. With multi ple blocks running at different voltages, and with
libraries that may not be charac terized at the exact voltage we are using,
timing analysis becomes much more complex. • Floor planning, power
planning, grids. Multiple power domains require more careful and detailed
floorplanning. The power grids become more complex. • Board level issues.
Multi-voltage designs require additional resources on the board – additional
regulators to provide the additional supplies. • Power up and power down
sequencing. There may be a required sequence for powering up the design in
order to avoid deadlock. 3.2 Voltage Scaling Interfaces – Level Shifters When
driving signals between power domains with radically different power rails,
the need for level shifters is clear. Driving a signal from a 1V domain to a 5V
domain is a problem – the 1V swing may not even reach threshold in the 5V
domain. But the internal voltages in today’s chips are tightly clustered
around 1V. Why would we need level shifters on signals going from a 0.9V
domain to a 1.2V domain? Multi-Voltage Design 23 One fundamental reason
is that a 0.9V signal driving a 1.2V gate will turn on both the NMOS and
PMOS networks, causing crowbar currents.This issue is discussed later in this
chapter. In addition, standard cell libraries are characterized for – and
operate best with – a clean, fast input that goes rail to rail. Failure to meet
this requirement may result in signals exhibiting significant rise- or fall-time
degradation between the driver cell in one domain and the receiver in
another voltage domain. This in turn can lead to tim ing closure problems
and even excessive crowbar switching currents. The best solution is to make
sure each domain gets the voltage swings (and rise- and fall-times) that it
expects. We do this by providing level shifters between any domains that use
different voltages. This approach limits any voltage swing and timing charac
terization issues to the boundary of voltage domains, and leaves the internal
timing of the domain unaffected. This kind of clean interfacing makes timing
closure – and reuse – much easier. 3.2.1 Unidirectional Level Shifters The
design of a level shifter to provide an effective voltage swing between one
differ ent voltage rails is an analog design problem. And for analog design
reasons, these cells are typically only designed to shift one direction - either
from a higher voltage to a lower one, or from a lower voltage to a higher one.
Later in this chapter we provide some example designs that show the
difference between the two types of cells. For static voltage scaling, this
limitation on level shifters is not a problem. But for the other forms of multi-
voltage, where supply voltages can change during operation, it does pose a
challenge. The designer must architect and partition the design such that
voltage domains have a defined relation to neighboring domains – such as
“always higher”, “always lower”, or “always the same.” With this restriction,
it then becomes straightforward to implement the interface with the
appropriate level shifting compo nents. Designing interfaces that can operate
in both directions may appear attractive from a system perspective but
requires non-standard implementation components and tool ing. 3.2.2 Level
Shifters – High to Low Voltage Translation On the face of it, simply
overdriving a CMOS input from an output buffer on a higher voltage rail does
not appear to be a problem – there are no latch-up or breakdown issues,
simply a “better”, faster edge compared to normal CMOS logic high or low
level switching levels. 24 Low Power Methodology Manual However for safe
timing closure one does need some specially identified “down shift” cells
characterized specifically for this purpose. If specialized high-to-low level
shifter cells were not provided in the library then the entire library would
have to be re-characterized to allow accurate static timing analy sis. Each
gate would have to be characterized for an arbitrary input voltage swing. As
shown in Figure 3-1, high to low level shifters can be quite simple, essentially
two inverters in series. Level shifter design is described in more detail in a
later chapter, but for now we just observe that require only a single power
rail, which is the one from the lower or destination power domain. As implied
by the drawing, a high-to-low level shifter only introduces a buffer delay, so
its impact on timing is small. VDDL VDDL INH VSS 3.2.3 Level Shifters – Low-
to-High Voltage OUTL INH OUTL VSS Figure 3-1 High to Low Level Shifters
Driving logic signals from a low supply rail to a cell on a higher voltage rail is
a more critical problem. An under-driven signal degrades the rise and fall
times at the receiv ing inputs. This in turn can lead to higher switching
currents and reduced noise mar gins. A slow transition time means that the
signal spends more time near VT, causing the short circuit (crowbar) current
to last longer than necessary. For clock tree buffering this becomes
particularly important. Clock tree buffering is always a challenge, and any
degradation in rise and fall times across voltage region boundaries can
increase clock skew. Specially designed level shifter cells solve this problem.
They provide fast, full-rail signals to the higher voltage domain. They can be
correctly modeled with the design tools to achieve accurate timing
