DATA SHEET

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Silicon Carbide (SiC)

TAB
Cascode JFET – EliteSiC,
Power N-Channel, D2PAK-3, 1 2
3
650 V, 42 mohm
D2PAK-3 (TO-263, 3-LEAD)
CASE 418AJ
UF3C065040B3
Description MARKING DIAGRAM
This SiC FET device is based on a unique ‘cascode’ circuit
configuration, in which a normally-on SiC JFET is co-packaged with a
Si MOSFET to produce a normally-off SiC FET device. The device’s
standard gate-drive characteristics allows for a true “drop-in UF3C065040B3
replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si AYYWW ZZZ
superjunction devices. Available in the D2PAK-3 package, this device
exhibits ultra-low gate charge and exceptional reverse recovery
characteristics, making it ideal for switching inductive loads when
used with recommended RC-snubbers, and any application requiring
standard gate drive.
UF3C065040B3 = Specific Device Number
Features A = Assembly Location
• Typical On-resistance RDS(on),typ of 42 m YY = Year
WW = Work Week
• Maximum Operating Temperature of 175°C
ZZZ = Lot ID
• Excellent Reverse Recovery
• Low Gate Charge
• Low Intrinsic Capacitance PIN CONNECTIONS
• ESD Protected, HBM Class 2
TAB
• Very Low Switching Losses (Required RC-snubber Loss Negligible D (2)
under Typical Operating Conditions)
• This Device is Halogen Free and RoHS Compliant with Exemption
7a, Pb−Free 2LI (on second level interconnection)

Typical Applications
G (1)
• EV Charging
• PV Inverters
• Switch Mode Power Supplies
• Power Factor Correction Modules S (3)
• Motor Drives
• Induction Heating
ORDERING INFORMATION
See detailed ordering and shipping information on page 9
of this data sheet.

© Semiconductor Components Industries, LLC, 2024 1 Publication Order Number:

March, 2025 − Rev. 3 UF3C065040B3/D
 UF3C065040B3

MAXIMUM RATINGS
Parameter Symbol Test Conditions Value Unit
Drain-source Voltage VDS 650 V
Gate-source Voltage VGS DC −25 to +25 V
Continuous Drain Current (Note 1) ID TC = 25 °C 41 A
TC = 100 °C 30
Pulsed Drain Current (Note 2) IDM TC = 25 °C 125 A
Single Pulsed Avalanche Energy (Note 3) EAS L = 15 mH, IAS = 3.19 A 76 mJ
Power Dissipation Ptot TC = 25 °C 176 W
Maximum Junction Temperature TJ,max 175 °C
Operating and Storage Temperature TJ, TSTG −55 to 175 °C
Reflow Soldering Temperature Tsolder Reflow MSL 1 245 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Limited by TJ,max
2. Pulse width tp limited by TJ,max
3. Starting TJ = 25 °C

THERMAL CHARACTERISTICS
Parameter Symbol Test Conditions Min Typ Max Unit
Thermal Resistance, Junction-to-Case RJC − 0.65 0.85 °C/W

ELECTRICAL CHARACTERISTICS (TJ = +25 °C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit
TYPICAL PERFORMANCE − STATIC
Drain-source Breakdown Voltage BVDS VGS = 0 V, ID = 1 mA 650 − − V
Total Drain Leakage Current IDSS VDS = 650 V, VGS = 0 V, TJ = 25 °C − 0.7 150 A
VDS = 650 V, VGS = 0 V, TJ = 175°C − 10 −
Total Gate Leakage Current IGSS VDS = 0 V, VGS = −20 V / +20 V − 6 ±20 A
Drain-source On-resistance RDS(on) VGS = 12 V, ID = 30 A TJ = 25 °C − 42 52 m
TJ = 125 °C − 59 −
TJ = 175 °C − 78 −
Gate Threshold Voltage VG(th) VDS = 5 V, ID = 10 mA 4 5 6 V
Gate Resistance RG f = 1 MHz, open drain − 4.5 − 
TYPICAL PERFORMANCE − REVERSE DIODE
Diode Continuous Forward Current (Note 1) IS TC = 25 °C − − 41 A
Diode Pulse Current (Note 2) IS,pulse TC = 25 °C − − 125 A
Forward Voltage VFSD VGS = 0 V, IS = 20 A, TJ = 25 °C − 1.5 1.75 V
VGS = 0 V, IS = 20 A, TJ = 175 °C − 1.8 −
Reverse Recovery Charge Qrr VDS = 400 V, IS = 30 A, VGS = −5 V, − 138 − nC
RG_EXT = 22 , di/dt = 1600 A/s,
Reverse Recovery Time trr TJ = 25 °C − 26 − ns

Reverse Recovery Charge Qrr VDS = 400 V, IS = 30 A, VGS = −5 V, − 137 − nC

RG_EXT = 22 , di/dt = 1600 A/s,
Reverse Recovery Time trr TJ = 150 °C − 26 − ns

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 UF3C065040B3

ELECTRICAL CHARACTERISTICS (TJ = +25 °C unless otherwise specified) (continued)

Parameter Symbol Test Conditions Min Typ Max Unit
TYPICAL PERFORMANCE − DYNAMIC
Input Capacitance Ciss VDS = 100 V, VGS = 0 V, − 1500 − pF
f = 100 kHz
Output Capacitance Coss − 200 −
Reverse Transfer Capacitance Crss − 2.2 −
Effective Output Capacitance, Energy Related Coss(er) VDS = 0 V to 400 V, VGS = 0 V − 146 − pF
Effective Output Capacitance, Time Related Coss(tr) − 325 −
COSS Stored Energy Eoss VDS = 400 V, VGS = 0 V − 11.7 − J
Total Gate Charge QG VDS = 400 V, ID = 30 A, − 51 − nC
VGS = −5 V to 15 V
Gate-drain Charge QGD − 11 −
Gate-source Charge QGS − 19 −
Turn-on Delay Time td(on) VDS = 400 V, ID = 30 A, − 34 − ns
Gate Driver = −5 V to +15 V,
Rise Time tr Turn-on RG,EXT = 1.8 , − 15 −
Turn-off Delay Time td(off) Turn-off RG,EXT = 22 , − 57 −
Inductive Load, FWD: same device
Fall Time tf with VGS = −5 V and RG = 22 , − 12 −
Turn-on Energy including RS Energy (Note 4) EON RC snubber: RS = 5  and − 327 − J
CS = 150 pF, TJ = 25 °C
Turn-off Energy including RS Energy (Note 4) EOFF − 65 −
Total Switching Energy including RS Energy ETOTAL − 392 −
(Note 4)
Snubber RS Energy during Turn-on ERS_ON − 1.5 −
Snubber RS Energy during Turn-off ERS_OFF − 3 −
Turn-on Delay Time td(on) VDS = 400 V, ID = 30 A, − 33 − ns
Gate Driver = −5 V to +15 V,
Rise Time tr Turn-on RG,EXT = 1.8 , − 15 −
Turn-off Delay Time td(off) Turn-off RG,EXT = 22 , − 58 −
Inductive Load, FWD: same device
Fall Time tf with VGS = −5 V and RG = 22 , − 13 −
Turn-on Energy including RS Energy (Note 4) EON RC snubber: RS = 5  and − 314 − J
CS = 150 pF, TJ = 150 °C
Turn-off Energy including RS Energy (Note 4) EOFF − 66 −
Total Switching Energy including RS Energy ETOTAL − 380 −
(Note 4)
Snubber RS Energy during Turn-on ERS_ON − 1.5 −
Snubber RS Energy during Turn-off ERS_OFF − 2.9 −
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The switching performance are evaluated with a RC snubber circuit as shown in Figure 29.

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 UF3C065040B3

TYPICAL PERFORMANCE DIAGRAMS

100 100
Vgs = 15 V Vgs = 15 V
Vgs = 8 V Vgs = 8 V
80 Vgs = 7 V 80 Vgs = 7 V
Vgs = 6.5 V Vgs = 6.5 V
ID, Drain Current (A)

ID, Drain Current (A)

Vgs = 6 V Vgs = 6 V
60 60

40 40

20 20

0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
VDS, Drain-Source Voltage (V) VDS, Drain-Source Voltage (V)
Figure 1. Typical Output Characteristics at TJ = −55 5C, Figure 2. Typical Output Characteristics at TJ = 25 5C,
tp < 250 ms tp < 250 ms

100 2.0
Vgs = 15 V
Vgs = 8 V
RDS_ON, On Resistance (P.U.)

80 Vgs = 7 V
1.5
ID, Drain Current (A)

Vgs = 6.5 V
Vgs = 6 V
60
Vgs = 5.5 V
1.0
40

0.5
20

0 0.0
0 1 2 3 4 5 6 7 8 9 10 −75 −50 −25 0 25 50 75 100 125 150 175
VDS, Drain-Source Voltage (V) TJ, Junction Temperature (°C)
Figure 3. Typical Output Characteristics at TJ = 175 5C, Figure 4. Normalized On-Resistance vs.
tp < 250 ms Temperature at VGS = 12 V and ID = 30 A

160 100
Tj = 175 °C Tj = −55 °C
140 Tj = 25 °C Tj = 25 °C
RDS(on), On-Resistance (m)

Tj = −55 °C 80 Tj = 175 °C
120
ID, Drain Current (A)

100 60
80

60 40

40
20
20

0 0
0 20 40 60 80 100 0 1 2 3 4 5 6 7 8 9 10
ID, Drain Current (A) VGS, Gate-Source Voltage (V)
Figure 5. Typical Drain-Source On-Resistances at Figure 6. Typical Transfer Characteristics at VDS = 5 V
VGS = 12 V

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 UF3C065040B3

TYPICAL PERFORMANCE DIAGRAMS (CONTINUED)

6 20

VGS, Gate-Source Voltage (V)

5
Vth, Threshold Voltage (V)

15

4
10
3
5
2

0
1

0 −5
−100 −50 0 50 100 150 200 0 10 20 30 40 50 60
TJ, Junction Temperature (°C) QG, Gate Charge (nC)
Figure 7. Threshold Voltage vs. Junction Temperature Figure 8. Typical Gate Charge at VDS = 400 V and
at VDS = 5 V and ID = 10 mA ID = 30 A

0 0
Vgs = −5 V Vgs = −5 V
Vgs = 0 V Vgs = 0 V
Vgs = 5 V Vgs = 5 V
−20 −20
ID, Drain Current (A)

ID, Drain Current (A)

Vgs = 8 V Vgs = 8 V

−40 −40

−60 −60

−80 −80
−4 −3 −2 −1 0 −4 −3 −2 −1 0
VDS, Drain-Source Voltage (V) VDS, Drain-Source Voltage (V)
Figure 9. 3rd Quadrant Characteristics at TJ = −55 5C Figure 10. 3rd Quadrant Characteristics at TJ = 25 5C

0 30
Vgs = −5 V
Vgs = 0 V 25
Vgs = 5 V
−20
ID, Drain Current (A)

Vgs = 8 V
20
EOSS (J)

−40 15

10
−60
5

−80 0
−4 −3 −2 −1 0 0 100 200 300 400 500 600
VDS, Drain-Source Voltage (V) VDS, Drain-Source Voltage (V)
Figure 11. 3rd Quadrant Characteristics at TJ = 175 5C Figure 12. Typical Stored Energy in COSS at VGS = 0 V

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 UF3C065040B3

TYPICAL PERFORMANCE DIAGRAMS (CONTINUED)

10,000 45
40
Ciss

ID, DC Drain Current (A)

1,000 35
C, Capacitance (pF)

30
Coss 25
100
20
15
10 10
Crss 5
1 0
0 100 200 300 400 500 600 −75 −50 −25 0 25 50 75 100 125 150 175
VDS, Drain-Source Voltage (V) TC, Case Temperature (°C)
Figure 13. Typical Capacitances at f = 100 kHz and Figure 14. DC Drain Current Derating
VGS = 0 V

200
1
ZJC, Thermal Impedance (°C/W)
175
Ptot, Power Dissipation (W)

150

125 0.1
100 D = 0.5
D = 0.3
75 D = 0.1
0.01 D = 0.05
50 D = 0.02
D = 0.01
25 Single Pulse
0 0.001
−75 −50 −25 0 25 50 75 100 125 150 175 1.E−06 1.E−05 1.E−04 1.E−03 1.E−02 1.E−01
TC, Case Temperature (°C) tp, Pulse Time (s)
Figure 15. Total Power Dissipation Figure 16. Maximum Transient Thermal Impedance

150

100 125
1 s
ID, Drain Current (A)

100
10 10 s
Qrr (nC)

75

100 s
50
1
1 ms VDS = 400 V, IS = 30 A,
DC 25 di/dt = 1600 A/s,
10 ms
VGS = −5 V, RG = 22 
0.1 0
1 10 100 1000 0 25 50 75 100 125 150 175
VDS, Drain-Source Voltage (V) TJ, Junction Temperature (°C)
Figure 17. Safe Operation Area at TC = 25 5C, D = 0, Figure 18. Reverse Recovery Charge Qrr vs.
Parameter tp Junction Temperature

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 UF3C065040B3

TYPICAL PERFORMANCE DIAGRAMS (CONTINUED)

600 7
VDS = 400 V, VGS = −5 V / 15 V,
Rs Etot
RC snubber: CS = 150 pF, 6
500 Rs Eon
RS = 5 , FWD: same device

Snubber RS Energy (J)

Rs Eoff
Switching Energy (J)

with VGS = −5 V, RG = 22  5
400
Etot 4
300 Eon
Eoff 3
200
2
100 1

0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
ID, Drain Current (A) ID, Drain Current (A)
Figure 19. Clamped Inductive Switching Energy vs. Figure 20. RC Snubber Energy Loss vs. Drain
Drain Current at TJ = 25 5C, Turn-on RG_EXT = 1.8 W Current at the Test Conditions shown in Figure 19
and Turn-off RG_EXT = 22 W

500 2
Turn-on Snubber RS Energy (J)
Eon, Turn-On Energy (J)

400
1.5

300
1
200 VDS = 400 V, ID = 30 A,
VGS = −5 V / 15 V, TJ = 25 °C,
RC snubber: CS = 150 pF, RS = 5 , 0.5
100 FWD: same device with VGS = −5 V,
RG = 22 

0 0
0 5 10 15 20 0 5 10 15 20
RG_EXT, Total External Turn-on RG () RG_EXT, Total External Turn-on RG ()
Figure 21. Clamped Inductive Switching Turn-On Energy Figure 22. RC Snubber Energy Loss as a Function
including RC Snubber Energy Loss as a Function of of Total External Turn-on Gate Resistor RG_EXT at
Total External Turn-on Gate Resistor RG_EXT the Test Conditions shown in Figure 21

120 4.0
Turn-off Snubber RS Energy (J)

3.5
100
Eoff, Turn-Off Energy (J)

3.0
80
2.5

60 2.0

1.5
40
VDS = 400 V, ID = 30 A,
VGS = −5 V / 15 V, TJ = 25 °C, 1.0
20 RC snubber: CS = 150 pF, RS = 5 , 0.5
FWD: same device with VGS = −5 V
0 0.0
0 10 20 30 40 50 0 10 20 30 40 50
RG_EXT, Total External Turn-off RG () RG_EXT, Total External Turn-off RG ()
Figure 23. Clamped Inductive Switching Turn-Off Energy Figure 24. RC Snubber Energy Loss as a Function of
including RC Snubber Energy Loss as a Function of Total External Turn-off Gate Resistor RG_EXT at the
Total External Turn-off Gate Resistor RG_EXT Test Conditions shown in Figure 23

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 UF3C065040B3

TYPICAL PERFORMANCE DIAGRAMS (CONTINUED)

500 5.0
Etot
Eon 4.5
400 Eoff 4.0 Rs Etot

Snubber RS Energy (J)

Switching Energy (J)

Rs Eon
3.5
Rs Eoff
300 3.0
2.5
200 VDS = 400 V, VGS = −5 V / 15 V, RG_ON = 1.8 ,
2.0
RG_OFF = 22 , FWD: same device with VGS = −5 V,
RG = 22 , RC snubber: CS = 150 pF, RS = 5  1.5
100 1.0
0.5
0 0.0
0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175
TJ, Junction Temperature (°C) TJ, Junction Temperature (°C)
Figure 25. Clamped Inductive Switching Energy Figure 26. RC Snubber Energy Loss as a Function of
including RC Snubber Energy Loss as a Function of Junction Temperature at the Test Conditions shown
Junction Temperature at ID = 30 A in Figure 25

500 14
Etot Rs Etot
Eon 12 Rs Eon
400 Eoff Rs Eoff
Snubber RS Energy (J)
Switching Energy (J)

10
300 8

200 VDS = 400 V, VGS = −5 V / 15 V, RG_ON = 1.8 , 6

RG_OFF = 22 , FWD: same device with VGS = −5 V,
RG = 22 , RC snubber: RS = 5  4
100
2

0 0
0 100 200 300 400 0 100 200 300 400
CS, Snubber Capacitance (pF) CS, Snubber Capacitance (pF)
Figure 27. Clamped Inductive Switching Energy Figure 28. RC Snubber Energy Loss as a Function
including RC Snubber Energy Loss as a Function of of Snubber Capacitance at the Test Conditions
Snubber Capacitance at ID = 30 A and TJ = 25 5C shown in Figure 27

Figure 29. Clamped Inductive Load Switching Test Circuit. An RC Snubber (RS = 5 W and CS = 150 pF) is required
to Improve the Turn-off Waveforms.

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 UF3C065040B3

APPLICATIONS INFORMATION

SiC FETs are enhancement-mode power switches formed working in the diode mode in order to achieve the optimum
by a high-voltage SiC depletion−mode JFET and a reverse recovery performance. For more information on SiC
low-voltage silicon MOSFET connected in series. The FET operation, see www.onsemi.com.
silicon MOSFET serves as the control unit while the SiC A snubber circuit with a small R(G), or gate resistor,
JFET provides high voltage blocking in the off state. This provides better EMI suppression with higher efficiency
combination of devices in a single package provides compared to using a high R(G) value. There is no extra gate
compatibility with standard gate drivers and offers superior delay time when using the snubber circuitry, and a small R(G)
performance in terms of low on-resistance (RDS(on)), output will better control both the turn-off V(DS) peak spike and
capacitance (Coss), gate charge (QG), and reverse recovery ringing duration, while a high R(G) will damp the peak spike
charge (Qrr) leading to low conduction and switching losses. but result in a longer delay time. In addition, the total
The SiC FETs also provide excellent reverse conduction switching loss when using a snubber circuit is less than using
capability eliminating the need for an external anti-parallel high R(G), while greatly reducing E(OFF) from mid-to-full
diode. load range with only a small increase in E(ON). Efficiency
Like other high performance power switches, proper PCB will therefore improve with higher load current. For more
layout design to minimize circuit parasitics is strongly information on how a snubber circuit will improve overall
recommended due to the high dv/dt and di/dt rates. An system performance, visit the onsemi website at
external gate resistor is recommended when the FET is www.onsemi.com.

ORDERING INFORMATION
Part Number Marking Package Shipping†
UF3C065040B3 UF3C065040B3 D2PAK−3 (TO−263, 3−LEAD) 800 units / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

D2PAK−3 (TO−263, 3−LEAD)

CASE 418AJ
ISSUE F
SCALE 1:1 DATE 11 MAR 2021

XXXXXX = Specific Device Code

A = Assembly Location
GENERIC MARKING DIAGRAMS* WL = Wafer Lot
Y = Year
WW = Work Week
XX W = Week Code (SSG)
AYWW
XXXXXXXXX XXXXXXXXG XXXXXX M = Month Code (SSG)
XXXXXXXXG
AWLYWWG AYWW XXYMW G = Pb−Free Package
AKA
AKA = Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
IC Standard Rectifier SSG may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON56370E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: D2PAK−3 (TO−263, 3−LEAD) PAGE 1 OF 1

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