Management and Public Service College
Department of Information Technology
ITec3071-Coputer Organization and Architecture
Final Exam
______________________________________________________________________________
Name: ____________________________ID: ________ Time allowed: 2:00 Hrs. Weight 40%
Program: _______________ (Regular / Weekend)
Instructions: -
The exam contains 4 parts.
Make sure that your answers are clear and to the point.
Cheat and all attempts to cheat leads to punishment.
Don’t forget to write your Name and ID on the first page.
Part Part I (5) Part II (20) Part III (5) Part III (20) Total (50)
Marks Obtained
Good Luck!
1|Page
Part I: True or False ( 1 Point each)
Instruction:_________________________________________________________?
1. Direct Memory Access data transfer techniques need CPU involvements to exchange data.
2. Data bus was designed to carry the actual data between memory and processor.
3. Both ASCII and Unicode (or UTF-8 encoding) are capable for representing all non-numeric
data in computing systems.
4. Memory classified as erasable permits the overwriting or deletion of its stored data when
needed.
5. When designing digital circuits, minimizing gate delays is no essential for faster circuit
operation.
Part II: Multiple Choice Items (1 Point each)
Instruction:__________________________
?
1. Off the following which method can be used to reduce I/O wait times by allowing batch
processing.
A. Programmed I/O C. Handshaking
B. Interrupt driven I/O D. Buffering
2. What is the primary function of the control unit in a CPU?
A. Perform arithmetic operations C. Decode and execute instructions
B. Manage memory access D. Store program data
3. Which register holds the address of the next instruction to be executed?
A. Accumulator C. Instruction Register (IR)
B. Program Counter (PC) D. Memory Address Register (MAR
4. What does CISC stand for?
A. Complex Instruction Set Computer C. Centralized Instruction System
B. Compact Instruction Set Computing D. Cache-Inclusive Storage Control
5. Subtract 1001210012 from 1101211012:
2|Page
A. 0100201002 C. 1000210002
B. 0100201002 D. 0010200102
6. Which gate outputs 1 only when both inputs are 1?
A. AND C. NOT
B. OR D. XOR
7. The 1’s complement of 1010210102 is:
A. 0101201012 C. 1011210112
B. 0101201012 D. 1101211012
8. _______________ is a small, high-speed storage area in a computer system.
A. Cache memory C. External memory
B. Main memory D. All
9. The ALU performs:
A. Instruction fetching C. Arithmetic and logical operations
B. Power management D. Data storage
10. Which RAID level provides both striping and parity?
A. RAID level 5 C. RAID level 3
B. RAID level 1 D. RAID level 2
Part III: Matching (5 pts)
Instruction: Match the information listed under “A” with those that correspond in column
“B”
Answer Column A Column B
3|Page
1. Array A. Concerned with two values
2. Address bus B. It is the reverse of programmed I/O.
3. Interrupt-driven I/O C. Start at the beginning and read
through in order
4. Boolean expressions D. Temporary memory
5. Sequential access E. It carries the address of data
F. Allows users to store and
manipulate a collection of elements
Part IV. Essay/Short answer (20 Pts )
1. Convert the binary number 100110112 to decimal number (2pts).
2. Perform the following arithmetic operations (4pts)
A. 010111 + 001100
B. 1011 – 0110
C. 1010 * 1001
D. 1100 ÷ 0100
3. List the different types of flip-flops and draw the block diagram of each (4pts).
4. Construct the truth table and draw the logic diagram for the following Boolean function
(4pts).
X = A + BC + D .
5. Discuss the working principle of the three primary DMA configurations? (3pts)
6. List down the key characteristics of memory systems(3pts)
4|Page
