UNIT-IV: INPUT-OUTPUT AND MEMORY ORGANIZATION

I/O Bus and Interface Modules:

The I/O bus is the route used for peripheral devices to interact with the computer processor. A typical connection of the I/O bus
to I/O devices is shown in the figure.

The I/O bus includes data lines, address lines, and control lines. In any general-purpose computer, the magnetic disk, printer, and
keyboard, and display terminal are commonly employed. Each peripheral unit has an interface unit associated with it. Each
interface decodes the control and address received from the I/O bus.
It can describe the address and control received from the peripheral and supports signals for the peripheral controller. It also
conducts the transfer of information between peripheral and processor and also integrates the data flow.
The I/O bus is linked to all peripheral interfaces from the processor. The processor locates a device address on the address line to
interact with a specific device. Each interface contains an address decoder attached to the I/O bus that monitors the address lines.
When the address is recognized by the interface, it activates the direction between the bus lines and the device that it controls.
The interface disables the peripherals whose address does not equivalent to the address in the bus.
An interface receives any of the following four commands −
 Control − A command control is given to activate the peripheral and to inform its next task. This control command
depends on the peripheral, and each peripheral receives its sequence of control commands, depending on its mode of
operation.
 Status − A status command can test multiple test conditions in the interface and the peripheral.
 Data Output − A data output command creates the interface counter to the command by sending data from the bus to
one of its registers.
 Data Input − The data input command is opposite to the data output command. In data input, the interface gets an
element of data from the peripheral and places it in its buffer register.
Asynchronous Data Transfer
Asynchronous data transfer enables computers to send and receive data without having to wait for a real-time
real
response. With this technique, data is conveyed in discrete units known as packets that may be handled
separately. This article will explain what asynchronous data transfer is, its primary terminologies, advantages and
disadvantages, and some frequently asked questions.

Terminologies used in Asynchronous Data Transfer

 Sender:: The machine or gadget that transfers the data.
 Receiver: A device or computer that receives data.
 Packet:: A discrete unit of transmitted and received data.
 Buffer: A short-term
term location for storing incoming or departing data.

Classification of Asynchronous Data Transfer

 Strobe Control Method
 Handshaking Method

Strobe Control Method for Data Transfer

Transfer:
Strobe control is a method used in asynchronous data transfer that synchronizes data flow between two devices.
Bits are transmitted one at a time, independently of one another, and without the aid of a clock signal in
asynchronous communication. To properly receive the data, the receiving equipment needs to be able to
synchronize with the transmitting devi
device.
Strobe control involves sending data along with a different signal known as the strobe signal. The strobe signal
alerts the receiving device that the data is valid and ready to be read. The receiving device waits for the strobe
signal before reading thee data to ensure sure it is synchronized with its clock.
The strobe signal is usually generated by the transmitting device and is sent either before or after the data. If the
strobe signal is sent before the data, it is called a leading strobe. If it is se
sent
nt after the data, it is called a trailing
strobe.

Types of Strobes
It is advantageous to utilize strobe control because it enables asynchronous data transfer, which is helpful when
the participating devices have dissimilar clock rates or are not synchro
synchronized.
nized. The time of data transfer is also
made more flexible by strobe control since the receiving device doesn’t have to synchronize with the transmitting
device’s clock; instead, it can wait for the strobe signal before reading the data.
Overall, strobe control,
ontrol, which is frequently employed in a range of electronic devices and systems, is a helpful
technique for assuring dependable data flow in asynchronous communication.

Handshaking Method for Data Transfer:

During an asynchronous data transfer, two devices manage their communication using handshaking.
handshaking It is
guaranteed that the transmitting and receiving devices are prepared to send and receive data. Handshakes are
essential in asynchronous communication since there is no clock signal to synchronize tthe
he data transfer.
During handshaking, we use two types of signals mostly they are request
request-to-send
send (RTS) and clear-to-send
clear (CTS).
The receiving device is notified by an RTS signal when the transmitting equipment is ready to provide data. The
receiving devicee responds with a CTS signal when it is ready to accept data.
once data is transmitted to the receiver end. the receiver generates a signal that it has done by sending an
acknowledgment (ACK) signal. If the data is not successfully received, the receiving device will notify that a new
transmission is necessary via a negative acknowledgment (NAK) signal.
The handshaking procedure guarantees synchronized and dependable data delivery. Additionally, it allows for
flow management, preventing the transmitting device from sending the receiving device an excessive amount of
data all at once. In order to offer flow control, handshaking signals are utilized to regulate the rate at which data
is sent.
The Handshaking Method in asynchronous data transfer is used in different devices for the transfer of data to
ensure reliable communication.

Advantages of Asynchronous Data Transfer

 Because asynchronous data transfer sends data in discrete, independently processable pieces, it enables faster
data transfer speeds.
 This method is more effective than synchronous data transfer because there is no need for the receiver to
respond.
 Transmission is done by making large files or data sets into smaller packets and sending them in parallel cuts
the duration time.

Disadvantages of Asynchronous Data Transfer

 Asynchronous data transfer requires more complex programming and it may be possible that some data may
get corrupted or lose data if packets are not received in the correct order or are lost during transmission.
 As we know there will be no real-time communication in asynchronous data transport can be more prone to
errors than synchronous data transfer.

Mode of Transfer:
The binary information that is received from an external device is usually stored in the memory unit. The
information that is transferred from the CPU to the external device is originated from the memory unit. CPU
merely processes the information but the source and target is always the memory unit. Data transfer between CPU
and the I/O devices may be done in different modes. Data transfer to and from the peripherals may be done in any
of the three possible ways

1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now let’s discuss each mode one by one.

1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program. Each
data item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU register and
memory. In this case it requires constant monitoring by the CPU of the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory unit. A
 transfer from I/O device to memory requires the execution of several instructions by the CPU, including an
input instruction to transfer the data from device to the CPU and store instruction to transfer the data from
CPU to memory. In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is
ready for data transfer. This is a time consuming process since it needlessly keeps the CPU busy. This
situation can be avoided by using an interrupt facility. This is discussed below.
2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This situation
can very well be avoided by using an interrupt driven method for data transfer. By using interrupt facility and
special commands to inform the interface to issue an interrupt request signal whenever data is available from
any device. In the meantime the CPU can proceed for any other program execution. The interface meanwhile
keeps monitoring the device. Whenever it is determined that the device is ready for data transfer it initiates an
interrupt request signal to the computer. Upon detection of an external interrupt signal the CPU stops
momentarily the task that it was already performing, branches to the service program to process the I/O
transfer, and then return to the task it was originally performing.
 The I/O transfer rate is limited by the speed with which the processor can test and service a device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each
I/O transfer.
 Terms:
 Hardware Interrupts: Interrupts present in the hardware pins.
 Software Interrupts: These are the instructions used in the program whenever the required
functionality is needed.
 Vectored interrupts: These interrupts are associated with the static vector address.
 Non-vectored interrupts: These interrupts are associated with the dynamic vector address.
 Maskable Interrupts: These interrupts can be enabled or disabled explicitly.
 Non-maskable interrupts: These are always in the enabled state. we cannot disable them.
 External interrupts: Generated by external devices such as I/O.
 Internal interrupts: These devices are generated by the internal components of the processor
such as power failure, error instruction, temperature sensor, etc.
 Synchronous interrupts: These interrupts are controlled by the fixed time interval. All the
interval interrupts are called as synchronous interrupts.
 Asynchronous interrupts: These are initiated based on the feedback of previous instructions.
All the external interrupts are called as asynchronous interrupts.
3. Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and memory
unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each
other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is
known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory
buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and
the memory unit.
 1. Bus grants request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the speed
at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU So, total time taken to transfer the N bytes = Bus grant request
time + (N) * (memory transfer rate) + Bus release control time.
Buffer the byte into the buffer
Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
Transfer the byte (at system bus speed)
Release the control of the bus back to CPU.

Priority Interrupts:
In I/O Interface (Interrupt and DMA Mode), we have discussed the concept behind the Interrupt-initiated I/O. To
summarize, when I/O devices are ready for I/O transfer, they generate an interrupt request signal to the computer.
The CPU receives this signal, suspends the current instructions it is executing, and then moves forward to service
that transfer request. But what if multiple devices generate interrupts simultaneously. In that case, we have a way
to decide which interrupt is to be serviced first. In other words, we have to set a priority among all the devices for
systemic interrupt servicing. The concept of defining the priority among devices so as to know which one is to be
serviced first in case of simultaneous requests is called a priority interrupt system. This could be done with either
software or hardware methods.
SOFTWARE METHOD – POLLING

In this method, all interrupts are serviced by branching to the same service program. This program then checks
with each device if it is the one generating the interrupt. The order of checking is determined by the priority that
has to be set. The device having the highest priority is checked first and then devices are checked in descending
order of priority. If the device is checked to be generating the interrupt, another service program is called which
works specifically for that particular device. The structure will look something like this-

if (device[0].flag)

device[0].service();

else if (device[1].flag)

device[1].service();

.
.

else

//raise error

The major disadvantage of this method is that it is quite slow. To overcome this, we can use hardware solution,
one of which involves connecting the devices in series. This iis called Daisy-chaining method.

HARDWARE METHOD – DAISY CHAINING

The daisy-chaining
chaining method involves connecting all the devices that can request an interrupt in a serial manner.
This configuration is governed by the priority of the devices. The device with the highest priority is placed first
followed by the second highest priority device and so on. The given figure depicts this arrangement.

WORKING: There is an interrupt request line which is common to all the devices and goes into the CPU.
 When no interrupts
pts are pending, the line is in HIGH state. But if any of the devices raises an interrupt, it
places the interrupt request line in the LOW state.
 The CPU acknowledges this interrupt request from the line and then enables the interrupt acknowledge line in
response to the request.
 This signal is received at the PI(Priority in) input of device 1.
 If the device has not requested the interrupt, it passes this signal to the next device through its PO(priority out)
output. (PI = 1 & PO = 1)
 However, if the device had requested the interrupt, (PI =1 & PO = 0)
  The device consumes the acknowledge signal and block its further use by placing 0 at its
PO(priority out) output.
 The device then proceeds to place its interrupt vector address(VAD) into the data bus of CPU.
 Thee device puts its interrupt request signal in HIGH state to indicate its interrupt has been taken
care of.
 If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that acknowledge signal
has been blocked. (PI = 0 & PO = 0)
Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an interrupt.
Therefore, by daisy chain arrangement we have ensured that the highest priority interrupt gets serviced first and
have established a hierarchy. The farther a device is from the first device, the lower its priority.

Memory Organization
The memory is organized in the form of a cell; each cell is able to be identified with a unique number called
address. Each cell is able to recognize control signals such as “read” and “write”, generated by CPU when it
wants to read or write address. Whenever CPU executes the program there is a need to transfer the instruction
from the memory to CPU because the program is available in memory. To access the instruction CPU generates
the memory request.
 Memory Hierarchy
Hierarchy:
A memory unit is an essential component in any digital computer since it is needed for storing programs and data.

Typically, a memory unit can be classified into two categories:

1. The memory unit that establishes

stablishes direct communication with the CPU is called Main Memory.
Memory The main
memory is often referred to as RAM (Random Access Memory).
2. The memory units that provide backup storage are called Auxiliary Memory.. For instance, magnetic disks
and magnetic tapess are the most commonly used auxiliary memories.

Apart from the basic classifications of a memory unit, the memory hierarchy consists all of the storage devices
available in a computer system ranging from the slow but high
high-capacity
capacity auxiliary memory to relatively
rela faster main
memory.

The following image illustrates the components in a typical memory hierarchy.

Auxiliary Memory
Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-access storage in a computer system.
Auxiliary memory provides storage for programs and data that are kept for long-term storage or when not in
immediate use. The most common examples of auxiliary memories are magnetic tapes and magnetic disks.

A magnetic disk is a digital computer memory that uses a magnetization process to write, rewrite and access data.
For example, hard drives, zip disks, and floppy disks.

Magnetic tape is a storage medium that allows for data archiving, collection, and backup for different kinds of data.

Main Memory
The main memory in a computer system is often referred to as Random Access Memory (RAM). This memory unit
communicates directly with the CPU and with auxiliary memory devices through an I/O processor.

The programs that are not currently required in the main memory are transferred into auxiliary memory to provide
space for currently used programs and data.

I/O Processor
The primary function of an I/O Processor is to manage the data transfers between auxiliary memories and the main
memory.

Cache Memory
The data or contents of the main memory that are used frequently by CPU are stored in the cache memory so that the
processor can easily access that data in a shorter time. Whenever the CPU requires accessing memory, it first checks
the required data into the cache memory. If the data is found in the cache memory, it is read from the fast memory.
Otherwise, the CPU moves onto the main memory for the required data.

We will discuss each component of the memory hierarchy in more detail later in this chapter.

Main Memory
The main memory acts as the central storage unit in a computer system. It is a relatively large and fast memory
which is used to store programs and data during the run time operations.

The primary technology used for the main memory is based on semiconductor integrated circuits. The integrated
circuits for the main memory are classified into two major units.

1. RAM (Random Access Memory) integrated circuit chips

2. ROM (Read Only Memory) integrated circuit chips
RAM integrated circuit chips
chips:
The RAM integrated circuit chips are further classified into two possible operating modes, static and dynamic.

The primary compositions of a static RAM are flip flip-flops

flops that store the binary information. The nature of the stored
information is volatile, i.e. it remains valid as long as power iiss applied to the system. The static RAM is easy to use
and takes less time performing read and write operations as compared to dynamic RAM.

The dynamic RAM exhibits the binary information in the form of electric charges that are applied to capacitors. The
capacitors are integrated inside the chip by MOS transistors. The dynamic RAM consumes less power and provides
large storage capacity in a single memory chip.

RAM chips are available in a variety of sizes and are used as per the system requirement. The following
fol block
diagram demonstrates the chip interconnection in a 128 * 8 RAM chip.

o A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits (one byte) per word. This requires a
7-bit address and an 8-bit
bit bidirectional data bus.
o The 8-bit bidirectional
ctional data bus allows the transfer of data either from memory to CPU during
a read operation or from CPU to memory during a write operation.
o The read and write inputs specify the memory operation, and the two chip select (CS) control inputs are
for enabling
ing the chip only when the microprocessor selects it.
o The bidirectional data bus is constructed using three-state buffers.
o The output generated by three--state
state buffers can be placed in one of the three possible states which include a
signal equivalent to logic
gic 1, a signal equal to logic 0, or a high
high-impedance state.

The following function table specifies the operations of a 128 * 8 RAM chip.
From the functional table, we can conclude that the unit is in operation only when CS1 = 1 and CS2 = 0. The bar on
top
op of the second select variable indicates that this input is enabled when it is equal to 0.

ROM integrated circuit

The primary component of the main memory is RAM integrated circuit chips, but a portion of memory may be
constructed with ROM chips.

A ROM memory is used for keeping programs and data that are permanently resident in the computer.

Apart from the permanent storage of data, the ROM portion of main memory is needed for storing an initial program
called a bootstrap loader.. The primary function of the bootstrap loader program is to start the computer software
operating when power is turned on.

ROM chips are also available in a variety of sizes and are also used as per the system requirement. The following
block diagram demonstrates the chip interco
interconnection in a 512 * 8 ROM chip.
 o A ROM chip has a similar organization as a RAM chip. However, a ROM can only perform read operation;
the data bus can only operate in an output mode.
o The 9-bit
bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
o The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate. Otherwise, the data bus
is said to be in a high-impedance
impedance state.

Auxiliary Memory:
An Auxiliary memory is known as the lowest
lowest-cost, highest-capacity and slowest-access
access storage in a computer
system. It is where programs and data are kept for long
long-term
term storage or when not in immediate use. The most
common examples of auxiliary memories are magnetic tapes and magnetic disks.

Magnetic Disks
A magnetic disk is a type of memory constructed using a circular plate of metal or plastic coated with magnetized
materials. Usually, both sides of the disks are used to carry out read/write operations. However, several disks may be
stacked on one spindle with read/write head available on each surface.

The following image shows the structural representation for a magnetic disk.

o The memory bits are stored in the magnetized surface in spots along the concentric circles called tracks.
o The concentric circles (tracks) are commonly divided into sections called sectors.
Magnetic Tape
Magnetic tape is a storage medium that allows data archiving, collection, and backup for different kinds of data. The
magnetic tape is constructed using a plastic strip coated with a magnetic re
recording medium.

The bits are recorded as magnetic spots on the tape along several tracks. Usually, seven or nine bits are recorded
simultaneously to form a character together with a parity bit.

Magnetic tape units can be halted, started to move forward or in reverse, or can be rewound. However, they cannot
be started or stopped fast enough between individual characters. For this reason, information is recorded in blocks
referred to as records.

Associative Memory
Memory:
An associative memory can be considered as a memory unit whose stored data can be identified for
access by the content of the data itself rather than by an address or memory location.

Associative memory is often referred to as Content Addressable Memory (CAM).

When a write operation is performed on associative memory, no address or memory location is given to
the word. The memory itself is capable of finding an empty unused location to store the word.

On the other hand, when the word is to be read from an associative memory, the content of the word, or
part of the word, is specified. The words which match the specified content are located by the memory
and are marked for reading.

The following diagram shows the block representation of an Associative memory.

From the block diagram, we can say that an associative memory consists of a memory array and logic for
'm' words with 'n' bits per word.

The functional registers like the argument register A and key register K each have n bits, one for each bit
of a word. The match register M consists of m bits, one for each memory word.

The words which are kept in the memory are compared in parallel with the content of the argument
register.

The key register (K) provides a mask for choosing a particular field or key in the argument word. If the
key register contains a binary value of all 1's, then the entire argument is compared with each memory
word. Otherwise, only those bits in the argument that have 1's in their corresponding position of the key
register are compared. Thus, the key provides a mask for ide identifying
ntifying a piece of information which
specifies how the reference to memory is made.

The following diagram can represent the relation between the memory array and the external registers in
an associative memory.

The cells present inside the memory array are marked by the letter C with two subscripts. The first
subscript gives the word number and the second specifies the bit position in the word. For instance, the
cell Cij is the cell for bit j in word i.

A bit Aj in the argument register is compared with all the bits in column j of the array provided that Kj =
1. This process is done for all columns j = 1, 2, 3......, n.
If a match occurs between all the unmasked bits of the argument and the bits in word i,, the corresponding
bit Mi in the match register is set to 1. If one or more unmasked bits of the argument and the word do not
match, Mi is cleared to 0.

Cache Memory:
The data or contents of the main memory that are used frequently by CPU are stored in the cache memory
so that the processor can easily access that data in a shorter time. Whenever the CPU needs to access
memory, it first checks the cache memory. If the data is not found in cache memory, then the CPU moves
into the main memory.

Cache memory is placed between the CPU and the main memory. Th
Thee block diagram for a cache memory
can be represented as:

The cache is the fastest component in the memory hierarchy and approaches the speed of CPU
components.

Cache memory is organized as distinct set of blocks where each set contains a small fixed number
num of
blocks.
As shown in the above sets are represented by the rows. The example contains N sets and each set
contains four blocks. Whenever an access is made to cache, the cache controller does not search the entire
cache in order to look for a match. Rather, the controller maps the address to a particular set of the cache
and therefore searches only the set for a match.

If a required block is not found in that set, the block is not present in the cache and cache controller does
not search it further. This kind of cache organisation is called set associative because the cache is divided
into distinct sets of blocks. As each set contains four blocks the cache is said to be four way set
associative.

The basic operation of a cache memory is as follows:

o When the CPU needs to access memory, the cache is examined. If the word is found in the cache,
it is read from the fast memory.
o If the word addressed by the CPU is not found in the cache, the main memory is accessed to read
the word.
 o A block of words one just accessed is then transferred from main memory to cache memory. The
block size may vary from one word (the one just accessed) to about 16 words adjacent to the one
just accessed.
o The performance of the cache memory is frequently measured in terms of a quantity called hit
ratio.
o When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
o If the word is not found in the cache, it is in main memory and it counts as a miss.
o The ratio of the number of hits divided by the total CPU references to memory (hits plus misses)
is the hit ratio.

Levels of memory:
Level 1

It is a type of memory in which data is stored and accepted that are immediately stored in CPU. Most
commonly used register is accumulator, Program counter, address register etc.

Level 2

It is the fastest memory which has faster access time where data is temporarily stored for faster access.

Level 3

It is memory on which computer works currently. It is small in size and once power is off data no longer
stays in this memory.

Level 4

It is external memory which is not as fast as main memory but data stays permanently in this memory.

Cache Mapping:
There are three different types of mapping used for the purpose of cache memory which are as follows:

o Direct mapping,
o Associative mapping
o Set-Associative mapping

Direct Mapping -
In direct mapping, the cache consists of normal high-speed random-access memory. Each location in the
cache holds the data, at a specific address in the cache. This address is given by the lower significant bits
of the main memory address. This enables the block to be selected directly from the lower significant bit
of the memory address. The remaining higher significant bits of the address are stored in the cache with
the data to complete the identification of the cached data.
 `
As shown in the above figure, the address from processor is divided into two field a tag and an index.

The tag consists of the higher significant bits of the address and these bits are stored with the data in
cache. The index consists of the lower significant b of the address. Whenever the memory is referenced,
the following sequence of events occurs

1. The index is first used to access a word in the cache.

2. The tag stored in the accessed word is read.
3. This tag is then compared with the tag in the address.
4. If two tags are same this indicates cache hit and required data is read from the cache word.
5. If the two tags are not same, this indicates a cache miss. Then the reference is made to the main
memory to find it.

For a memory read operation, the word is then transferred into the cache. It is possible to pass the
information to the cache and the process simultaneously.

In direct mapped cache, there can also be a line consisting of more than one word as shown in the
following figure
In such a case,
e, the main memory address consists of a tag, an index and a word within a line. All the
words within a line in the cache have the same stored tag

The index part in the address is used to access the cache and the stored tag is compared with required tag
address.

For a read operation, if the tags are same, the word within the block is selected for transfer to the
processor. If tags are not same, the block containing the required word is first transferred to the cache. In
direct mapping, the corresponding blo blocks
cks with the same index in the main memory will map into the
same block in the cache, and hence only blocks with different indices can be in the cache at the same
time. It is important that all words in the cache must have different indices. The tags may beb the same or
different.

Set Associative Mapping -

In set associative mapping a cache is divided into a set of blocks. The number of blocks in a set is known
as associativity or set size. Each block in each set has a stored tag. This tag together with index
completely identifies the block.

Thus, set associative mapping allows a limited number of blocks, with the same index and different tags.

An example of four way set associative cache having four blocks in each set is shown in the following
figure
In
n this type of cache, the following steps are used to access the data from a cache:

1. The index of the address from the processor is used to access the set.
2. Then the comparators are used to compare all tags of the selected set with the incoming tag.
3. If a match
ch is found, the corresponding location is accessed.
4. If no match is found, an access is made to the main memory.

The tag address bits are always chosen to be the most significant bits of the full address, the block address
bits are the next significant bitss and the word/byte address bits are the least significant bits. The number
of comparators required in the set associative cache is given by the number of blocks in a set. The set can
be selected quickly and all the blocks of the set can be read out simultsimultaneously
aneously with the tags before
waiting for the tag comparisons to be made. After a tag has been identified, the corresponding block can
be selected.

Fully associative mapping

In fully associative type of cache memory, each location in cache stores both memo
memory
ry address as well as
data.
Whenever a data is requested, the incoming memory address a simultaneously compared with all stored
addresses using the internal logic the associative memory.

If a match is found, the corresponding is read out. Otherwise, the main memory is accessed if address is
not found in cache.

This method is known as fully associative mapping approach because cached data is related to the main
memory by storing both memory address and data in the cache. In all organisations, data can be more
m than
one word as shown in the following figure.
A line constitutes four words, each word being 4 bytes. In such case, the least significant part of the
address selects the particular byte, the next part selects the word, and the remaining bits form the address.
These address bits are compared to the address in the cache. The whole line can be transferred to and
from the cache in one transaction if there are sufficient data paths between the main memory and the
cache. With only one data word path, the words of the line have to be transferred in separate transactions.

The main advantage of fully associative mapped cache is that it provides greatest flexibility of holding
combinations of blocks in the cache and conflict for a given cache.

It suffers from certain disadvantages:

1. It is expensive method because of the high cost of associative memory.

2. It requires a replacement algorithm in order to select a block to be removed whenever cache miss
occurs.
3. Such an algorithm must be implemented in hardware to maintain a high speed of operation.

The fully associative mechanism is usually employed by microprocessors with small internal cache.