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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015 1

A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE

802.11ac Applications in 20 nm CMOS
Chun-Cheng Liu, Member, IEEE, Che-Hsun Kuo, and Ying-Zu Lin, Member, IEEE

Abstract—This paper presents a low-cost successive approx-

imation register (SAR) analog-to-digital converter (ADC) for
IEEE 802.11 ac applications. In this paper, a binary-scaled re-
combination capacitor weighting method is disclosed. The digital
sub-blocks in this ADC are composed of standard library logic
cells. The prototype is fabricated in a 1P8M 20 nm CMOS tech-
nology. At 0.9 V supply and 160 MS/s, the ADC consumes 0.68
mW. It achieves an SNDR of 57.7 dB and 57.13 dB at low and
Nyquist input frequency, respectively, resulting in figures of merit
(FoMs) of 6.8 and 7.3 fJ/conversion-step, respectively. At 1 V
supply and 320 MS/s, the ADC consumes 1.52 mW. It achieves
an SNDR of 57.1 dB and 50.89 dB at low and Nyquist input Fig. 1. Architecture of a WLAN RX system.
frequency, respectively, resulting in FoMs of 8.1 and 16.5 fJ/con-
version-step, respectively. The ADC core only occupies an active
area of m m. TABLE I
IEEE802.11 STANDARDS EVOLUTION
Index Terms—20 nm CMOS, analog-to-digital converter (ADC),
IEEE 802.11ac, low cost, low power, redundancy, successive ap-
proximation register (SAR).

I. INTRODUCTION

T ODAY'S digital life is all about connections. People

connect to the internet for daily work, entertainment
and communication. The growing number of mobile devices,
like smart phones, notebook, tablet, etc., makes our life more
convenient. The high data rate applications such as wireless dis-
play and rapid media content upload/download are driving the With the progress of CMOS technology, the feature size
need for high-data-rate wireless local area network (WLAN). of CMOS devices is scaled down. The conversion rate of
Table I shows the evolution of IEEE 802.11 WLAN standards. successive approximation register (SAR) ADCs improves with
The IEEE 802.11ac ( th Generation Wi-Fi) is expected to be the growing transistor bandwidth. The SAR ADC becomes an
the mainstream WLAN specification in the next few years. The attractive ADC architecture in the nanometer scaled CMOS
mandatory channel bandwidths of IEEE 802.11ac system are processes. A lot of recent research activity has been invested in
20 MHz, 40 MHz, and 80 MHz (80 80 MHz and 160 MHz this type of ADCs. The asynchronous SAR ADC [2] eliminates
are optional) [1]. Fig. 1 shows the architecture of a WLAN the need of high frequency clock and speed up the SAR oper-
RX system which includes antenna, mixer, analog filter, I/Q ation. The passive charge sharing SAR ADCs [3]–[5] works
ADCs, digital filter, decimation unit and FFT unit. To reserve in charge domain and uses only passive circuits to reduce the
some bandwidth margin for digital filtering or decimation, the power consumption of reference buffer. The sampling phase
sampling rate of I/Q ADCs must be higher than the is also enlarged. The redundant SAR ADCs [6], [7] adds extra
signal bandwidth. Therefore, the receiver of an IEEE 802.11ac redundant bit to tolerate a certain range of settling and decision
system requires an analog-to-digital converter (ADC) with a error during bit-cycling, therefore, improves the conversion
sampling rate of 160 to 320 MS/s and a resolution of 8 to 10 bits speed. The time-interleaving SAR ADC [8], [9] enhances the
for sufficient signal bandwidth and signal to noise ratio (SNR). sampling rate. Digital calibration technique [8] overcomes
the channel mismatch problem and other nonideal effects
in medium-to-high-resolution time-interleaving SAR ADCs.
Manuscript received February 17, 2015; revised May 15, 2015; accepted July
30, 2015. This paper was approved by Guest Editor Stefan Rusu. Several energy-efficient switching methods [10], [11] have
The authors are with MediaTek, Hsinchu Science Park, Hsinchu, Taiwan, been proposed to lower the switching energy of the capacitor
R.O.C. (e-mail: jason.liu@mediatek.com).
network. The other techniques, like multibit/step [12], [13],
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. pipelined-SAR [14]–[16], etc., also improve the sampling rate
Digital Object Identifier 10.1109/JSSC.2015.2466475 or reduce the power consumption of pipelined ADC. Recently,

0018-9200 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015

Fig. 2. Architecture of a conventional SAR ADC.

the conversion rate of single-channel SAR ADCs has achieved

more than 100 MS/s with the resolutions from 10 to 14 bit
[17]–[20]. The SAR ADCs also have the feature of low-power
and low-cost that makes it more attractive than the other ADC
architectures for the high-speed WLAN systems, especially for
those embedded in mobile devices.
This paper presents a binary-scaled recombination capacitor Fig. 3. Conventional binary search: (a) correct conversion; (b) wrong conver-
sion.
weighting method for SAR ADC [21]. With the proposed ca-
pacitor partition algorithm, the reference buffer requirement is
relaxed greatly. The prototype ADC achieves a conversion rate
of 320 MS/s and an effective resolution bandwidth (ERBW) until the final bit is obtained. If all bit cycling operations are cor-
more than 100-MHz while consumes 1.52-mW dynamic power rect, we can get a correct digital output code. In this case, the
from 1.0-V supply and 0.9-V reference voltage, and only digital output code is equal to 4.
occupies an active area of m m in a 20-nm CMOS If a wrong decision is made before the last cycle as shown
technology. The remaining part of this paper is organized as in Fig. 3(b), even if the remaining decisions and their corre-
follows: Section II describes the comparison of redundant sponding DAC switching are correct, the difference between
weighting methods for SAR ADC. Section III presents the im- the input and reference in the last cycle is still larger than one
plementation of proposed SAR ADC and key building blocks. LSB, resulting in performance degradation. To make sure the
Section IV shows the measurement results of the prototype conversion is correct, the DAC setting error must be less than
ADC and the comparison to the state-of-the-art works. Conclu- 0.5-LSB in each bit-cycling. It takes a long time for MSB capac-
sions are given in Section V. itors and reference voltage to stabilize. Otherwise, the nonset-
tled DAC may result in wrong decisions and degrade the ADC
performance. The long settling time limits the conversion rate
II. REDUNDANT WEIGHTING METHODS FOR SAR ADC
of SAR ADCs especially in high resolution cases. To improve
Fig. 2 shows the block diagram of a conventional SAR the settling speed, the binary SAR ADC needs a power hungry
ADC, which includes a sample and hold (S/H) circuit, a on-chip reference buffer to fast settling of reference voltage, or
comparator, a SAR logic and a digital-to-analog convertor directly uses external reference voltages [10], [11]. However,
(DAC). A SAR ADC requires several comparison cycles to the SAR ADC consumes pretty large dynamic current. It needs
complete one conversion. Therefore, it needs a S/H circuit to large decoupling capacitors to minimize the variation on refer-
hold the input signal. The comparator compare the sampled ence voltage. In the nanometer scaled CMOS process, the area
input signal with the DAC reference voltage, then the output of on-chip decoupling capacitors is usually much larger than
of comparator triggers the SAR logic operation. According to the core area of SAR ADCs. To avoid a strong reference buffer
the SAR logic, the DAC changes the output voltage. Then, the or large area on-chip decoupling capacitors, some redundant
comparator performs comparison again. The SAR ADC repeats weighting methods [6], [7] for the SAR ADC are proposed to
these procedures until the final bit is obtained. For a correct speed up conversion by increasing extra bit-cycles to alleviate
conversion, the difference between the analog signal and digital the DAC and reference settling requirement during bit-cycling.
presentation should be less than 1 LSB. If the difference is
larger than 1 LSB, that means there are some errors happened A. Nonbinary Weighting Method
during the conversion.
Fig. 3(a) shows an example of binary search SAR ADC. This In the nonbinary SAR ADCs [6], the effective input range
is a 4 bit case. Hence, it has sixteen quantization levels. The is reduced by a factor smaller than 2 in each bit-cycle.
is the input signal and the bold line is the threshold. The com- Fig. 4(a) shows the concept of nonbinary search algorithm.
parator distinguishes the input signal is higher or lower than the This is also a 4 bit case. The effective input range is reduced by
threshold and generates one bit digital code. In the first bit cycle, a factor small than 2 after each bit cycles. For example, after
the input signal is lower the threshold. Therefore, the first bit is the first bit cycles, the number of possible quantization levels
0. After the first bit is decided, the number of possible quanti- is reduced from 16 to 9. Fig. 4(b) shows a wrong decision
zation levels is reduced from 16 to 8. That means the effective happened during the conversion. If the remaining bit cycling
input range is reduced by a fact of 2. The conversion will repeat operations are all correct, it is possible to get a correct digital
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LIU et al.: 10 BIT 320 MS/S LOW-COST SAR ADC FOR IEEE 802.11AC APPLICATIONS IN 20 NM CMOS 3

Fig. 5. Binary-scaled compensation: (a) correct conversion; (b) conversion

Fig. 4. Nonbinary search: (a) correct conversion; (b) conversion with wrong with wrong decision.
decision.

C. Proposed Binary-Scaled Recombination Weighting Method

output code at the cost of extra bit cycles. In this 4 bit example, For an bit redundant SAR ADC, it needs bit cycles
it needs 5 bit cycles to complete the conversion. to convert an bit digital code. The DAC capacitor
The nonbinary SAR ADC generates more decision levels array comprises capacitors, ( to descending in
than a conventional one. There are several digital codes rep- size, is a termination capacitor with the same size of a unit
resenting the same input voltage, meaning different switching capacitor). The total capacitance to is defined as ,
procedures can lead to the same result. Hence, a certain range and is the reference voltage. The maximum tolerable settling
of error does not have influence on the conversion result. error range during switching the capacitor can be expressed
Comparator can do comparison before the DAC and reference as
voltage is well settled. Hence, the bit-cycling time can be
reduced. Even the no-binary SAR ADC needs extra bit cycles, (1)
the total conversion time still can be improved.
However, the nonbinary architecture needs extra hardware,
including control circuits, a ROM to store the bit weightings and Therefore, each capacitance in a redundant SAR ADC must
an arithmetical unit to calculate the sum. Moreover, the nonbi- satisfy
nary scaled bit weighting is not favored for layout matching,
(2)
which may limit the linearity of the DAC network.
According to the redundancy principle, we proposed a binary-
B. Binary-Scaled Compensation Weighting Method scaled recombination weighting method without adding extra
compensative capacitors and with less circuit overhead than the
In the binary-scaled error compensation SAR ADC [7], previous techniques. For an bit proposed SAR ADC, the
some binary-scaled capacitors are inserted in the original capacitors in DAC array are composed of only capacitor
binary DAC network to provide compensative voltage values. cells. To make the MSB capacitor has a certain range of
Fig. 5(a) shows the concept of the binary-scaled error com- redundant margin, the MSB capacitor only includes
pensation algorithm. Like the binary search, the effective input capacitor cells, which is less than half of .
range is reduced by a factor of 2. But in some bit cycles, The capacitor cells removed from the MSB capacitor
the input range does not reduce but shift to compensate for are distributed into groups. In each of the
some errors. With the extra compensative bit cycles, there are groups, the number of capacitor cells is a power-of-2 number.
multiple digital presentations for an input voltage. Different The groups are selectively allocated to different capacitors
output codes can lead to the same result. Even a wrong decision among to . Therefore, , one of the capacitors from
happened during the conversion, as shown in Fig. 5(b). It is to , has either or capacitor cells,
still possible to get a correct digital output code. where , and must satisfy (2).
This is a simpler way to overcome the DAC settling issues Take a 10 bit case, for example. There are quantization
with less design and hardware overhand. Only the compensative levels for the proposed weighting method to arrange. The MSB
capacitors and the digital error correction logic added to per- capacitor with half of the total bit weights is split into two
form the compensation function and compute the binary output groups, and . Next, cells are split
codes. However, the extra compensative capacitors increases into , , , , , , and ,
the sampling capacitance and results in a smaller input range. respectively. Those weights are added to the LSBs groups. The
The mismatch between the compensative capacitors and the cor- new weighting ratio of to are , ,
responding digital value also degrades the linearity of the ADC. , , , , ,
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015

TABLE II With the redundancy, the noise requirement of the comparator

COMPARISON OF REDUNDANT METHODS in the proposed SAR ADC can be relaxed in the MSBs bit-
cycling. Exclude the settling issues of reference buffer and DAC
circuit, the maximum noise relaxed range for each bit-cycling
is about quarter (for 4 sigma variation) of redundant range in
Table II. Similar to the ADC in [4], the proposed SAR ADC still
needs a low-noise comparator in the last few LSBs bit-cycling
to achieve sufficient SNR. To simplify the design and avoid the
offset problem between coarse and fine comparator, we only use
one low-noise comparator in this SAR ADC implementation.
The proposed technique also relaxes the settling requirement
of reference buffer and DAC circuit. It reduces the power con-
sumption of reference buffer and improves the operation speed
of SAR ADC. However, the requirement of capacitor mismatch
in CDAC cannot be moderated, because the mismatch between
, , and , real and ideal capacitance value of each unit capacitor cell is not
respectively. This example takes 11 bit-cycles to convert 10 bits. changed with the proposed technique.
The digital output can be expressed as

III. IMPLEMENTATION OF PROPOSED SAR ADC AND

BUILDING BLOCKS
Fig. 6 shows the architecture of the proposed SAR ADC,
which consists of a comparator, two bootstrapped switches, two
capacitor arrays, SAR control logic and digital error correction
logic (DEC). Similar to a monotonic switching SAR ADC [10],
Take another case as an example. It takes 12 bit-cycles to
the ADC sampled input signal on the top plates of capacitor ar-
convert 10 bits. The MSB capacitor is split into
rays. Therefore, the 10 bit ADC only needs capacitor cells
and . Next, cells are split into , , ,
in each capacitor array. The bottom plates of the capacitor cells
, , , , and , respectively. Those
are either connected to reference voltage or ground. A CMOS
weights are added to the LSBs groups. The new weighting ratio
inverter can perform the DAC switching with very simple con-
of to are , , , ,
trol logic. This ADC adds two extra redundant bit-cycles to
, , , ,
alleviate the DAC settling problem and speed up the conver-
, , and , respectively. The digital
sion. The capacitor cells will be arranged into 11 capacitor
output can be expressed as
groups to with the proposed binary-scaled recombina-
tion weighting method. Fig. 7 shows how to weight the 11 ca-
pacitor groups. The MSB capacitor group is split into
two groups, and . Next, is split
into , , , , , , and .
Those groups are added to the LSBs capacitor groups. The new
capacitor weighting ratios are , , ,
, , , , ,
In the proposed redundant method, the MSB weights can be , and . The effective bit weights of
expressed as a difference of two power-of-2 numbers the 12 bits are 480, 256, 128, 72, 40, 20, 12, 6, 4, 2, 2, 1. The
. Except the MSB weights, the other bit weights can be ex- digital output can be expressed as
pressed as a sum of two or only one power-of-2 numbers. The
method doesn't need extra compensative capacitors and the dig-
ital error correction logic is very simple to realize.
Table II shows the comparison of redundant range with dif-
ferent redundant methods. The arrangement of redundancy is
more flexible with the proposed binary-scaled recombination
algorithm. We can design the number of bit-cycling and the re-
dundant range for each bit cycling and according to the refer-
ence buffer and DAC settling. The redundant ranges of the two
A. S/H Circuit
examples of the proposed methods are smaller than the previous
cases. This is because the redundant range of MSB is sufficient The proposed SAR ADC samples the input signal via the
for our circuit implementation. To get a larger redundant range, bootstrapped switches at the top plates of capacitors. When the
we can remove more bit weight from MSB weighting, and add bootstrapped switch is turned off and the SAR ADC is in bit-
the reduced weightings to the other LSB weightings. cycling, the signal couples to the sampling capacitors through
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LIU et al.: 10 BIT 320 MS/S LOW-COST SAR ADC FOR IEEE 802.11AC APPLICATIONS IN 20 NM CMOS 5

Fig. 6. Architecture of proposed SAR ADC.

Fig. 8. Bootstrapped switch with a dummy.

Fig. 7. Capacitor array weighting used in the SAR ADC.

the metal routing parasitic capacitor and the drain-source ca-

pacitor of the sampling transistor . The coupling ef-
fect degrades the ADC performance. The work [10] utilizes
a cross-coupled metal-oxide-metal (MOM) capacitor to neu-
tralize the effect. However, with process variation, the coupling
effect could not be totally cancelled. In this works, an iden-
tical dummy transistor is added to the bootstrapped switch
as shown in Fig. 8. The dummy switch is always off, and the
drain and source of the dummy switch are connected to the op-
posite input signal and the sampling capacitor arrays, respec-
tively. In Fig. 9(a), without this dummy switch, any variation of
input signal will directly coupled to the sampling capacitor ar-
rays. The variation on the single side sampling capacitor arrays Fig. 9. Coupling effect: (a) without a dummy transistor; (b) with a dummy
transistor.
will disturb the ADC bit-cycling. In Fig. 9(b), with the identical
dummy switch, any variation of input signal will be coupled
to dual sampling capacitor arrays. The coupling effect will be
eliminated mutually and has no influence on the SAR conver-
sion result in this differential ADC.
We run a transient simulation of the S/H circuit to demon-
strate the effective of the dummy switch. Assume that the metal
parasitic capacitance between the drain and the source of sam-
pling transistor is 0.5 fF. When the sampling switch turned on,
the input is connected to a 3.2 MHz signal source. After the sam-
pling switch turned off, the input frequency changed to 75 MHz.
Fig. 10 shows the FFT spectrum of simulation results with and
without the dummy switch. With the dummy switch, the inter-
ference frequency has not influence to the result. Without the
Fig. 10. FFT spectrum of simulation results with and without the dummy
dummy switch, the interference frequency of 75 MHz appears in switch.
the spectrum and decreases the SNDR from 68.8 dB to 55.0 dB.
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015

Fig. 11. Schematic of a dynamic two-stage comparator.

B. Dynamic Two-Stage Comparator

A high-speed, low-power and low-noise comparator is cru-
cial for the SAR ADC. To satisfy those considerations, a dy-
namic two-stage comparator composed of a dynamic pream-
plifier stage [22] and a dynamic latch is used in this proto-
type ADC. The detail schematic of the dynamic two-stage com-
parator is shown in Fig. 11. To work properly with a gradually
decreasing common-voltage, the pre-amplifier utilizes a p-type
input pair. When Clkc is high, the pre-amplifier outputs
and are reset to ground. When Clkc goes to low,
and are charged from low to high dependent on the input
voltages and . The pre-amplifier transfers the differ-
ence of two voltage signals into a difference of timing. The
dynamic latch performs a timing comparator and generates a
digital output according which input signal goes high first. The
comparator does not consume any static power. Hence, it is very
energy efficient.

C. Capacitor Array
The DAC capacitor array occupies most of the area, usually
more than 50% of the whole ADC. The layout of the capacitor
array becomes critical to reduce the area of ADC. Fig. 12 shows
two metal-oxide-metal (MOM) capacitor cell structures. The
structure in Fig. 12(a) has some similarities with the capacitor
cell in [10]. The top plate of the capacitor cell is enclosed by
bottom plate to reduce the parasitic of top plate. However, the
parasitic capacitor between each bottom plate increases to the
switch buffers. The space between each unit cell also occupies
extra area. Fig. 12(b) shows the proposed capacitor cell. The
bottom plate of the capacitor cell is enclosed by the top plate,
and the top plates of all capacitor cells are combined together.
Therefore, the capacitor array is very compact and has smaller Fig. 12. Structure of capacitor array: (a) top plate encolsed by bottom plate;
area and gradient effect, that resulting in better matching. We (b) bottom plate enclosed by top plate.
can use a smaller capacitance to achieve 10 bit linearity. When
the capacitance reduced, the DAC switch size can also be re-
duced for the same settling time. E. Standard Library Based Design
D. Digital Error Correction Logic Many sub-circuits in the proposed SAR ADC are digital, in-
The digital error correction logic converts the 12 bit redun- cludes comparator cycling timing loop logic, SAR control logic,
dant codes into 10 bit binary codes. Fig. 13 shows the logic im- digital error correction logic and DAC switches. In advance
plementation of digital error correction circuit, which consists of CMOS technology, many dummy devices are added to ensure
10 full adders, 10 D-type flip-flops (DFFs) and 2 multiplexers. the device property in full custom design and layout. The extra
When the skip_sel is set to high, the last bit-cycling operation is dummy cells result in extra area overhead, larger routing resis-
skipped and the total number of bit-cycles is reduced to 11. The tance and parasitic capacitance to main devices. The digital stan-
conversion time is improved at the cost of missing two quanti- dard library logic cells provided by foundry have verified device
zation levels. properties, regular and compact layout size. Therefore, we use
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LIU et al.: 10 BIT 320 MS/S LOW-COST SAR ADC FOR IEEE 802.11AC APPLICATIONS IN 20 NM CMOS 7

Fig. 13. Implementation of digital error correction logic.

the digital standard logic cells to construct the digital sub-cir-

cuits in the proposed ADC. With the standard cell, we can run
prelayout simulation with detail layout parasitic. The parasitic
effect in those digital sub-circuits can be taken into consider-
ation during prelayout design and simulation. That can reduce
a lot of iterations between layout modification and postlayout
simulation. Moreover, with the standard cell based design, the
layout of each standard cell is already available. Those digital
sub-blocks also can use CAD tool for auto-routing. Hence, the
layout effort is relaxed very much. Therefore, the develop time
and cost are reduced greatly.

F. Reference Generator
For a traditional binary SAR ADC with 10 bit resolution and
hundreds of MHz sampling rate, the reference buffer and capac-
itor DAC network must settled in few tens of pico-seconds. It
needs a reference buffer with several tens GHz bandwidth. The Fig. 14. Implementation of reference buffer.
current consumption of the wide bandwidth buffer may dissi-
pate few tens mA, which is much higher than the current con-
sumption of SAR ADC. The power hungry reference buffer re-
duces the low-power attractiveness of SAR ADC. With the help
of the proposed binary-scaled recombination redundant algo-
rithm, the bandwidth requirement of reference buffer is relaxed
greatly.
Fig. 14 shows the schematic of reference buffer adopted for
the proposed SAR ADC. A A static current through a k
resistance generates a 0.9 V voltage. The transistors and
mirror 12 times current from , and the currents through two
k resistances generates a pair of 0.9 V reference voltage for
I/Q channel ADCs. The open-loop topology has the benefit of
small output impedance, wide bandwidth, low noise, and small
area. It is very suitable for such high resolution and high speed
ADC.

IV. MEASUREMENT RESULTS

The prototype ADC is fabricated in a 1P8M 20-nm CMOS
technology. Fig. 15 shows the chip micrograph and the layout Fig. 15. Chip micrograph and layout zoomed-in view of the SAR ADC core.
zoomed-in view of the ADC core which only occupies an ac-
tive area of m m. Different from the other works
[10], [11] achieving almost rail-to-rail input range to improve about 300 fF and the capacitance of dummies and parasitic is
SNR. The prototype ADC adopts only input swing due 240 fF.
to the limited linear range of the on-chip front-end circuits. The At 160 MS/s sampling rate mode, the supply voltage is
supply (0.9-V to 1-V) and reference voltage (0.9-V) of the SAR set to 0.9-V to save power, and the sampling time is 50%
ADC are provided by an internal LDO and a reference generator duty of clock cycle. The dynamic power consumption in the
(consuming only 0.36 mA static current). The total sampling ca- condition is 0.68 mW (S/H and comparator 67%, SAR control
pacitance is 540 fF where the capacitance in the main DAC is logic 23%, DAC reference 7%, and DEC 3%). Most power is
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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015

Fig. 16. Measured performance versus input frequency at 0.9 V and 160 MS/s.
Fig. 18. FFT plot with 19.9-MHz input frequency at 320 MS/s.

Fig. 17. Measured performance versus input frequency at 1.0 V and 320 MS/s.

dissipated in the comparator to improve SNR. Fig. 16 plots the

measured SNDR and SFDR values versus the input frequency Fig. 19. Measured DNL and INL.
at 160 MS/s. At low input frequency, the measured SNDR
and SFDR are 57.7 dB and 78.9 dB, respectively. The resul-
tant ENOB is 9.29 bits. When the input frequency increases TABLE III
SUMMARY OF PERFORMANCE
to Nyquist frequency, the measured SNDR and SFDR were
57.1 dB and 77.1 dB, respectively. The effective resolution
bandwidth (ERBW) is higher than 160 MHz. According to
Walden FoM equation

(3)

The resultant FoMs are 6.8 and 7.3 fJ/conversion-step at low

and Nyquist frequency, respectively.
To achieve 320 MS/s sampling rate with a 1 V supply, the th
bit-cycle of SAR conversion is skipped to extend sampling time.
The sampling time is about 40% of clock cycle in this condition,
and the power consumption is 1.52 mW. Fig. 17 plots the mea-
sured SNDR and SFDR values versus the input frequency at 320
MS/s. At low input frequency, the measured SNDR and SFDR is limited by the resistance in ADC test path (includes the ESD
are 57.1 dB and 78.1 dB, respectively. The resultant ENOB protection resistor, routing resistor and switch on-resistor, total
is 9.20 bits. When the input frequency increases to Nyquist about according to postlayout extraction), which slows
frequency, the measured SNDR and SFDR were 50.9 dB and down the slewing during ADC sampling. Fig. 18 shows the
58.6 dB, respectively. The ERBW is higher than 100 MHz. FFT plot at 19.9-MHz input and 320 MS/s sampling frequency.
The resultant FoMs are 8.1 and 16.5 fJ/conversion step at low The measured SNDR, SFDR, THD are 56.8 dB, 74.8 dB and
and Nyquist frequency, respectively. The sampling bandwidth dB, respectively.
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LIU et al.: 10 BIT 320 MS/S LOW-COST SAR ADC FOR IEEE 802.11AC APPLICATIONS IN 20 NM CMOS 9

TABLE IV
COMPARISON TO STATE-OF-THE-ART WORKS

Fig. 19 shows the measured static performance at 160 MS/s. [5] J.-H. Tsai, Y.-J. Chen, M.-H. Shen, and P.-C. Huang, “A 1-V, 8 b,
The DNL is within LSB and the INL is within 40 MS/s, W charge-recycling SAR ADC with a W asyn-
chronous controller,” in Symp. VLSI Circuits Dig. Tech. Papers, 2011,
LSB. A summary of the ADC performance is pp. 264–265.
listed in Table III.Table IV compares the proposed ADC with the [6] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approx-
state-of the-art ADCs. With similar conversion rate and resolu- imation ADC in 0.13- m CMOS,” in IEEE ISSCC Dig. Tech. Papers,
2002, pp. 176–177.
tion, the proposed SAR achieves similar FOM with only [7] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, and C. H.
input signal swing and 10 X smaller area compared to those Huang, “A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error
works. The prototype ADC is the fast and smallest 10 bit non- compensation,” in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 386–387.
[8] W. Liu, Y. Chang, S. K. Hsien, B. W. Chen, Y. P. Lee, W. T. Chen,
interleaving SAR ADC so far. T. Y. Yang, G. K. Ma, and Y. Chiu, “A 600 MS/s 30 mW m
CMOS ADC array achieving over 60 dB SFDR with adaptive digital
V. CONCLUSION equalization,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 82–83.
[9] L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli,
In this paper, a binary-scaled recombination redundant algo- M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, “A 90 GS/s 8
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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 11, NOVEMBER 2015

[21] C. C. Liu, “A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802. Che-Hsun Kuo was born in Tainan, Taiwan, R.O.C.,
11ac applications in 20-nm CMOS,” in Proc. IEEE A-SSCC, 2014, pp. in 1990. He received the B.S. and M.S. degrees in
77–80. electrical engineering from National Cheng Kung
[22] M. V. Elzakker, E. Tuijl, P. Geraedts, D. Schinkel, E. A. M. University, Tainan, Taiwan, in 2012 and 2014,
Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC respectively.
consuming W at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, He is currently an engineer with MediaTek,
no. 5, pp. 1007–1015, May 2010. Hsinchu, Taiwan, working on high-performance
[23] M. Miyahara, H. Lee, D. Paik, and A. Matsuzawa, “A 10 b 320 MS/s front-end analog circuits. His research interests
40 mW open-loop interpolated pipeline ADC,” in Symp. VLSI Circuits include the high-speed, low-power ADCs and other
Dig. Tech. Papers, 2011, pp. 126–127. analog and mixed-signal circuits and systems.
Mr. Kuo was the winner of the Gold Prize of the
Macronix Golden Silicon Award and the recipient of the Best Design Awards
of the National Chip Implementation Center (CIC) Outstanding Chip Award in
2015.

Ying-Zu Lin (S'06–M'11) received the B.S. and M.S.

degrees in electrical engineering and the Ph.D. de-
gree from National Cheng Kung University, Taiwan,
R.O.C., in 2003, 2005, and 2010, respectively.
From 2010 to 2013, He was with Novatek,
Chun-Cheng Liu (S'07–M'11) received the B.S. Hsinchu, Taiwan, as a senior engineer working on
and Ph.D. degrees in electrical engineering from the analog circuits for advanced display systems. He is
National Cheng Kung University (NCKU), Taiwan, currently with MediaTek, Hsinchu, as a technical
R.O.C., in 2005 and 2010, respectively. manager working on data converters and analog
In 2011, he joined MediaTek, Hsinchu, Taiwan, circuit for wireless communication systems. His re-
where he has been working on analog-to-digital search interests include analog/mixed-signal circuits
converters for video receivers and wireless com- and data converters.
munication systems. Currently, he is a technical Dr. Lin won the Excellent Award in the thesis contest of the Mixed-Signal
manager working on high-performance data con- and RF Consortium, Taiwan, in 2005. In 2008, he won the Best Paper Award
verters and analog circuits. His main research of VLSI Design/CAD Symposium, Taiwan, and the TSMC Outstanding Stu-
interests include analog/mixed-signal circuits and dent Research Award. In 2009, he won the Third Prize in the Acer Long-Term
analog-to-digital converters. Smile Award and was the recipient of the MediaTek Fellowship. In 2010, he
Dr. Liu won the 2007 Third Prize and 2008 First Prize in the IC design con- received the Best Paper Award from the IEICE and the Best Ph.D. Award from
tests (Analog Circuit Category) held by the Ministry of Education, Taiwan. In the IEEE Tainan Section. He was also the corecipient of the Gold Award in the
2010, he was the winner of the Gold Prize in Macronix Golden Silicon Award Macronix Golden Silicon Design Contests 2010. In 2011, he was the winner of
and the Best Ph.D. Dissertation Award of the Taiwan IC Design Society. He also ISSCC/DAC Student Design Contest and the recipient of the CIC Outstanding
received the Best Design Awards of the National Chip Implementation Center Chip Design Award (Best Design) and the Silver Award of the ISIC Chip De-
(CIC) Outstanding Chip Award in 2010 and 2011. sign Competition.