IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO.

6, JUNE 2010 1111

A 10-bit 100-MS/s Reference-Free SAR ADC

in 90 nm CMOS
Yan Zhu, Student Member, IEEE, Chi-Hang Chan, U-Fat Chio, Student Member, IEEE,
Sai-Weng Sin, Member, IEEE, Seng-Pan U, Senior Member, IEEE, Rui Paulo Martins, Fellow, IEEE, and
Franco Maloberti, Fellow, IEEE

Abstract—A 1.2 V 10-bit 100 MS/s Successive Approximation increase of the transconductance. Recent works [5]–[9] opti-
(SA) ADC is presented. The scheme achieves high-speed and mize the power design of pipeline ADCs but the figure of merit
low-power operation thanks to the reference-free technique that
(FoM) remains in the hundred of fJ/conv-step range.
avoids the static power dissipation of an on-chip reference gener-
ator. Moreover, the use of a common-mode based charge recovery The pipeline architecture does not benefit from the tech-
switching method reduces the switching energy and improves nology scaling because the use of low voltage supplies gives
the conversion linearity. A variable self-timed loop optimizes the rise to an augmented consumption of power. In contrast, the
reset time of the preamplifier to improve the conversion speed.
scaling of technology does not penalize much the SAR ADC
Measurement results on a 90 nm CMOS prototype operated at
1.2 V supply show 3 mW total power consumption with a peak architecture because its analog part is simply made by a com-
SNDR of 56.6 dB and a FOM of 77 fJ/conv-step. parator and a capacitive DAC array. Indeed, the FoM values of
Index Terms—Charge-recovery, reference-free, switched tech- state-of-art SAR ADCs [10]–[12] are well lower than those of
nique. pipelines and the best FoM in record is an SAR ADC [13]. The
FoM of a SAR converter that improves with thinner line-widths
is now in the range of tens of fJ/conv-step. However, for 65 and
I. INTRODUCTION 90 nm technologies, the conversion rate is still low, not more
than 50 MS/s.
OW POWER is the most relevant design concern for
L battery-powered mobile applications, such as DVB-T,
DVB-H and TDMB [1]. Since the ADCs operate at tens of
The speed of a SAR ADC is determined by the time required
by the DAC to settle within 1/2-LSB. With large number of bits
and capacitive arrays, the main cause of power consumption is
MS/s with 10 b to 12 b, the pipeline ADC is the commonly used the reference generator that must provide very low output re-
architecture because of its power efficiency [2]–[4]. However, sistance. A second important source of consumed power is the
recently, the successive approximation register (SAR) architec- dynamic power of the DAC. Previous works [12]–[14] improve
ture has re-emerged as a valuable alternative to the pipelined the conversion efficiency by saving part of the switching energy
solution. during each bit cycling. However, the spared energy is a small
The conventional pipeline topology uses op-amps and fraction of the total power dissipated by the reference voltage
switched capacitor structures to generate the residual. More- generator, especially at high conversion speed [15]. Therefore,
over, the internal flash uses comparators (n is the number the power efficiency improves if the power needed by the ref-
of bits of the stage). All these blocks burn up power. Moreover, erence generator is not accounted for [9], [16], [17]. When this
the reduction of supply voltage, as requested by sub-100 nm power is included the FoM drops significantly.
technologies, increases the consumed power because the This design obtains remarkable power effectiveness for
reduced quantization step amplitude imposes an equivalent medium resolution and high conversion speed by using two
strategies: the first avoids the reference generator by directly
Manuscript received December 14, 2009; revised February 28, 2010; ac- using the supply voltages; the second saves the switching
cepted March 24, 2010. Current version published June 09, 2010. This paper energy during the SA conversion. The use of the supply voltage
was approved by Associate Editor Lucien Breems. This work was supported by
Research Grants from University of Macau and Macao Science and Technology as the reference of the ADC would lead to a signal swing of
Development Fund (FDCT). the converter that is wider than the typical signal range; this
Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin and S.-P. U are with Analog
and Mixed Signal VLSI Laboratory and Faculty of Science and Technology, would reduce the effective SNR. This drawback is removed
University of Macau, Macao, China (e-mail: yanjulia@ieee.org; http://www. with the proposed technique that grants a passive gain by 2
fst.umac.mo/en/lab/ans_vlsi/). of the input. A doubling of the LSB, that relaxes the limits of
R. P. Martins is with Analog and Mixed Signal VLSI Laboratory and
Faculty of Science and Technology, University of Macau, Macao, China. He noise and offset, also lowers the power consumption of the
is on leave from Instituto Superior Técnico/TU of Lisbon, Portugal (e-mail: comparator. In addition, it is worth to notice that a multiplica-
RMartins@umac.mo).
F. Maloberti is with the Electronic Department, University of Pavia, Italy, tion by 2 enables an input signal that is half the rail-to-rail and
and also with the University of Macau, Macao, China (e-mail: franco.mal- not the full rail-to-rail as is presented in [12], [13], [18], [19].
oberti@unipv.it) Having an input range of the converter well within the supply
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. limit is suitable for signals generated on-chip. This is very
Digital Object Identifier 10.1109/JSSC.2010.2048498 common because the input of an ADC is the result of on-chip
0018-9200/$26.00 © 2010 IEEE
1112 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010

Fig. 1. Overall schematic diagram of the ADC architecture.

pre-conditioning, like amplification or filtering, obtained with

op-amps whose signal swing represents headroom from the
supply limits.
Fig. 2. Conceptual scheme that obtains a passive gain by 2.
The switching energy saving technique, described in detail
below, avoids the mismatch error at the conventional most sig-
nificant bit (MSB) transition and enables a reduction by 2 of
A. Passive Multiplication by 2
the overall capacitance used in the SAR. The charge recovery,
implemented during each bit cycling, cuts by 1/3 the switching A well-known feature of many SAR architectures is their
energy with respect to the one achieved in [12]. In addition, the insensitivity to parasitic capacitances. With conventional ap-
used switching approach improves the conversion linearity that proaches the input of the comparator is at the reference voltage
typically affects a conventional SAR ADC. in the beginning of the conversion cycle and draws near the ref-
Instead of using the asynchronous processing [16] this paper erence at the end of the conversion. As a result, the charge of the
avoids the fast clock by implementing a variable self-timed loop parasitic capacitance is almost the same at the beginning and the
that adjusts the plus width of the preamplifier to reduce the ideal end of the conversion cycle. The schemes that are sensitive to
time for the LSBs conversions. parasitic experience a gain error and a linearity error. Obviously,
the gain error due to the top-plate parasitic of DAC is not very
important as it corresponds to an error of the voltage reference.
II. ADC ARCHITECTURE
More relevant is the non-linearity of the preamplifier input par-
Fig. 1 shows the architecture of the proposed 10-bit SAR asitic: the variation of the gate voltage may degrade the integral
ADC. It comprises differential capacitor networks, a dynamic nonlinearity (INL). However, this parasitic nonlinearity effect is
comparator and the SA control logic. The differential capacitor irrelevant: the parasitic of the preamplifier input is quite small
networks are composed by 10-bit split schemes with the addi- when compared with the total capacitance of the DAC array.
tional sampling capacitors necessary for the passive multi- Therefore, the SAR ADC is, in practice, insensitive to the par-
plication by 2. The SA logic controls asitic effects of both the DAC array and preamplifier. Conse-
for bringing it toward . In the quently, for medium resolutions, parasitic insensitivity can be
comparator, the 4 inputs preamplifier and the dynamic latch traded with other more valuable features. This design trades the
determine the value of each bit. The SA control logic includes parasitic insensitivity with the passive amplification by 2.
shift registers, bit registers and a switching logic block, which The conceptual scheme of Fig. 2 illustrates the method.
control the DAC operation to perform the binary-scaled feed- During the sampling phase the binary-weighted capacitive
back during the successive approximation cycle. The frequency DAC samples the input, like in a conventional scheme, while
of the clock used by the SA block is the ADC sampling fre- samples the complementary input. During the conversion
quency. No fast clock at the input is needed because the SA phase shifts the voltage of the reference node to ,
uses the self-timed technique. All the SA control signals re- making equal to the signal that the SAR algorithm must
sult from a proper use of internal delay lines and their logic compensate for.
combination. The conventional SAR algorithm drives the DAC to finally
As mentioned in the introduction, the scheme presented in converge to the common mode voltage at the end of the
the next sub-section obtains as a great benefit the equivalent bit-cycling, according to
multiplication by two of the input. This permits the reference
free operation and enhances the profit of charge recovery, thus
(1)
reducing power consumption.
ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS 1113

Fig. 3. The Vcm -based switching timing diagram with its n-bit split capacitive DAC array (n = i + j).

on the contrary, the proposed method drives the DAC to con- B. -Based Switching Method
verge toward instead of Switching the capacitive array consumes significant power.
In order to reduce this term the value of the unit capacitance
must be brought down to the limit allowed by the technology
(2) and the noise. Moreover, the use of the split capacitive
array, that substitutes the full binary-weighted array, helps in
the power reduction because the method reduces the total capac-
(3) itance of the arrays. Further energy saving is obtained with ef-
fective switching approaches [12]–[14], [20], [21]. One of them,
the set-and-down method recently proposed [12], saves signif-
In the above equations (1 or 0) is the ADC decision for icant switching energy thanks to its halving of the overall ca-
bit n and , represents the capacitors connected to pacitance. The method used here, named -based switching
the reference voltage and the total array capacitance. approach, also obtains a half-capacitance reduction. In addition,
Moreover, (3) certifies that the proposed operation corresponds as shown below, the switching sequence reduces the energy by
to a passive amplification by 2 of the input. Furthermore, the an additional 1/3 with respect to the set-and-down technique.
proposed technique uses a reference voltage, , that is The -based switching approach determines the sign of
twice , as used in the conventional counterpart. This is a the differential input (MSB) by connecting the differential ar-
key feature for the use of the supply voltage as reference. With rays to . The power dissipation is just derived from what is
identical to the supply voltage, the signal swing needed to drive the bottom-plate parasitic of the capacitive ar-
is 0.3–0.9 V with , a value that allows the ADC to rays, while in the conventional charge-redistribution [13], [22]
use signals generated by on-system stages biased by the supply and the charge-recycling [14] methods the necessary MSB “up”
voltage. transition costs significant switching energy and settling time.
The sampling capacitor serves to hold the input signal for Moreover, the MSB capacitor, being not required anymore, can
the SA conversion, consequently no specific matching condition be removed from the n-bit DAC array. Therefore, the next
is required between and the DAC array. However, must estimation is done with an bit array instead of its
be large enough to comply with the noise constraint. n-bit counterpart, leading to half capacitance with respect to the
In addition to the supply voltages this architecture uses the conventional and charge-recycling methods.
common mode voltage to pre-charge the capacitors. However, Fig. 3 details the -based switching algorithm. In the
since the processing is fully-differential, no charge flows global sampling phase , is stored in the capacitor array.
through the common mode terminal, unless there is a mismatch During the resting phase , all the capacitors’ bottom-plates
between the used common mode and the one of the input signal. are switched to the common-mode voltage, resulting in the
Assuming that the mismatch is less than 10%, the common equivalent output voltage at the output. The value of
mode generator must provide a limited charge: 10 times smaller determines the MSB during as the logic properly
than what is required to references used in conventional SAR controls . If , goes to while the
converters. Therefore, the output resistance of the common other switches remain connected to . The
mode generator and its power needs are significantly relaxed. result is that the voltage at [2] becomes .
1114 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010

Fig. 4. A 3-bit example of set-and-down and proposed Vcm -based switching procedures.

If , is switched to , raising the voltage at set-and-down methods. From [12] when the supply is directly
[2] to . The cycle is repeated for times. used as the reference voltage, a rail-to-rail input signal is
The scheme of Fig. 3 and the above description are for a single required. Fig. 4 illustrates the case where the input signal of the
ended operation. In reality, the fully differential operation makes two methods is in both rail-to-rail. Accordingly, the reference
the algorithm insensitive to the input common mode, . voltage and the common-mode voltage in the two
The difference between the common mode input and deter- approaches are equal to and , respectively. The
mines equal shifts of the output of the array of switching energy needed for the first bit comparison is just what
Fig. 3. These shifts, assumed within the limits of the comparator is necessary for driving the bottom-plate parasitics of the DAC
common mode range, are rejected being a common mode com- arrays. Since the -based method charges the parasitic to
ponent. Moreover, the -based switching method foresees half of the reference voltage, while the set-and-down uses the
“up” or “down” transitions after the comparator determines the full reference, the consumed energy for the first bit comparison
bit and not before. This does not require pre-charging of capaci- of the -based method is half of the set-and-down. The
tors and, possibly, their discharging after the bit decision. There- parasitic capacitance depends on technology and layout. Its
fore, the performed charge-redistribution is just what is required value can be large because for medium and high-resolutions
without wasting power. The only additional cost of this method it is necessary to use electronic shielding on the top and the
is that it uses n more switches to initially reset all the capacitors bottom which prevents couplings and noise injections.
to a common-mode voltage. The value of the MSB sets the arrays for second bit estima-
tion. The SA logic controls the 2C of the and
C. Charge-Recovery for “up” or “down” transition, respectively, as indicated also
in Fig. 4, and the DACs’ outputs finally settle to the following
The -based switching method operates in a similar way values:
as the set-and-down [12] technique. Both reduce the capaci-
tive array and simplify the MSB transition. However, for the
determinations of the remaining there is a different
switching sequence.
To outline the difference between the two methods Fig. 4
shows the operational steps of a 3-bit differential capacitive
array performing the -based charge recovery and the (4)
ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS 1115

The energy needed for the “up” transition in the is

from 2C charged up from to and from the other
capacitors connected to . They are

(5)

(6)

For the “down” transition in , the switching energy is only

coming from the capacitors connected to and the
value is

(7)
Fig. 5. Switching energy versus output code for three different techniques.
From (6) and (7) it is deducted that the energy used by the
differential DACs is complementary. Therefore, com-
pensates the energy drawn from by . Qualitatively,
the charge-recovery effect corresponds to a compensation of the the MSB mismatch-independently, the worst case DNL occurs
charge transferred to with charge coming from , at and . The feature relaxes the request of
as illustrated also in Fig. 4. Accordingly, we don’t need energy matching between unit capacitor by a factor . Therefore
from in each bit-cycling. Due to the charge-recovery imple-
(8)
mentation, the “down” transition of does not consume
switching energy; the second bit comparison just needs the en-
ergy for where the capacitor 2C is charged from that, for the used technology and design, gives fF.
to . The switching energy of the second bit transition However, this project employs a larger unity value: fF.
is output code independent, and it always obtains 50% less en- The choice serves to make negligible the effect of parasitic as-
ergy than the set-and-down which requires to discharge sociated to the interconnection metal lines.
the same capacitor in one of the differential DAC arrays.
The estimation of the energy required for the 3rd bit estima- III. CIRCUIT DESIGN
tion is code dependent and gives rise to the values indicated in
Fig. 4. For the transition A the -based switching method is A. Comparator Design
more advantageous; for the transition B the energy is almost the Fig. 6 shows the circuit schematic of the comparator with
same. resistive loaded preamplifier and latch [24]. The comparator
For the conventional charge-redistribution method the preamplifier has two differential pairs M1, M2 and M3, M4 con-
switching energy also depends on the code. The consumed nected to the outputs of the differential capacitive DAC and the
energy is much higher because of unnecessary charging and additional sampling capacitor . The currents at the output of
discharging actions. Fig. 5 compares the switching energy of the two pairs are summed up and injected on the resistive loads,
the charge-recycling, the set-and-down and the -based . The bias current and the load resistance yield a preamplifier
approaches. The given figures assume equal unit capacitor gain of 27 dB.
for the 10 b capacitor arrays. For all the methods the peak of The comparison cycling is divided into a reset phase and a
the consumed power occurs at half scale. The set-and-down regeneration phase. During the reset phase ,
method is more effective than the charge-recycling technique the preamplifier output is shorted to avoid memory effect of the
by almost a factor of 3. The -based switching method comparison. Moreover, M11–M14 reset the regenerative loop
grants an additional 33% average benefit. and set the outputs and to . Since the current source
transistor M15 is switched off no current flows from the supply
D. Linearity to ground. When the regeneration phase starts
As known the SAR algorithm does not ensure intrinsic M15 switches on and the input transistors M5–M6 force cur-
monotonicity. The most critical transition for the conventional rents flowing through the back-to-back inverters M7–M8 and
SAR ADC is at the middle range where half of the array M9–M10 to amplify the voltage difference to a full swing.
switches-on and the other half (minus one) switches-off. The The devices mismatch in the comparator bias does not affect
random variation of the value of the unity capacitance the linearity of the conversion. Since the non constant common
with variance renders rise to a differential nonlinearity mode voltage is rejected by the CMRR of the preamplifier, the
(DNL) at the critical transistion equal to [20], component mismatch gives rise to an equivalent input offset, as
[23]. Since the -based switching approach determines it is the case in conventional solutions.
1116 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010

Fig. 6. Circuit schematic of the dynamic comparator.

Fig. 7. (a) Timing diagram of bit-cycling. (b) Self-timed loop diagram and circuit schematic of VDC used to generate the preamplifier reset signal.

B. Variable Self-Timed Loop bit comparisons the conversion cycle is successively reduced
The bit-cycling can be divided into two phases as shown in according to the binary-weighted capacitor array. When the
Fig. 7(a): phase 1 for regeneration of the latch that depends asynchronous processing is applied the comparison period will
on the topology of the comparator; phase 2 for the SAR logic be always limited by the worst case DAC settling (the MSB/2
delay and settling for the DAC and preamplifier, which mainly transition in this work), which loses the advantage of asyn-
depends on the DAC’s structure and complexity of the logic. chronous operation. Instead, the scheme uses a variable delay
The asynchronous processing [16] can improve the conver- controller (VDC) that optimizes the pre-amplifier reset signal
sion speed by synchronizing the bit-cycling with the latch’s according to the switching sequence. As shown in Fig. 7(b), the
resolving time, which contributes with time saving between beginning of the reset signal is synchronous with the sampling
two adjacent strobes only when the time required by the phase clock and its delayed version, and it is triggered
1 is significant. Furthermore, its implementation depends on periodically by an inverter chain in series with the VDC. The
the time required for phase 2 being identical and fast enough. pulsewidth of the reset signal is controlled by the different
Indeed, the ladder structure of the capacitive DAC [16] allows sized PMOS transistors M1 and M2, which are enabled or
the bit switching of equivalent smaller capacitance instead of disabled according to the gate logic. The gate voltage of M3 is
binary weighted capacitor array, thus insuring that the next controlled by an external to determine the tradeoffs between
comparison signal triggered by the previous output of the the extended settling time and ADC’s performance.
latch should start after the DAC and preamplifier are settled.
C. SAR Logic
However, in this design, the SA logic and DAC settling in
phase 2 dominate the bit-cycling (i.e., the latch delay in phase For high-speed operation the SAR logic must be minimized
1 is much smaller). Since the MSBs are switched in the early to achieve more spare time allocation for the DAC and preampli-
ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS 1117

Fig. 8. Block diagram of the SAR logic.

fier settling. The SAR logic, shown in Fig. 8, consists of a set of

shift registers [25] , bit registers [26]
and a switching logic block. The CLKs used to control the shift
registers are synchronous with the reset of the comparator. The
bit register detects each bit decision from the comparator and
locks it for next stage processing. Since the circuit uses the
-based switching the designed switching logic block ob-
tains the outputs according to the switching sequence of
Fig. 3. Both the shift registers and bit registers are implemented
in full custom dynamic logic, which provides a faster and lower
power consumption SAR implementation. Fig. 9. Die microphotograph of the SAR ADC.

D. Technology and Layout Considerations

relaxed. The design uses , where is the unit ca-
The 10-bit SAR implementing the -based switching ap- pacitor equal to 50 fF. The split DAC leads to an architecture
proach has been designed using a one-poly-nine-metal (1P9M) with 5 b MSB array and 4 b LSB array, being the total capaci-
CMOS process with metal–insulator–metal (MIM) capacitor. tance 2.75 pF.
The supply voltage is 1.2 V with a target conversion speed of
100 MS/s. The digital part of the SAR ADC obtains low power IV. MEASUREMENT RESULTS
and fast conversion speed. Moreover, special care on the design The prototype ADC was fabricated and tested. Fig. 9 shows
of the layout prevents the capacitor mismatch and parasitic non- the die photograph whose total active area is 0.18 mm . The
linearity effect [23]. ADC has a full-scale input range of differential, or
Since the scheme uses the supply as reference, the switching single-ended. Fig. 10 shows the dynamic performance
speed of the capacitor array improves because the MOS transis- of the ADC with input frequency swept from 1.8 MHz to
tors that realize the switches are controlled with a maximum Nyquist. At a sampling rate of 100 MS/s the ADC can achieve
overdrive. The split structure of the capacitive DAC requires 9.1 ENOB@1.8 MHz and 8.6 ENOB@Nyquist. Fig. 11 shows
a low parasitic in the array’s LSB internal node [23]; further- the ADC output spectrum with the input frequency at 1.8 MHz
more, it is necessary to reduce the spur interference. The layout and 47 MHz. The second-harmonic distortion dominates the
satisfies these two requests by using of MIM capacitors and a Spurious Free Dynamic Range (SFDR): 71 dB at low frequency
carefully layout routing. The result limits the top-plate parasitic and near Nyquist frequency 65 dB. The mismatch between
to about 3%. As mentioned above, there is no requirement of two differential paths of the ADC is likely the cause. The
matching between the capacitive DAC array and the sampling third-harmonic becomes significant at Nyquist and the SNDR
capacitor . The only limitation is the limit that is very drops by 3 dB with a loss of 0.5 b. The distortion at high
1118 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010

Fig. 10. Dynamic performance versus input frequency.

Fig. 12. Measured INL and DNL.

TABLE I
SUMMARY OF PERFORMANCE

Fig. 11. FFT of the digital output. The input is either a 1.8 MHz or a 47 MHz
sine wave (full-scale) sampled at 100 MS/s.

frequency increases because of a relatively high nonlinearity of

the on-resistance of the sampling switches.
The DNL and INL are illustrated in Fig. 12. At 100 MS/s, The measured performance of the prototype ADC is summa-
the DNL and INL are LSB and rized in Table I. Table II compares this work with the state-of-
LSB, respectively. Usually, the worst case DNL and INL hap- the-art ADCs. The designs with a slightly better FoM [11], [12]
pens in the middle (the MSB transition) in the conventional SAR are for lower speed and ENOB.
ADC. The experimental measurements verify the benefit of the
-based switching approach that imposes a lower DNL at V. CONCLUSION
the MSB transition. The INL is s-like and is minimized in the A 1.2 V 10-bit 100 MS/s SAR ADC has been presented. The
middle. The advantage is due to the MSB decision’s indepen- reference-free and the power efficient -based switching
dence of the capacitor mismatch as discussed in Section II-D. technique enable high speed and low power SAR ADC’s oper-
The worst cases DNL occur at points where the parasitic effect ation. The -based switching approach ensures a mismatch
of the split DAC structure is more significant. The power con- free MSB determination and, at the same time, saves capacitor
sumption is 3 mW at 1.2 V. The analog power, including the ca- area. The charge-recovery in each bit cycling leads to switching
pacitive DAC array, the comparator and the sampling network, energy lower than both charge-recycling and set-and-down
is 1.3 mW and the digital power is 1.7 mW. Since the conven- methods. The reference-free implementation and the passive
tional tradeoff between conversion speed and power of the ref- multiplication by 2 avoid the use of the power-hungry resistive
erence generator does not affect this design the digital power is ladder/reference buffer without imposing a rail-to-rail input.
a significant fraction of the total power dissipation. It is mainly The result is a fast RC settling and low power dissipation during
drawn from the switches buffers and self-timed loop. SA conversion in the capacitive DAC array. The utilization
ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS 1119

TABLE II
COMPARISON TO STATE-OF-THE-ART WORKS

of a variable self-timed loop minimizes the waste of time [11] V. Giannini et al., “An 820 W 9 b 40 MS/s noise-tolerant dy-
during each bit cycling and improves the conversion speed. The namic-SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2008, pp. 238–239.
prototype ADC draws only 3 mW power from the 1.2 V supply [12] C. C. Liu et al., “A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 m
and has a FoM of 77 fJ/step. CMOS process,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009,
pp. 236–237.
[13] M. V. Elzakker et al., “A 1.9 W 4.4 fJ/conversion-step 10 b 1 MS/s
ACKNOWLEDGMENT charge-redistribution ADC,” in IEEE ISSCC Dig. Tech. Papers, Feb.
The authors would like to thank the Associate Editor and 2008, pp. 244–246.
[14] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge
the anonymous reviewers for their insightful comments and recycling approach for a SAR converter with capacitive DAC,” in Proc.
suggestions. IEEE ISCAS, May 2005, pp. 184–187.
[15] Z. Cao, S. Yan, and Y. Li, “A 32 mW 1.25 GS/s 6 b 2 b/step SAR ADC
in 0.13 m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp.
REFERENCES 542–543.
[1] O. A. Adeniran et al., “A CMOS low-power ADC for DVB-T and [16] M. S. W. Chen and R. W. Brodersen, “A 6 b 600 MS/s 5.3 mW asyn-
DVB-H systems,” in Proc. IEEE ISCAS, May 2004, vol. 1, pp. 209–212. chronous ADC in 0.13 m CMOS,” in IEEE ISSCC Dig. Tech. Papers,
[2] K. Honda et al., “A low-power low-voltage 10-bit 100-M sample/s Feb. 2006, pp. 574–575.
pipeline A/D converter using capacitance coupling techniques,” IEEE [17] W. Liu et al., “A 600 MS/s 30 mW 0.13 m CMOS ADC array
J. Solid-State Circuits, vol. 42, no. 4, pp. 757–765, Apr. 2007. achieving over 60 dB SFDR with adaptive digital equalization,” in
[3] S.-T. Ryu et al., “A 10-bit 50-MS/s pipelined ADC with opamp current IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 82–83.
reuse,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 475–485, Mar. [18] Y. F. Chen et al., “Split capacitor DAC mismatch calibration in suc-
2007. cessive approximation ADC,” in Proc. IEEE CICC, Sep. 2009, pp.
[4] J. Li et al., “A 1.8-V 22-mW 10-bit 30 MS/s pipelined CMOS ADC 279–482.
for low-power subsampling applications,” IEEE J. Solid-State Circuits, [19] S.-K. Lee, S.-J. Park, and Y. Suh, “A 1.3 W 0.6 V 8.7-ENOB succes-
vol. 43, no. 2, pp. 312–329, Feb. 2008. sive approximation ADC in a 0.18 m CMOS,” in Symp. VLSI Circuits
[5] B. Murmann and B. Boser, “A 12 b 75 MS/s pipelined ADC using Dig. Tech. Papers, Jun. 2009, pp. 242–243.
open-loop residue amplification,” in IEEE ISSCC Dig. Tech. Papers, [20] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in
Feb. 2003, pp. 328–329. 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State
[6] T. Sepke et al., “Comparator-based switched-capacitor circuits for Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
scaled CMOS technologies,” in IEEE ISSCC Dig. Tech. Papers, Feb. [21] Y.-K. Chang et al., “A 8-bit 500 KS/s low power SAR ADC for bio-
2006, pp. 220–221. medical application,” in Procs. IEEE ASSCC, Nov. 2008, pp. 228–231.
[7] S.-K. Shin and Sepke et al., “A fully-differential zero-crossing-based [22] A. Agnes et al., “A 9.4-ENOB 1 V 3.8 W 100 kS/s SAR ADC with
1.2 V 10 b 26 MS/s pipelined ADC in 65 nm CMOS,” in Symp. VLSI time-domain comparator,” in IEEE ISSCC Dig. Tech. Papers, Feb.
Circuits Dig. Tech. Papers, Jun. 2008, pp. 218–219. 2008, pp. 246–247.
[8] M. Anthony et al., “A process-scalable low-power charge-domain [23] Y. Zhu, U.-F. Chio, H.-G. Wei, S.-W. Sin, S.-P. U, and R. P. Martins,
13-bit pipeline ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. “A power-efficient capacitor structure for high-speed charge recycling
2008, pp. 222–223. SAR ADCs,” in Proc. IEEE ICECS, Aug. 2008, pp. 642–645.
[9] I. Ahmed et al., “A 50 MS/s 9.9 mW pipeline ADC with 58 dB SNDR [24] V. Katyal, R. L. Geiger, and D. J. Chan, “A new high precision low
in 0.18 m CMOS using capacitive charge-pumps,” in IEEE ISSCC offset dynamic comparator for high resolution high speed ADCs,” in
Dig. Tech. Papers, Feb. 2009, pp. 164–2165. Proc. IEEE APCCAS, Dec. 2006, pp. 5–8.
[10] J. Craninckx and G. V. Plas, “A 65 fJ/conversion-step 0-to-50 MS/s [25] B. P. Ginsburg and A. P. Chandrakasan, “Dual time-interleaved suc-
0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” cessive approximation register ADCs for an ultra-wideband receiver,”
in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246–247. IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 247–257, Feb. 2007.
1120 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010

[26] U.-F. Chio, H.-G. Wei, Y. Zhu, S.-W. Sin, S.-P. U, and R. P. Mar- Seng-Pan U (S’94–M’00–SM’05) received the
tins, “A self-timing switch-driving register by precharge-evaluate logic B.Sc. and M.Sc. degrees in 1991 and 1997, respec-
for high-speed SAR ADCs,” in Proc. IEEE APCCAS, Dec. 2008, pp. tively, and the joint Ph.D. degree from the University
1164–1167. of Macau (UM) and the Instituto Superior Técnico
[27] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW de Lisboa in 2002 with highest honor in the field of
pipelined ADC using dynamic residue amplification,” in Symp. VLSI high-speed analog IC design.
Circuits Dig. Tech. Papers, Jun. 2008, pp. 216–217. He has been with the Department of EEE/FST/UM
[28] K. Honda, M. Furuta, and S. Kawahito, “A low-power low-voltage since 1994. He is currently an Associate Professor.
10-bit 100-M sample/s pipeline A/D converter using capacitance He co-founded in 2003 and is leading the Analog
coupling techniques,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. and Mixed-Signal VLSI research lab. Dr. U is also
757–765, Apr. 2007. the advisor for more than 10 international student
paper award recipients. He has published more than 100 scientific papers in
IEEE/IET journals and conferences. He holds one U.S. patent (three filed) and
Yan Zhu (S’10) received the B.Sc. degree in elec- has co-authored two scientific books at Springer. In 2001, Dr. U co-founded
trical engineering and automation from Shanghai the Chipidea Microelectronics (Macau), Ltd.—the sole innovative-technology
University, Shanghai, China, in 2006, and the M.Sc. IC design company in Macau for devoting advanced analog and mixed-signal
degree in electrical and electronics engineering from Semiconductor IP product development. He is currently the corporate Senior
the University of Macau, Macao SAR, China, in 2008. Analog Design Manager and Site Manager. (Chipidea was acquired in May
She is working in a research group of the Analog and 2009 by Synopsys Inc.).
Mixed-Signal VLSI Laboratory and pursuing the Dr. U received the Excellent Young Scholar Award 2001 (1st Prize), The
Ph.D. degree at the University of Macau. Most Favorite EEE Teacher Award 2002 and 2003, The FST Teaching Award
Her research interests include low-power, high- 2004 from the UM. He also received The Young Researcher Award 2002
speed monolithic A/D converter designs. from Macau International Institute, and the National Lecture Fellowship 2005
from K. C. Wong Education Foundation for lectures in Tsinghua, Fudan and
Zhejiang University. Dr. U is currently the Industrial Relationship Officer of
IEEE Macau Section and the Chairman of IEEE Macau CAS/COMM and
Chi-Hang Chan was born in Macau S.A.R., China, SSC chapters. He has been with technical review committee of various IEEE
in 1985. He received the B.S. degree in electrical en- journals and conferences. He was the chairman of the local organization
gineering from University of Washington, Seattle, in committee of IEEJ AVLSIWS’04, Technical Program co-Chair of IEEE
2008. He is currently working toward the M.S. degree APCCAS’08. He is also the Program Co-chair of ICICS’09 and Technical
at University of Macau, Macao SAR, China. Program Committee of A-SSCC.
His research interests include Nyquist ADC and
mixed-signal circuits. Currently, his research mainly
focuses on comparator offset calibration and ADC.

Rui Paulo Martins (M’88–SM’99–F’08) received

U-Fat Chio (S’07) received the B.Sc. degree in elec- the Bachelor, Masters, and Ph.D. degrees as well
trical engineering and the M.Sc. degree in communi- as the Habilitation for Full Professor in electrical
cations engineering, both from National Sun Yat-Sen engineering and computers from the Department
University, Taiwan, in 2002 and 2004, respectively. of Electrical and Computer Engineering, Instituto
From 2004 to 2005, he was with DenMOS Tech- Superior Técnico (IST), TU of Lisbon, Portugal, in
nology Inc., Hsinchu Science Park, Taiwan. Now 1980, 1985, 1992 and 2001, respectively.
he is studying in a research group of the Analog He has been with the Department of Electrical and
and Mixed-Signal VLSI Laboratory, University of Computer Engineering/IST, TU of Lisbon, since Oc-
Macau, Macao SAR, China. His research interest tober 1980. Since 1992, he has been on leave from
is high-speed analog and mixed-signal integrated IST, TU of Lisbon, and is also with the Department
circuit designs. of Electrical and Electronics Engineering, Faculty of Science and Technology
(FST), University of Macau (UM), Macao, China, where he is a Full Professor
since 1998. In FST he was the Dean of the Faculty from 1994 to 1997 and he
has been Vice-Rector of the University of Macau since 1997. From September
Sai-Weng Sin (S’98–M’06) received the B.Sc., 2008, after the reform of the UM Charter, he was nominated after open inter-
M.Sc., and Ph.D. degrees with the highest honor in national recruitment as Vice-Rector (Research) until August 31, 2013. Within
electrical and electronics engineering from Univer- the scope of his teaching and research activity he has taught 20 bachelor and
sity of Macau, Macao SAR, China, in 2001, 2003, master courses and has supervised 21 Ph.D. and Masters theses. He has pub-
and 2008, respectively. lished 13 books, co-authoring three and co-editing ten, and five book chapters,
He is currently an Assistant Professor in the Faculty 176 refereed papers in scientific journals and conference proceedings, as well as
of Science and Technology, University of Macau, 70 other academic works, for a total of 264 publications, in the areas of micro-
and is the Coordinator of the Data Conversion and electronics, electrical and electronics engineering, engineering and university
Signal Processing (DCSP) Research Line in Analog education. He has co-authored seven submitted U.S. patents. He founded the
and Mixed-Signal VLSI Laboratory, University of Analog and Mixed-Signal VLSI Research Laboratory of UM: http://www.fst.
Macau. His research interests include low-voltage, umac.mo/en/lab/ans_vlsi/.
high-speed analog integrated circuit designs, high-performance data converters, Prof. Rui Martins was the Founding Chairman of the IEEE Macau Section
as well as in the timing-jitter analysis and low-jitter clock generator designs for from 2003 to 2005, and of the IEEE Macau Joint Chapter on Circuits and
high-performance, high-speed mixed-signal systems. He has published over 30 Systems (CAS)/Communications (COM) from 2005 to 2008 [World Chapter
technical journals and conference papers in the field of interests. of the Year 2009 of the IEEE Circuits And Systems Society (CASS)]. He
Dr. Sin is currently the Secretary of IEEE SSC Macau Chapter, and Treasurer/ was the General Chair of the 2008 IEEE Asia-Pacific Conference on Circuits
Secretary of IEEE CAS/COM Macau Joint Chapter and the Member of Exec- and Systems (APCCAS’2008), and was elected Vice-President for Region
utive Committee—Academic Affair of IEEE Macau, and has been a member 10 (Asia, Australia, the Pacific) of the IEEE Circuits and Systems Society
of the Organization Committee of the 2004 IEEJ AVLSI Workshop, as well as (CASS), for the period 2009–2010. He is Associate Editor of the IEEE
the Special Session Co-Chair of the 2008 IEEE APCCAS Conference. He re- TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II—EXPRESS BRIEFS for
ceived the Chipidea Microelectronics Prize—Postgraduate Level in 2008 for 2010–2011. He was the recipient of two government decorations: the Medal
outstanding academic and research achievements in microelectronics, as well of Professional Merit from Macao Government (Portuguese Administration)
as the Financial Support Award for the Student Paper Contest in ISCAS’05, and in 1999, and the Honorary Title of Value from Macao SAR Government
the Paper with Certificate of Merit for the RIUPEEEC’06. (Chinese Administration) in 2001.
ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS 1121

Franco Maloberti (A’84–SM’97–F’96) received mainly in the areas of switched-capacitor circuits, data converters, interfaces
the Laurea degree in physics (summa cum laude) for telecommunication and sensor systems, and CAD for analog and mixed
from the University of Parma, Parma, Italy, in 1968, A/D design. He has written more than 400 published papers on journals or
and the Doctorate Honoris Causa in electronics conference proceedings, four books, and holds 30 patents.
from the Instituto Nacional de Astrofisica, Optica y Dr. Maloberti was the recipient of the XII Pedriali Prize for his technical and
Electronica (Inaoe), Puebla, Mexico, in 1996. scientific contributions to national industrial production, in 1992. He was co-re-
He was the TI/J.Kilby Chair Professor at the cipient of the 1996 Fleming Premium, IEE, the Best Paper Award, ESSCIRC
A&M University, Texas and the Distinguished 2007, and the Best Paper Award, IEEJ Analog Workshop 2007. He received
Microelectronic Chair Professor at the University of the 1999 IEEE CAS Society Meritorious Service Award, the 2000 IEEE CAS
Texas at Dallas. He was a Visiting Professor at The Society Golden Jubilee Medal, and the IEEE Millenium Medal. He was Vice
Swiss Federal Institute of Technology (ETH-PEL), President, Region 8, of the IEEE Circuit and Systems Society (1995–1997), As-
Zurich, Switzerland and at the EPFL, Lausanne, Switzerland. Presently he is sociate Editor of IEEE TRANSACTIONS ON CIRCUIT AND SYSTEMS PART II 1998
Microelectronics Professor and Head of the Micro Integrated Systems Group, and 2006–2007, President of the IEEE Sensor Council (2002–2003), member
University of Pavia, Italy and Honorary Professor, University of Macau, of the BoG of the IEEE CAS Society (2003–2005) and Vice President, Publica-
Macao SAR, China. His professional expertise is in the design, analysis, tions, of the IEEE CAS Society (2007–2008). He is Distinguished Lecturer of
and characterization of integrated circuits and analog digital applications, the Solid-State Circuits Society.