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com/science/article/pii/S0026269219303179
Manuscript_7354692b375ed082c2b577e092c389e8

A 7b 400MS/s Pipelined SAR ADC in 65nm CMOS

Ruixue Ding, Li Dang, Hanchao Lin, Depeng Sun, Shubin Liu, Zhangming Zhu
†shuvin101@126.com

School of Microelectronics, Xidian University, 2 Taibai Road, Xi’an 710071, P. R. China

Abstract: This paper presents a 7-bit 400-MS/s pipelined successive approximation register (SAR)
analog-to-digital converter (ADC) with high reliability. To meet the high demand for medium
resolution and high sampling speed, a modified switching scheme is adopted to resolve charge
leakage problem and to improve the reliability of SAR ADC. Compared to the conventional
architecture, the modified bootstrapped switch which uses two sampling MOSFETs is employed
to increase the uniformity of sampling voltage and save the chip area. In addition, three parallel
comparators are controlled by a novel asynchronous clock generator to minimize the latching error.
The measurement result shows that the ADC, implemented in the 65-nm CMOS process, achieves
the 40.83 signal-to-noise and distortion ratio (SNDR) and 64.75 spurious-free dynamic ranges
(SFDR) at 400-MHz sampling frequency without additional digital calibration.
Keywords: Pipelined SAR ADC, reliability, charge leakage, asynchronous clock generator

I. INTRODUCTION
With the development of mobile communication toward 5th generation wireless systems,
communication systems put forward higher demand for ADCs with ultra-high speed, medium
resolution and low power consumption. Considering the following type of ADCs: flash ADC is the
fastest but sacrifices a lot of power and area; pipelined ADC can achieve high speed and precision,
but it still has high power consumption due to the existence of inter-stage operational amplifier;
the SAR ADC has the advantages of low power consumption and high accuracy, but its
quantization speed is slow. Based on these structures to realize an ADC with high performance
and low power consumption has become a key challenge. Although time interleaving technique
has been adopted in many papers [1]-[2] to greatly improve quantization speed, the increasing
number of channels makes the impact of inter-channel mismatch on quantization accuracy more
serious. So, a single-channel ADC with high quantization speed is also required in time
interleaved ADC. Many mixed structures are proposed by combining the advantages of various
structures and suppressing the shortcomings as much as possible, which meet the application
requirement. Multi-bit per cycle conversion is the advantage of flash ADC, and pipeline SAR
ADC [3] also achieves a high performance. Therefore, an ADC combined the two structure above
can greatly improve the overall performance of the converter.
In the published papers [7]-[10], multi-bit per cycle technique has demonstrated its
advantages of speed. The 2b per cycle means that the ADC converter can produce two comparison
results in a comparison cycle. A 2.4GS/s SAR ADC in [8] with 1-then-2b/cycle conversion scheme
is proposed to realize 7 bits resolution. A 2b/cycle SAR ADC in [9] achieves 6-bit and 1.35GS/s
quantization speed. In [10], an SAR ADC with 2b/cycle in 65nm CMOS resolves 8 bits at
400-MHz sampling frequency.
However, due to many non-ideal factors not taken into account, there are also many
reliability problems in the relevant papers. In [8], the 1-then-2b/cycle conversion scheme is
suitable for the background offset calibration, but the residual voltage drops to a voltage lower

© 2019 published by Elsevier. This manuscript is made available under the Elsevier user license
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than GND, leading to the charge leakage. Many comparators are employed in [9] to resolve 2-bit
in one comparison, causing larger power consumption and mismatch problems. Using independent
bootstrapped switches to sample the same signal in [10], there will be some discrepancies between
the sampled voltages on different capacitor arrays. Consequently, all the non-ideal factors reduce
performance advantages of the new structure.
In order to address the above issues, this paper analyzes the conventional circuit and
switching scheme in detail, and some solutions are given out in the proposed pipelined SAR ADC.
The paper is organized as follows. Section II briefly illustrates the architecture of the proposed
pipelined SAR ADC. Section III analyses the inaccuracy factor and put forward relevant solutions.
The chip microphotography and measurement results of the ADC are described in Section IV.
Section V concludes this paper.

II. ARCHITECTURE OF THE PROPOSED PIPELINED SAR ADC

Fig. 1 shows the conceptual block diagram of the pipelined SAR ADC in this paper. In order
to restrain the unreliability and improve the speed of SAR ADC in traditional architecture, the
1-then-2b/cycle technique proposed in [8] is adopted. Fig. 2 demonstrates the operation timing of
the proposed Pipelined SAR ADC. Following by the second comparison, the sampled differential
signal can realize 3-bit rough quantization in two comparison cycles. Then a multiplying
digital-to-analog converter (MDAC) circuit with a high-performance operational amplifier,
sharing the partial capacitor arrays with the first-stage SAR ADC, is applied to realize the double
amplification of residual signals. After that, the second-stage SAR ADC will finely quantify the
amplified residual signals to resolve 5-bit quantization code. Finally, a 7-bit resolution can be
obtained through the digital output of two-stage ADC being encoded by the digital error correction
circuit.

Φ1 Φ2

ΦRA
VCM

VCM
VDD

GND

GND

Fig. 1 Proposed Pipelined SAR ADC architecture

As the key function module of pipelined ADC, the gain and load of MDAC are higher than
the traditional pipeline ADC, which requires higher gain and bandwidth operational amplifiers to
ensure accuracy and conversion speed. In a word, the design of MDAC circuit is very important.
In order to improve the quantization accuracy and reduce power consumption, the redundant bit
correction technique [4] and gain halving technique are applied in this design, reducing the
inter-stage gain from 23 to 2. These techniques reduce the output amplitude and open-loop gain of
the operational amplifier, thereby making the circuit easier to be designed. Because of the negative
feedback structure, the open-loop gain needed must be greater than 41dB. In addition, in order to
achieve signal amplification in 700 ps, the GBW of the operational amplifier is required to be
greater than 1.8 GHz. To meet the requirements of gain and signal swing, the two-stage
operational amplifier achieves 2.1 GHz GBW and a gain of 45 dB.

Fig. 2 Operation timing of the proposed Pipelined SAR ADC

III. ANALYSIS AND SOLUTION OF INACCURACIES

In order to resolve the inaccuracies of the SAR ADC in this paper, the effects of non-ideal
factors on ADC performance are analyzed in detail from the aspects of switching scheme, control
of the comparator and sampling circuit, and corresponding solutions are proposed respectively.
1. Charge leakage
In the traditional 2b/cycle structure, the switching scheme is critical to the overall
quantization process. The various switching schemes result in different degree of charge leakage.
The probabilistic charge leakage problem is that the voltage on the top plate of capacitor changes
imperfectly due to the pre-charge operation, and this voltage can be expressed as：
D1 D2 D3
Vtop = Vsampled − VCM − VCM − VCM (1)
2 4 8
where D1, D2 and D3 may be “0” or “1” respectively. When the sampled signal Vsampled is relatively
small (especially close to GND), the negative voltage Vtop will drive the sampling MOS transistor
to enter the sub-threshold region in the holding phase, thereby leading to the charge leakage. The
charge leakage affects the accuracy of quantization results, even leading to error codes directly.
The cause of charge leakage has been introduced above, so the switching scheme should be
used carefully for different quantization circuits. Three conventional switching schemes suitable
for the 2-bit/cycle SAR architecture are as follow: a) monotonic switching scheme [5] with
addition pre-charge operation; b) monotonic switching scheme with subtraction pre-charge
operation; c) Vcm-based [6] multi-bit switching scheme.
When these switching schemes are applied in 2b/cycle conversion scheme, the residual signal
generated in the normal quantization process is illustrated in Fig. 3. As can be seen from the figure,
the pre-charge operation before every comparison is needed. When the full swing input signal is
taken into account, the residual signals shown in the Fig. 3(a) are always higher than GND. So,
there is no charge leakage. However, the figure also demonstrates that the change of the residual
signals results in the unstable common-mode voltage, which increases the mismatch between the
parallel comparators and limits the application of this switching scheme in the multi-bit per
conversion architecture of two-stage SAR ADC.
 1
VP1 = Vip VP1 = Vip − VCM
2
1 1 1
VN2 = VN1 = Vin + VCM VN2 = VN1 = Vin − VCM + VCM
2 4 8
1 1 1
VP2 = VP3 = Vip + VCM VP2 = VP3 = Vip − VCM + VCM
2 2 8
1
VN3 = Vin VN3 = Vin − VCM
4

1 1
1 VP1 = Vip − VCM − VCM
VP1 = Vip − VCM 2 8
2 1
VN2 = VN1 = Vin − VCM
VN2 = VN1 = Vin 4
VP2 = VP3 = Vip 1
VP2 = VP3 = Vip − VCM
2
1
VN3 = Vin − VCM 1 1
VN3 = Vin − VCM − VCM
2 4 8

1 1
VP = Vip − VCM → (Vip min = 0, VPmin = − VCM )
2 2
1 1
VN = Vin − VCM → (Vin min = 0, VN min = − VCM )
2 2

1 1 1 1
VP1 = Vip − VCM VP1 = Vip − VCM + VCM − VCM
2 2 4 8
1 1 1 1
VN2 = VN1 = Vin + VCM VN2 = VN1 = Vin + VCM − VCM + VCM
2 2 4 8
1 1 1 1
VP2 = VP3 = Vip + VCM VP 2 = VP3 = Vip − VCM + VCM + VCM
2 2 4 8
1 1 1 1
VN3 = Vin − VCM VN3 = Vin + VCM − VCM − VCM
2 2 4 8

Fig. 3 The residual signal in 2b/cycle conversion scheme, (a) monotonic switching scheme
with addition pre-charge operation, (b) monotonic switching scheme with subtraction pre-charge
operation, (c) Vcm-based multi-bit switching scheme.
The residual signal depicted in Fig. 3(b) demonstrates that some of them become lower than
the input signal after the initial pre-charge operation. If the input signal is close to GND, the
minimum residual signal will be a negative voltage, leading to a charge leakage. Besides, the
common-mode voltages of the residual signal also change all the time and are getting lower than
Vcm. Similarly, the residual signal in Fig. 3(c) shows that a negative voltage may be generated
during the quantization process to trigger a charge leakage. In addition, only one common-mode
voltage of the residual signals is getting closer to Vcm, and others remain Vcm.
From the above analysis, the degree of charge leakage in the three switching schemes is
different due to the pre-charge operation. If the first pre-charge operation is cancelled, the charge
leakage may be suppressed. In addition, restricting the swing of the input signal can also alleviate
the charge leakage. For example, the charge leakage can be avoided by increasing the
common-mode voltage of the input signal, which results in the signal swing shrinkage. Therefore,
the application of SAR ADC is severely restricted. In order to achieve a compromise between
reliability and speed, the 1-then-2b/cycle architecture, which removes the pre-charge operation
before the first comparison, is introduced to replace the traditional 2-bit/cycle architecture.
Fig. 4 illustrates the new residual signals in the 1-then-2b/cycle conversion scheme. Although
the monotonic switching scheme with subtraction pre-charge operation still results in the charge
leakage slightly, the minimum input signal to avoid charge leakage is decreased from the 1/2Vcm
to 1/4Vcm. And there is no charge leakage for the Vcm-based multi-bit switching scheme. Finally,
in the proposed pipelined SAR ADC, the Vcm-based multi-bit switching scheme is applied in the
1st-stage to ensure the reliability of quantization and meets the input common-mode voltage
requirements of inter-stage op-amp. In addition, it can be concluded from section II that the
differential input signals of the 2nd-stage are signals with common-mode 600mV and amplitude
150mV, which are suitable to be quantified by the monotonic switching scheme with subtraction
pre-charge operation.
1 1 1
1 1 VP1 = Vip − VCM − VCM − VCM
VP1 = Vip VP1 = Vip − VCM − VCM 2 8 16
2 4 1
VN 2 = VN1 = Vin VN 2 = VN1 = Vin VN 2 = VN1 = Vin − VCM
1 4
VP2 = VP3 = Vip VP2 = VP3 = Vip − VCM 1 1
2 VP2 = VP3 = Vip − VCM − VCM
1 2 8
VN3 = Vin VN3 = Vin − VCM 1 1
4 VN3 = Vin − VCM − VCM
4 16
1 1 1
VP = Vip − VCM → (Vip min = 0, VPmin = − VCM ) VN = Vin − VCM
2 2 4
1
1 1 (Vin min = 0, VN min = − VCM )
VN = Vin − VCM → (Vin min = 0, VN min = − VCM ) 4
2 2

1 1 1 1 1 1
VP1 = Vip − VCM − VCM VP1 = Vip − VCM + VCM − VCM − VCM
VP1 = Vip 2 4 2 4 8 16
1 1 1 1 1 1
VN 2 = VN1 = Vin VN 2 = VN1 = Vin + VCM + VCM VN 2 = VN1 = Vin + VCM − VCM + VCM + VCM
2 4 2 4 8 16
VP2 = VP3 = Vip 1 1 1 1 1 1
VP2 = VP3 = Vip − VCM + VCM VP2 = VP3 = Vip − VCM + VCM − VCM + VCM
2 4 2 4 8 16
VN3 = Vin 1 1 1 1 1 1
VN3 = Vin + VCM − VCM VN3 = Vin + VCM − VCM + VCM − VCM
2 4 2 4 8 16

Fig. 4 The residual signal in 1-then-2b/cycle conversion scheme, (a) monotonic switching scheme
with subtraction pre-charge operation, (b) Vcm-based multi-bit switching scheme.
2. Latching error
Unlike 1-bit/cycle SAR ADC, three parallel comparators, which are essential in 2-bits/cycle
architecture, must operate under the unified way to achieve the twofold quantization rate, so the
control of those comparators should be considered seriously.

Fig. 5 Simulation waveform under different asynchronous clock generators, (a) two-input
asynchronous clock generator, (b) six-input asynchronous clock generator.
 In the traditional asynchronous clock circuit, the comparator control signal Clkc and the
dynamic latch signal Valid are generated only by the outputs of one comparator. However, in the
2b/cycle SAR ADC, the pre-charge operation makes the input voltages of the three comparators
are not identical, leading to the various output delay in comparison phase. Therefore, if only one
traditional asynchronous clock circuit is employed to the three parallel comparators, three
comparators can work under the identical control of Clkc and Valid, but the output of other
comparators will not always be latched properly. As plotted in the Fig. 5(a), the OutP1 and OutN1
are not settled down when the negative edge of latch signal Valid comes, leading to a latching
error. Furthermore, when all the outputs of comparators should be taken into account to produce
the relevant signals in one clock generator, the delay of the combinational logic circuits caused by
the increasing fan-in number, as well as the output delay of comparators, will directly produce a
longer comparison cycle shown in the Fig. 5(b), which eventually affects the overall speed of
ADC and even leads to serious logical errors. To refrain from the above problems, a novel
structure of the asynchronous clock generator shown in Fig. 6(a) is proposed in this design.

Fig. 6 (a) The proposed asynchronous clock generator (b) simulation waveform
From the above analysis, the differences of input voltages between comparators vary the
output delays of the comparison results, but the reset delays of the three comparators are exactly
equal. Based on the two delays, the related control signal generation is divided into two parts in
the new structure. One part is that three comparison results are used to produce the falling edge of
the Valid signal and the rising edge of the Clkc signal. (The comparison results are latched on the
falling edge of Valid signal; the comparator is reset on the rising edge of the Clkc signal.) Another
part uses the reset result of one comparator to generate the rising edge of the Valid signal and the
falling edge of the Clkc signal. (The negative edge of Clkc signal triggers the comparators to enter
the comparison phase.)
Fig. 6(a) shows the proposed asynchronous clock generator. The outputs of three comparators
are passed through a NAND gate respectively, obtaining the three results (S1、S2、S3). Then these
results are adopted to drive the three-input dynamic NAND gate shown in the red ellipse, whose
result (S4) is employed to control the PMOS M7 and M9. In addition, only OutP3/OutN3 are applied
to an AND gate to drive the NMOS M8 and M11. Finally, the four MOS transistors drive the
following invertor or buffer to flip the Valid and Clkc signal respectively. Worth noting that is this
structure separates the Clks and RDY signal from the critical path by an OR gate and a NMOS
M10, reducing a lot of delays in traditional circuits. The simulation results, demonstrated in the Fig.
6(b), show a shorter comparison cycle and the correct latching operation.
3. Sampling error
In a 2b/cycle SAR ADC, using multiple bootstrapped switches shown in [10] increases the
area overhead significantly. In addition, there are more discrepancies between the bootstrapped
switches causing by the fluctuation of production process and other non-ideal factors. As a result,
the voltage values sampled onto the two capacitor arrays are different when sampling the same
input signal. In order to save the chip area and improve the consistency between the sampled
voltages, a modified bootstrapped switch structure is proposed in this paper.
Fig. 7(a) illustrates the schematic of the proposed bootstrapped switch. It can be seen that two
sampling MOS transistors, M11 and M12, share the gate voltage bootstrapped circuit. So, this
structure can not only reduce the area of the whole sampling circuit, but also guarantee the
sampling MOSFETs working under the identical condition. Moreover, to meet the demand in
speed and accuracy of the bootstrapped switches, only one MOSFET (M9), whose source terminal
is jointed to Clk signal directly, instead of an inverter driven by Clkb, is used to shut down the
sampling MOSFETs in this structure. As shown in Fig. 7(b), the simulation results denotes that the
Vgate1 waveform falls down faster than the Vgate0 waveform, which means that the shutdown
delay is reduced by a third at least compared to the conventional structure. Vgate1 is the gate
terminal voltage of sampling MOSFETs in the proposed bootstrapped switch circuit, while Vgate0
is the corresponding voltage in conventional circuit.
VDD
Clkb
Clkb
Clk

Fig.7 (a) The proposed bootstrapped switch schematic (b) Shutdown delay

IV. EXPERIMENT RESULTS

The proposed ADC was fabricated in a 65-nm 1P9M CMOS technology, and the die
microphotograph of which is shown in Fig. 8, in which every function module is described by its
names. The active area is 0.18 mm2. The dynamic performance of the proposed pipelined SAR
ADC was measured using tone testing. After the fast Fourier transform (FFT), the output spectrum
of the ADC with a Nyquist input is illustrated in Fig. 9, and the harmonics are denoted by red dots
and numbers in the spectrum graph. Furthermore, the SNDR and SFDR are 40.83 dB and 64.75
dB at the sampling speed of 400MS/s, respectively. The proposed ADC consumes 5.9 mW at a
1.2V supply without offset calibration, and the simulated power breakdown of which has been
demonstrated in Fig. 10. Measured DNL and INL of the ADC are shown in the Fig. 11, in which
the peak DNL and INL are +0.188/-0.124LSB and +0.356/-0.315LSB respectively.
 As shown in Table I, compared with other state-of-the-art ADCs in [10]-[14], the proposed
ADC without offset calibration still has a competitive performance.

Fig. 8 Die microphotograph of the proposed ADC

Fig. 9 The measured FFT spectrum

Fig. 10 Power breakdown

Fig. 11 Measured DNL and INL

 Table I. Performance summary and comparison
References [10] [11] [12] [13] [14] This work

Architecture 2b SAR SAR 2b SAR 3b SAR SAR 1-2b Pipelined SAR

Technology 65nm 40nm 65nm 65nm 65nm 65nm

Resolution 8b 6b 6b 6b 9b 7b

Sampling 400MS/s 700 MS/s 320MS/s 410 MS/s 100 MS/s 400MS/s

Supply (V) 1.2 1.1 1.1 1 1.2 1.2

SNDR@Nyq(dB) 40.39 31.5 34.22 30.02 47 40.83

Power (mW) 4 3.1 9.81 2.03 4.0 5.9

Area (mm2) 0.028 0.015 N/A N/A 0.02 0.18

Fom@ Nyq
117 144 479 189.17 220 163
(fJ/conv.-step)

Offset Cal. Yes Yes No No No No

V. CONCLUSION
A 7b 400MS/s pipelined SAR ADC in 65nm CMOS has been presented. The modified
switching schemes are adopted to resolve the charge leakage, the latching error of three parallel
comparators is also suppressed by the new asynchronous clock generator, and the proposed
bootstrapped switch guarantees the uniformity of sampling voltage. Finally, a high reliability ADC
is achieved.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (61874173,
61874174, 61674118, 61625403), Key Research and Development Program of Shaanxi Province
(2018ZDXM-GY-007).

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