An Energy-Efficient 1MSps 7µW 11.

9fJ/conversion
step 7pJ/sample 10-bit SAR ADC in 90nm
Taimur G. R. Kuntz∗ , Cesar R. Rodrigues† Saeid Nooshabadi
Microelectronics Group Department of Electrical and Computer Engineering
Federal University of Santa Maria (UFSM) Michigan Technological University
Santa Maria, Brazil Houghton, MI 49931
Email: taimur@mail.ufsm.br∗ , cesar@ieee.org† Email: saeid@mtu.edu

Abstract—Current trends constantly increase the need for rather than charge redistribution. As an advantage, the DAC is
ultra-low power solutions for embedded and portable hardware. totally precharged once in the beginning of a conversion cycle,
One circuit component required in a wide range of devices is instead of per bit active interactions with the supply lines. Still,
the analog-to-digital converter (ADC). In this paper we propose
an extremely energy-efficient successive approximation register the settling requirements for DAC can be relaxed during de-
(SAR) ADC, in which we have overcome the limitations of con- sign cycle, and most importantly, avoiding any power-hungry
ventional approaches through topological improvements. Further opamp buffering the reference signal. Misleadingly, this opamp
advances include the implementation of a custom controller and is often not accounted for in the energy measurement of a
a novel bootstrapped track and hold (T/H) circuitry. Statistical given converter, which could be significant.
simulations indicate an ADC with a figure of merit (FOM) of 11.9
fJ per conversion step, and an effective number of bits (ENOB) In this paper we implement a 10-bit charge sharing ADC,
of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. with topological improvements over the reference paper in [1].
To put it into perspective, consuming only 7 pJ/sample, this ADC Its operation is described in Section II. Furthermore, we have
is able to work at its maximum speed for more than 40 years improved the inner circuit blocks. A modified T/H circuitry
with the total energy of a single alkaline AA battery.
is proposed, employing bootstrapped switches to achieve the
I. Introduction linearity required for the 10-bit ADC. In this paper we have
significantly decreased the contribution of digital controller
A tight power budget is present in an ever increasing to the overall energy by taking an extremely efficient custom
range of applications. New trends and emerging technologies approach to logic design based on true single phase clock
often focus on miniaturization and portability, bringing devices (TSPC) latches with embedded combinational logic and taking
which are mostly battery-powered. Therefore, in order to advantage of inherent parasitics to retain control signals. The
increase battery lifetime, every block in a system in this complete description of each circuit block, with additional
environment must consume the minimum possible energy. information on their implementation is presented in Section
One required circuit for a wide range of low-power appli- III. In order to validate the ADC and extract the reliable
cations is the analog-to-digital converter (ADC). Among the circuit parameters, we carried out statistical simulations. The
diversity of available topologies, the successive approximation simulation environment and procedures with the achieved
register (SAR) is well-known for its energy efficiency. It is results are expounded in Section IV. Conclusions are drawn
very attractive in applications which demand low data-rates, in Section V.
with tight power constraints, mainly due to the logarithmic
dependence of architecture on the resolution. II. Operation Principle
Based on a feedback loop, the SAR converter converges
iteratively to the final digital word, comparing the value of a Similar to charge redistribution ADCs, the charge sharing
digital-to-analog converter (DAC) to a sampled representation based architecture requires a controller, a voltage comparator,
of the input signal, captured with a track and hold (T/H) and a DAC. However, due to its working principle, it also
circuit. The conversion cycle is guided by the binary search requires a track and hold circuitry, as the sampled signal
algorithm. cannot be held on the DAC capacitances. The topology is
Conventional SAR ADCs rely on the charge redistribution depicted in Fig. 1.
(CR) method, so-called due to the DAC topology they employ. A conversion takes place on the falling edge of the reset
In that approach, the capacitive DAC is also used as tracking input. While this input is low, the T/H circuit is tracking the
circuit, and at every step, one of the binary-weighted capacitors input, whereas the DAC is being precharged. For the 10-bit
is tied to ground or reference terminal, leading the error converter described here, the DAC consists of 10 capacitors
voltage to diminish towards zero. with binary-weighted values of charge. During the precharge
In the inspiring work in [1], authors present a method to cycle, these capacitances are tied to reference voltage Vref , and
implement capacitive SAR based on charge sharing (CS), disconnected from T/H capacitors and each other. When reset
 Fig. 1. ADC blocks diagram and illustrative waveforms

is returned to high logic level, the input signal tracked on T/H

is held steady, and DAC is disconnected from Vref .
Next, the SAR circuit starts performing the binary search
algorithm adding or subtracting charge to or from the sampling
capacitors. On the next rising edge of the clock, comparator
is initiated to compare voltages Vp and Vn . The comparison
result is the most significant bit (MSB) of actual conversion.
Subsequently, some charge must be added or subtracted on
these nodes, in order to make the voltage difference (error
voltage) between Vp and Vn smaller. If, for instance, Vp
Fig. 2. Charge pump proposed switch
is evaluated larger than Vn , we remove an MSB-equivalent
(one half) amount of charge from sampling capacitors, by
The 10-bit resolution chosen for this ADC imposes stringent
turning on control signal cn9. Therefore, capacitor C9 would
linearity constraints on the T/H, as the overall ADC linearity
be connected anti-parallel to the series arrange of Csp and Csn .
is dependent on the T/H linearity. Therefore, in order to meet
If, on the other hand, Vp was smaller than Vn , the same amount
the fundamental linearity constraints for 10-bit resolution, we
of charge would be added C9 by being placed in parallel to the
have employed a novel bootstrapped switch, based on [4], as
sampling capacitances, by turning the control signal cp9 on.
shown in Fig. 2.
The process progressively repeats for the other bits, adding or
When signal reset is low, capacitor C1 is precharged to the
subtracting charge to/from the sampled charge from Vin . At
drain voltage VD minus diode D1 forward-biased voltage drop.
the end, cn(9...0) represents the desired 10-bit output.
Because of inverter U1 , n-MOS N1 is turned on, transferring
III. Circuits the zero voltage signal reset to the gate of Nswitch , therefore,
turning this switch off. If, on the other hand, reset signal is
In this section, we describe the working principle and the high, the inverter U1 outputs zero voltage, turning P1 on. As a
underlying design details of each one of the blocks inside the result, P1 delivers the sum of previously charged C1 and reset
ADC. node voltages (VC1 + Vreset ). The process is shown in Fig. 2.
In order to avoid channel modulation effect and its impact on
A. Track and Hold
linearity, we have employed p-well inside a deep n-well for
The power consumption of T/H circuit must be compatible Nswitch and tied its bulk and source together.
to a low-energy design. Despite of the fact that some complex Simulations of the T/H circuitry, with the bootstrapping
T/H topologies had been explored for charge sharing ADC through the simple arrangement of MOS switch and capacitor,
([1]–[3]), a very efficient approach is the simple arrangement show that it presents a signal to noise and distortion ratio
of MOS switch and capacitor, shown in Fig. 2. Apart from (SNDR) of around 74 dB. This corresponds to around 12
the increased energy efficiency and reduced complexity, this effective bits, giving the design some safety margin.
circuit does not reduce the signal to noise ratio (SNR) during
charge processing because it does not divide the input sampled B. DAC
voltage by a factor of 2, as is the case in [1]. The employment The DAC consists of 10 capacitors, that are precharged
of this simple circuit means no current is drawn from the input to binary-weighted values of charge in the beginning of
signal when the ADC is not effectively tracking the input. conversion cycle. During the conversion, these charge values
This is different from the cited approaches, where there is are added or subtracted to/from the sampled signal, in order
always one set of capacitors sampling the input and, therefore, to realize binary search algorithm. The circuit, with charge
consuming power. To avoid the use of a low-impedance buffer sharing switches cn(9...0) and cp(9...0) omitted, is shown in
on the input, the tracking time can be adjusted to march the Fig. 3.
input signal strength, by changing the time the signal reset is For this specific design, the capacitors mismatch is dominant
kept low. over thermal noise, so unitary capacitor were dimensioned to
 Fig. 3. DAC Circuit Schematic

fulfill linearity constraints. However, for the 10-bit accuracy

keeping σDNL < 0.2, the unit capacitance is smaller than
Fig. 4. Comparator circuit
the minimum size metal-metal capacitor design rule for the
technology. To overcome this limitation, we kept the charge
controller block. Some recent designs report the controller
proportionality on the least significant bits (LSBs) by first
contribution to be responsible to roughly 50% of the overall
precharging C2 to Vref and than redistributing its charge to C1
ADC power [1], [5]. To significantly reduce energy, we
and C0 , iteratively. This sharing on LSBs happens concurrently
propose a novel custom controller for charge sharing ADC. It
to conversion, and does not require extra clock periods.
relies on true single phase clock (TSPC) latch, with embedded
While the reset signal is low, the DAC remaining capacitors
combinatorial logic. Moreover, we exploit the CMOS inherent
C9 − C3 are tied to Vref through n-MOS and p-MOS transis-
parasitics to retain the control signals. Full-custom logic
tors on the bottom and top plates, respectively. The binary
controller has already been used in SAR ADCs, like in [6].
weighted relation is also kept for the transistors width. Doing
The controller is composed of 10 identical slices, as shown
so, the charge-injection on the DAC capacitors, when these
in Fig. 5. The circuit drains no static current and has been
transistors are turned off, does not lead to non-linearities in
implemented with high threshold low leakage transistors. Also
the ADC. Since the injected charge from the transistor gate is
notice that even though the proposed ADC is synchronous,
a direct function of its area, it is beneficial to inject a charge
the controller does not depend on the clock signal. Therefore,
proportional to the value of each capacitor, leading to the same
the same circuit may be employed without any adaption in
voltage increase on every capacitor. It has the same effect of a
an asynchronous ADC. In that case, the only modifications
constant offset on Vref for every conversion, and it is naturally
should be made to the comparator, changing the way it is
a linear process.
activated; based on the clock signal for our design, or based
The charge sharing switches (cn(9...0) and cp(9...0)), are
on certain delay after a valid comparison for the asynchronous
implemented using transmission gates, to decrease their re-
alternative.
sistance over the full signal range. Different from the charge
redistribution technique, once connected to the sampled input IV. Simulation Results
signal, capacitors are not disconnected until the end of con- In order to compensate for the absence of a prototype
version. Since there is no transistor turn-off during this period, chip and extract reliable results, we have employed extensive
there is also no charge-injection from cp and cn transistors. Monte-Carlo (MC) simulations. This was only feasible due to
C. Comparator the reduced number of transistors in the controller logic block,
From the energy point of view, the comparator must con- when compared to standard logic approach employed in other
sume very little or no power while not performing a compar- designs. Using the full-custom controller the time required
ison. The other requirements include a minimum offset, since to run a 512 points transient analysis with transient noise
the charge sharing SAR is much more sensitive to this non- was around 2.5 hours on an 8-core processor machine. For
ideality, as it manifests as non-linearity. Moreover, the noise every run (30 random seeds) in the Monte Carlo simulation,
will limit the size and power consumption of the comparator. the important parameters were extracted, and their mean and
Different from other charge sharing designs ([1]–[3]), we standard deviation calculated. Average effective number of bits
decided against the inclusion of calibration feature for this (ENOB) and its standard deviation for different sinusoidal
ADC. The relative low data-rate chosen as a design parameter inputs along the frequency range of the converter are plotted
enables us to accept larger devices on the comparator in order in Fig. 6.
to increase the matching and, consequently, reduce offset. Unfortunately, the converter has some performance degrada-
Trading off speed and matching, we get an standard deviation tion in higher range of frequencies. The linearity loss is caused
in the offset voltage σoffset in the micro volts range. Fig. 4 by the track and hold circuit, that is not able to respond well
shows the differential latched comparator topology, together on low duty-cycles. Fig. 7 shows an FFT plot for the ADC
with the comparator controller block. for a 41 kHz 1 V peak to peak signal.
Regarding the power consumption, sampling at 1 MSps,
D. Custom Controller the converter consumes 7 µW from a 1 V supply source. The
Most of the SAR ADCs reported to-date the employ stan- power distribution among the blocks is as follows; comparator
dard cell CMOS design methodology to implement the digital 2.4%, controller 2%, T/H circuit 1.4%, DAC precharge 94.2%.
 Fig. 5. Logic blocks diagram and custom controller slice circuit schematic
TABLE I
Comparison with state-of-the-art designs
Parameter [1] [2] [5] [6] This work
Technology 90nm 90nm 65nm 90nm 90nm
Bits 9 9 10 8 10
ENOB 7.8 8.23 8.75 7.8 9.2
Samples/s 50M 40M 1M 10M 1M
Fig. 6. ENOB mean and standard deviation as a function of input frequency Power(µW) 700 820 1.9 69 7
J
FOM( conv.step ) 65f 54f 4.4f 30f 11.9f

V. Conclusions
In this paper, we successfully designed a state-of-the art
ADC with extreme energy efficiency. The results place this
design in the leading edge of ultra-low energy ADCs.
Fig. 7. FFT Plot with harmonics for a 41 kHz input signal To illustrate the power scale, we compare the energy nec-
essary for a single conversion of the ADC to the amount of
It is important to consider that parasitics were not accounted energy available in a conventional AA alkaline battery [7].
in the simulation, and the power consumption may increase Working at full 1 MSps speed, the converter is theoretically
slightly in the physical design. Fig. 8 shows the energy able to work for 40 years with 9000 Joules.
dissipated by each one of the circuit blocks during a complete References
conversion cycle, within 1 µs. The energy needed to precharge
[1] J. Craninckx and G. Van der Plas, “A 65fJ/conversion-step 0-to-50MS/s
the DAC by far surpasses the other blocks energy. 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS,”
A commonly used figure of merit (FOM), is defined as, in Proceedings of IEEE International Solid-State Circuits Conference
(ISSCC), Digest of Technical Paper, San Francisco, CA, USA, February
P 2007, pp. 246 –600.
FOM = (1) [2] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and
2ENOB F s J. Craninckx, “An 820µW 9b 40MS/s noise-tolerant dynamic-SAR ADC
where P is total power and F s the sampling frequency. Using in 90nm digital CMOS,” in Proceedings of IEEE International Solid-State
Circuits Conference, (ISSCC), Digest of Technical Paper, February 2008,
(1), the proposed ADC achieved a FOM of 11.9 fJ/conv. pp. 238 –610.
step, with the 9.2-bit ENOB at nearly Nyquist frequency. We [3] T. Kuntz and S. Nooshabadi, “An energy-efficient successive approxi-
compare our design to other state-of-the art ADCs in Table I. mation register analog to digital converter in 180nm,” in Proceedings of
IEEE Asia Pacific Conference On Circuits And Systems, 2010, (APCCAS
2010), vol. To be Published, December 2010.
[4] M. Scott, B. Boser, and K. Pister, “An ultralow-energy ADC for Smart
Dust,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1123 –
1129, July 2003.
[5] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink,
and B. Nauta, “A 1.9µW 4.4fJ/conversion-step 10b 1MS/s charge-
redistribution ADC,” in Proceedings of IEEE International Solid-State
Circuits Conference (ISSCC), Digest of Technical Paper, San Francisco,
CA, USA, February 2008, pp. 244 –610.
[6] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A
30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm
CMOS,” in Proceedings of IEEE International Solid-State Circuits Con-
ference (ISSCC), Digest of Technical Paper, San Francisco, CA, USA,
February 2010, pp. 388 –389.
[7] Energizer, “Energizer E91 AA alkaline battery datasheet,”
http://data.energizer.com/PDFs/E91.pdf, September 2010.

Fig. 8. Energy versus time for each circuit block in the ADC