Functional Mode (Func Mode) in VLSI design is the chip's primary operating state—the
configuration in which it performs its intended, real-world function. Here’s a concise
overview:
Operational Definition: Defined by specific clocks, supply voltages, timing
constraints, libraries, and sometimes annotation data (e.g., SDF or parasitics),
functional mode reflects the chip’s normal operating environment.
Purpose: It ensures that the chip meets performance and power targets under nominal
conditions, guiding optimization and verification efforts.
Verification: Static Timing Analysis (STA) in functional mode assesses whether
critical paths meet the required setup and hold times under typical conditions.
Design Focus: Optimizations such as clock tree synthesis, routing, and cell placement
are all centered around ensuring robust operation in functional mode.
In short, func mode is essential for verifying that the chip will behave correctly and
efficiently in its day-to-day application.
Input files for functional mode:
When performing functional mode analysis—especially during Static Timing Analysis (STA)
—several input files ensure that the design is accurately modeled under nominal operating
conditions. Here’s a concise overview of the typical input files used for functional mode:
1. Constraint Files (SDC):
o Contents: Clock definitions, timing constraints, input/output delays, multicycle
and false-path constraints, etc.
o Purpose: Define the operational environment and guide STA to verify setup,
hold, and other timing parameters under functional conditions.
2. Standard Cell Libraries (Liberty Files, .lib):
o Contents: Timing, power, and noise characterization for the standard cells
(typically measured under nominal conditions like TT).
o Purpose: Provide the delay and transition information for every cell used in the
design.
3. Netlist Files:
o Contents: Synthesized or extracted netlist (Verilog, VHDL, EDIF)
representing the logical connectivity of the circuit.
o Purpose: Serve as the circuit’s backbone for timing analysis by detailing how
cells are interconnected.
4. Physical Design Files (Optional, e.g., LEF/DEF):
o Contents: Abstract floorplan (LEF), placement, and routing details included in
DEF or related formats.
o Purpose: Enhance STA accuracy by incorporating physical information, such
as wire lengths and routing parasitics.
5. Annotation Files (e.g., SDF or Parasitic Files):
o Contents: Delay annotations that capture additional physical delays from
parasitic extraction.
o Purpose: Refine the netlist timing data by matching the physical reality of the
design, leading to tighter timing closure.
Here’s a summary of these inputs in a table:
Test Mode in VLSI design is a dedicated operating configuration created to facilitate
chip testing, diagnostics, and quality assurance during manufacturing. It differs significantly
from functional mode in that it prioritizes testability over everyday performance. Here are the
key aspects and inputs that define test mode:
Key Characteristics
Design-for-Test (DFT) Features: Test mode often incorporates specialized circuits
and structures such as scan chains, Built-In Self-Test (BIST) routines, and JTAG
interfaces. These features allow for controlled signal shifting and easier fault
detection.
Modified Clocking: Clocks in test mode may be altered—usually run at a slower rate
—to accommodate sequential scan operations. This ensures that the test infrastructure
can reliably capture and shift data without timing issues.
Tailored Constraints and Timing: The timing constraints for test mode are generally
relaxed or adjusted to account for extra delay introduced by test logic. For example,
the setup and hold margins might be slightly redefined to handle the slower
operational speeds during test cycles.
Additional Input Files: In a typical test mode configuration, you might have
specialized constraint files (often separate from those used in functional mode) that
define:
o Test-specific clock definitions and their frequency adjustments.
o Input/output timing constraints modified for shift operations.
o Test pattern constraints ensuring that scan chains and BIST elements are
adequately exercised.
Power and Biasing Considerations: Test mode may also specify different power
settings or enable additional voltage domains required during testing. This is essential,
as testing can temporarily lead to simultaneous activation of many circuit paths,
potentially stressing the power distribution network.
Inputs of test mode
1. Test Vectors: A set of predefined input patterns used to simulate and validate the
chip's operation against expected outputs.
2. Test Enable Signal: A signal that activates test mode, bypassing normal operational
modes to allow for testing-specific configurations.
3. Clock Signals: A precise clock is critical for timing analysis and ensures
synchronized testing of sequential circuits.
4. Scan Chain Inputs: If scan design (e.g., scan flip-flops) is implemented, the scan
input is required to shift test patterns through the scan chain.
5. Power and Ground: Stable power supplies ensure the chip operates correctly during
testing.
6. Reset Signals: These bring the design to a known state before initiating test mode.
7. Control Signals for Boundary-Scan or JTAG: If boundary-scan techniques are
used, signals like TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), and
TDO (Test Data Out) are essential.
Test mode inputs will vary depending on the type of testing, such as Built-In Self-Test
(BIST), functional testing, or fault coverage analysis.
Below is a concise comparison between Functional Mode and Test Mode in VLSI design:
Functional Mode defines the chip’s regular working state—optimized for
performance, power, and reliability.
Test Mode introduces dedicated test structures and may adjust timing, voltage, or
clocking constraints to enable thorough testing and fault coverage.
