MTP60N06HD

Preferred Device

Power MOSFET
60 Amps, 60 Volts
N–Channel TO–220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
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offers a drain–to–source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly 60 AMPERES
well suited for bridge circuits where diode speed and commutating 60 VOLTS
safe operating areas are critical and offer additional safety margin RDS(on) = 14 mΩ
against unexpected voltage transients.
• Avalanche Energy Specified
N–Channel
• Source–to–Drain Diode Recovery Time Comparable to a Discrete D
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
G

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

S
Rating Symbol Value Unit
Drain–Source Voltage VDSS 60 Vdc
MARKING DIAGRAM
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc & PIN ASSIGNMENT
Gate–Source Voltage 4
– Continuous VGS ± 20 Vdc 4 Drain
– Non–Repetitive (tp ≤ 10 ms) VGSM ± 30 Vpk
Drain Current – Continuous ID 60 Adc
– Continuous @ 100°C ID 42.3
– Single Pulse (tp ≤ 10 µs) IDM 180 Apk TO–220AB
CASE 221A
Total Power Dissipation PD 150 Watts STYLE 5 MTP60N06HD
Derate above 25°C 1.0 W/°C LLYWW
Operating and Storage Temperature TJ, Tstg –55 to °C 1
Range 175 2 1 3
3
Gate Source
Single Pulse Drain–to–Source Avalanche EAS 540 mJ
Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak 2
IL = 60 Apk, L = 0.3 mH, RG = 25 Ω) Drain
Thermal Resistance °C/W
MTP60N06HD = Device Code
– Junction to Case RθJC 1.0
LL = Location Code
– Junction to Ambient RθJA 62.5
Y = Year
Maximum Lead Temperature for Soldering TL 260 °C WW = Work Week
Purposes, 1/8″ from case for 10
seconds
ORDERING INFORMATION

Device Package Shipping

MTP60N06HD TO–220AB 50 Units/Rail

Preferred devices are recommended choices for future use

and best overall value.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

November, 2000 – Rev. 3 MTP60N06HD/D
 MTP60N06HD

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3.) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc) 60 – –
Temperature Coefficient (Positive) – 71 – mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) – – 100
Gate–Body Leakage Current IGSS nAdc
(VGS = ± 20 Vdc, VDS = 0 Vdc) – – 100
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage (Cpk ≥ 3.0) (Note 3.) VGS(th) Vdc
(VDS = VGS, ID = 250 µAdc) 2.0 3.0 4.0
Threshold Temperature Coefficient (Negative) – 7.0 – mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 3.0) (Note 3.) RDS(on) Ohm
(VGS = 10 Vdc, ID = 30 Adc) – 0.011 0.014
Drain–to–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 60 Adc) – – 1.0
(ID = 30 Adc, TJ = 125°C) – – 0.9
Forward Transconductance gFS mhos
(VDS = 5.0 Vdc, ID = 30 Adc) 15 20 –
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss – 1950 2800 pF
Output Capacitance (VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
Coss – 660 924
f = 1.0 MHz)
Transfer Capacitance Crss – 147 300
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time td(on) – 14 26 ns
Rise Time (VDD = 30 Vdc, ID = 60 Adc, tr – 197 394
VGS = 10 Vdc,
Vdc
Turn–Off Delay Time RG = 9.1 Ω) td(off) – 50 102
Fall Time tf – 124 246
Gate Charge
g QT – 51 71 nC
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 60 Adc, Q1 – 12 –
VGS = 10 Vdc) Q2 – 24 –
Q3 – 21 –
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (IS = 60 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 60 Adc, VGS = 0 Vdc, – 0.99 1.2
TJ = 125°C) – 0.89 –
Reverse Recovery
y Time trr – 60 – ns
(S Figure
(See Fi 15)
(IS = 60 Adc, VGS = 0 Vdc, ta – 36 –
dIS/dt = 100 A/µs) tb – 24 –
Reverse Recovery Stored Charge QRR – 0.143 – µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from contact screw on tab to center of die) – 3.5 –
(Measured from the drain lead 0.25″ from package to center of die) – 4.5 –
Internal Source Inductance LS nH
(Measured from the source lead 0.25″ from package to source bond pad) – 7.5 –
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA

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 MTP60N06HD

TYPICAL ELECTRICAL CHARACTERISTICS

120 120
VGS = 10 V 8V 7V VDS ≥ 10 V
100 100

I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

9V
80 TJ = 25°C 80

60 6V 60

40 40

5V 100°C 25°C
20 20
TJ = -55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.8 3.6 4.4 5.2 6.0 6.8 7.6
VDS, DRAIN-TO-SOURCE VOLTAGE (Volts) VGS, GATE-TO-SOURCE VOLTAGE (Volts)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.020 0.0132
VGS = 10 V TJ = 25°C
0.018 0.0128
TJ = 100°C
0.0124
0.016
0.0120
0.014 VGS = 10 V
0.0116
0.012 25°C
0.0112
0.010
0.0108
-55°C 15 V
0.008 0.0104

0.006 0.0100
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
ID, DRAIN CURRENT (Amps) ID, DRAIN CURRENT (Amps)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

1.8 1000
R DS(on) , DRAIN-TO-SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
1.6 ID = 30 A
TJ = 125°C
I DSS, LEAKAGE (nA)

1.4 100
(NORMALIZED)

1.2 100°C
25°C
1.0 10

0.8

0.6 1
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

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 MTP60N06HD

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off–state condition when
controlled. The lengths of various switching intervals (∆t) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on–state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain–gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
t = Q/IG(AV) complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG – VGSP) resistance (Figure 9) shows how typical switching
tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If
where the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG
The circuit used to obtain the data is constructed to minimize
RG = the gate drive resistance
common inductance in the drain and gate circuit loops and
and Q2 and VGSP are read from the gate charge curve.
is believed readily achievable with board mounted
During the turn–on and turn–off delay times, gate current is components. Most power electronic loads are inductive; the
not constant. The simplest calculation uses appropriate data in the figure is taken with a resistive load, which
values from the capacitance curves in a standard equation for approximates an optimally snubbed inductive load. Power
voltage change in an RC network. The equations are: MOSFETs may be safely operated into an inductive load;
td(on) = RG Ciss In [VGG/(VGG – VGSP)] however, snubbing reduces switching losses.
td(off) = RG Ciss In (VGG/VGSP)

5000
VDS = 0 V VGS = 0 V
Ciss TJ = 25°C
4000
C, CAPACITANCE (pF)

3000
Crss
Ciss
2000

Coss
1000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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 MTP60N06HD

12 60 1000
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
10 50 ID = 60 A
VGS VGS = 10 V
TJ = 25°C
8 40 tr
Q1 Q2
tf

t, TIME (ns)
6 30 100

4 ID = 60 A 20 td(off)
TJ = 25°C
2 10
Q3
VDS td(on)
0 0 10
0 8 16 24 32 40 48 56 1 10 100
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 12. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by
60
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)

50

40

30

20

10

0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

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 MTP60N06HD

di/dt = 300 A/µs Standard Cell Density

trr
High Cell Density

I S , SOURCE CURRENT
trr
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain–to–source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and must be adjusted for operating
forward biased. Curves are based upon maximum peak conditions differing from those specified. Although industry
junction temperature and a case temperature (TC) of 25°C. practice is to rate in terms of energy, avalanche energy
Peak repetitive pulsed power limits are determined by using capability is not a constant. The energy rating decreases
the thermal response data in conjunction with the procedures non–linearly with an increase of peak current in avalanche
discussed in AN569, “Transient Thermal Resistance – and peak junction temperature.
General Data and Its Use.” Although many E–FETs can withstand the stress of
Switching between the off–state and the on–state may drain–to–source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded, and that the continuous current (ID), in accordance with industry
transition time (tr, tf) does not exceed 10 µs. In addition the custom. The energy rating must be derated for temperature
total power averaged over a complete switching cycle must as shown in the accompanying graph (Figure 13). Maximum
not exceed (TJ(MAX) – TC)/(RθJC). energy at currents below rated continuous ID can safely be
A power MOSFET designated E–FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

1000 600
EAS, SINGLE PULSE DRAIN-TO-SOURCE

VGS = 20 V ID = 60 A
SINGLE PULSE
500
TC = 25°C
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)

100 10 µs 400

300
100 µs
10 200
1 ms
RDS(on) LIMIT 10 ms
THERMAL LIMIT 100
PACKAGE LIMIT dc
1 0
0.1 1.0 10 100 25 50 75 100 125 150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

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 MTP60N06HD

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
(NORMALIZED)

0.1
0.1 P(pk)
0.05 RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
0.02 PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01
t2 TJ(pk) - TC = P(pk) RθJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 15. Diode Reverse Recovery Waveform

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 MTP60N06HD

PACKAGE DIMENSIONS

TO–220 THREE–LEAD
TO–220AB
CASE 221A–09
ISSUE AA

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U C 0.160 0.190 4.07 4.82
H D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 --- 1.15 ---
Z --- 0.080 --- 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

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