Question 1 309

a) Distinguish between computer organization and computer function.

 Computer Organization: Refers to the physical and structural aspects of a
computer system, including hardware components (e.g., CPU, memory, buses) and
their interconnections. It focuses on how the system is built and operates at a low
level.
 Computer Function: Refers to the operations or tasks a computer performs, such
as data processing, storage, and input/output. It focuses on what the computer does,
regardless of its physical structure.
b) Explain briefly the functional components of a computer.
 Central Processing Unit (CPU): Executes instructions by performing arithmetic,
logical, control, and input/output operations.
 Memory: Stores data and instructions; includes primary (RAM, ROM) and secondary
(HDD, SSD) storage.
 Input Devices: Allow data entry (e.g., keyboard, mouse).
 Output Devices: Display or produce results (e.g., monitor, printer).
 Bus System: Connects components for data transfer, including data, address, and
control buses.
c) Explain the concept of the von Neumann computer.
The von Neumann architecture is a computer design model where a single memory stores
both program instructions and data. Key features include:
 A CPU with an arithmetic logic unit (ALU) and control unit.
 A single memory for instructions and data, accessed via a bus.
 Sequential instruction execution (fetch-decode-execute cycle).
 This model, introduced by John von Neumann in 1945, is the basis for most modern
computers but has a bottleneck due to shared memory access.
d) State the sequence of operations of the control unit in one clock pulse.
 Fetch: Retrieve the next instruction from memory using the program counter (PC).
 Decode: Interpret the instruction to determine the required operation.
 Execute: Generate control signals to perform the operation (e.g., ALU computation
or memory access).
 Update PC: Increment the program counter to point to the next instruction.
Question 2
b) State the basic functions that a computer can perform.
 Data Input: Accept data from input devices.
 Data Processing: Perform arithmetic or logical operations.
 Data Storage: Store data in memory or secondary storage.
 Data Output: Display or transmit results via output devices.
Question 3
a) Write short notes on:
i. ROM (Read-Only Memory):
 Non-volatile memory that stores permanent data, such as firmware or BIOS.
 Data is written during manufacturing and cannot be easily modified.
 Used for boot-up instructions and critical system software.
ii. RAM (Random Access Memory):
 Volatile memory that stores data and instructions temporarily during program
execution.
 Allows fast read/write access but loses data when power is off.

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  Types include SRAM (static) and DRAM (dynamic).
iii. Computer Architecture:
 The design and organization of a computer system, including CPU, memory, buses,
and instruction set.
 Defines how hardware and software interact to execute tasks.
 Examples include von Neumann and Harvard architectures.
b) Evaluate using two’s complement:
i. 0000 0101 – 0000 1000
 0000 0101 = +5, 0000 1000 = +8.
 Subtraction: 5 – 8 = 5 + (–8).
 Two’s complement of 8: Invert 0000 1000 → 1111 0111, add 1 → 1111 1000.
 Add: 0000 0101 + 1111 1000 = 1111 1101.
 1111 1101 is negative (MSB=1). Two’s complement: Invert → 0000 0010, add 1 →
0000 0011 = 3.
 Answer: 1111 1101 = –3.
ii. 0000 0111 – 0000 0011
 0000 0111 = +7, 0000 0011 = +3.
 Subtraction: 7 – 3 = 7 + (–3).
 Two’s complement of 3: Invert 0000 0011 → 1111 1100, add 1 → 1111 1101.
 Add: 0000 0111 + 1111 1101 = 0000 0100 (discard carry).
 Answer: 0000 0100 = +4.
Question 4
a) Evaluate using two’s complement, expressing answers in binary:
i. 17₁₀ – 10₁₀
 17₁₀ = 0001 0001, 10₁₀ = 0000 1010.
 Subtraction: 17 – 10 = 17 + (–10).
 Two’s complement of 10: Invert 0000 1010 → 1111 0101, add 1 → 1111 0110.
 Add: 0001 0001 + 1111 0110 = 0000 0111 (discard carry).
 Answer: 0000 0111 = +7.
ii. 9₁₀ + 11₁₀
 9₁₀ = 0000 1001, 11₁₀ = 0000 1011.
 Add: 0000 1001 + 0000 1011 = 0001 0100.
 Answer: 0001 0100 = +20.
b) Outline the 4 categories of micro-operations.
 Register Transfer: Move data between registers (e.g., R1 ← R2).
 Arithmetic: Perform calculations like addition or subtraction in the ALU.
 Logic: Execute logical operations (e.g., AND, OR, NOT) on data.
 Shift: Shift bits in a register left or right (e.g., logical or arithmetic shifts).
Question 5
a) Explain the difference between hardwired control and microprogrammed control.
 Hardwired Control:
 Uses fixed hardware circuits (e.g., combinational logic) to generate control
signals.
 Faster due to direct hardware implementation.
 Difficult to modify or debug; suited for simple systems.
 Microprogrammed Control:
 Uses microinstructions stored in control memory to generate control signals.
 Slower due to memory access but easier to modify or update.

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  Flexible, used in complex systems like CISC processors.
b) Enumerate the characteristics of RISC architectures.
 Simple Instructions: Single-cycle, fixed-length instructions.
 Large Register Set: Many registers to minimize memory access.
 Load/Store Architecture: Only load/store instructions access memory.
 Pipelining: Overlaps instruction execution for efficiency.
 Hardwired Control: Often uses hardwired control for speed.
Question 6
a) Differentiate between:
i. Control Bus: Carries control signals from the control unit to coordinate operations (e.g.,
read/write signals). ii. Address Bus: Transmits memory addresses to specify data locations.
iii. Data Bus: Transfers actual data between CPU, memory, and peripherals. iv. Karnaugh
Map: A graphical tool to simplify Boolean expressions by grouping minterms. v. Boolean
Algebra: A mathematical system for manipulating logical expressions using AND, OR, NOT
operations.
b) List and explain three performance parameters in computer memory.
 Access Time: Time taken to read/write data; lower is better (e.g., DRAM ~50ns).
 Bandwidth: Rate of data transfer (e.g., GB/s); higher improves performance.
 Latency: Delay between request and data delivery; lower reduces wait time.
Question One
1a. i. Discuss three characteristics of reduced instruction set architectures (RISC).
 Simplified Instructions: RISC uses a small set of simple, fixed-length instructions
that execute in a single clock cycle, enabling faster processing and easier decoding.
 Register-Based Operations: Most operations are performed on registers, with only
load/store instructions accessing memory, reducing memory access latency.
 Pipelining Support: RISC architectures are designed for efficient pipelining,
allowing multiple instructions to be processed concurrently, improving throughput.

1a. ii. Enumerate ten characteristics considered typical of a classic RISC.

 Fixed-length instructions (e.g., 32 bits).
 Single-cycle execution for most instructions.
 Large general-purpose register set (e.g., 32 registers).
 Load/store architecture (memory access via specific instructions).
 Simple addressing modes (e.g., register, immediate).
 Hardwired control unit for faster execution.
 Pipelined instruction execution for efficiency.
 Reduced instruction set (fewer, simpler instructions).
 Emphasis on compiler optimization to generate efficient code.
 High clock speeds enabled by simplified design.

1b. i. Explain briefly Sequential Access.

Sequential access is a method of accessing data in a linear, sequential order, where each
data unit must be read or written in sequence (e.g., on magnetic tapes). It is slower than
random access because accessing a specific data item requires traversing all preceding
data.
1b. ii. Explain the following terms:
i. Memory Address Register (MAR): Stores the address of the memory location to be
accessed for reading or writing data during CPU operations. ii. Memory Buffer Register

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(MBR): Temporarily holds data being transferred between the CPU and memory, serving as
a buffer during read/write operations. iii. Program Counter (PC): Contains the memory
address of the next instruction to be fetched and executed by the CPU. iv. Instruction
Register (IR): Holds the current instruction being decoded and executed by the CPU.
1d. i. Explicitly explain Program Execution
Program execution is the process of running a program stored in memory, involving:
 Fetch: The CPU retrieves an instruction from memory using the address in the
Program Counter (PC).
 Decode: The instruction in the Instruction Register (IR) is interpreted to determine
the required operation.
 Execute: The CPU performs the operation, such as arithmetic calculations, memory
access, or I/O tasks.
 Update: The PC is incremented to point to the next instruction, and results are
stored in registers or memory. This fetch-decode-execute cycle repeats until the
program terminates.

Question Two
2a. i. How did users submit instructions written in FORTRAN?
Users wrote FORTRAN programs on punch cards or paper tape, which were physically fed
into a card or tape reader connected to the computer. The system compiled the FORTRAN
code into machine language, typically processed in batch mode on mainframe computers.
2a. ii. What are Gates?
Gates are fundamental digital circuit components that perform basic logical operations (e.g.,
AND, OR, NOT, XOR, NAND). Built using transistors, they process binary inputs (0 or 1) to
produce a single binary output, forming the basis of all digital systems, including CPUs and
memory.
2a. iii. What is Design in Digital Circuitry?
Design in digital circuitry is the process of creating electronic circuits to process binary data
using logic gates, flip-flops, and other components. It involves defining requirements,
designing logic schematics, optimizing circuits (e.g., using Boolean algebra or Karnaugh
maps), and verifying functionality through simulation or testing.
2b. i. Discuss resource ownership of explicit multithreading.
Explicit multithreading (e.g., Simultaneous Multithreading or SMT) allows multiple threads to
share processor resources concurrently:
 Shared Resources: Threads share execution units, caches, and pipelines,
maximizing resource utilization but potentially causing contention.
 Dedicated Resources: Each thread has its own program counter, register set, and
thread state to maintain independence.
 Dynamic Allocation: The processor allocates resources (e.g., execution slots,
cache lines) dynamically based on thread priority or workload, balancing
performance and fairness while minimizing conflicts.

2b. ii. State the three activities that occur in parallel in a Register File [3 marks].
 Reading Data: Fetching operands from multiple registers simultaneously for
instruction execution.
 Writing Data: Storing results back into registers after computation.

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  Address Decoding: Selecting specific registers for read/write operations based on
instruction operands.

2b. iii. Briefly describe Program Creation.

Program creation involves:
 Writing source code in a high-level language (e.g., C++, Python).
 Compiling the code into machine language using a compiler or interpreter.
 Linking external libraries or modules to resolve dependencies.
 Generating an executable file that can be loaded into memory for execution.

Question Three
3a. i. Write a short note on the Long-term Scheduler and enumerate the two decisions
involved when it creates processes.
The Long-term Scheduler (or job scheduler) manages the admission of processes into the
system, selecting jobs from the job queue to load into memory for execution. It controls the
degree of multiprogramming to ensure efficient resource use and system stability.
 Two Decisions:
 Which Jobs to Select: Chooses processes based on priority, resource
needs, or system policies.
 When to Admit Jobs: Determines the timing of process loading to avoid
overloading system resources.

3a. ii. Describe sequential access as it relates to methods of accessing units of data.
Sequential access involves accessing data units in a fixed, linear order, where each unit is
processed sequentially (e.g., magnetic tapes or serial streams). It requires reading or
writing all preceding data to reach a specific unit, making it slower than random access but
suitable for applications like backups or streaming where data is processed in order.
3b. i. Differentiate between long-term and short-term scheduler.
 Long-term Scheduler:
 Selects jobs from the job queue to load into memory.
 Controls the degree of multiprogramming.
 Runs infrequently, when new jobs arrive.
 Focuses on system-level resource allocation.
 Short-term Scheduler:
 Allocates CPU time to processes in the ready queue.
 Manages context switching and CPU scheduling.
 Runs frequently (e.g., every few milliseconds).
 Focuses on minimizing response time and optimizing CPU usage.

3b. ii. Differentiate between volatile and nonvolatile memory.

 Volatile Memory:
 Loses data when power is removed (e.g., RAM, cache).
 Used for temporary storage of data and instructions during execution.
 Offers fast read/write access.
 Nonvolatile Memory:
 Retains data without power (e.g., ROM, flash, SSDs).
 Used for permanent storage, such as firmware or long-term data.

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  Slower access but preserves data across power cycles.

Question Four
4a. i. List the Flynn Categorization of parallel processing system.
 SISD (Single Instruction, Single Data): One instruction processes one data stream
(e.g., traditional single-core CPUs).
 SIMD (Single Instruction, Multiple Data): One instruction processes multiple data
streams (e.g., GPUs for vector processing).
 MISD (Multiple Instruction, Single Data): Multiple instructions process one data
stream (rare, used in fault-tolerant systems).
 MIMD (Multiple Instruction, Multiple Data): Multiple instructions process multiple data
streams (e.g., multicore processors, clusters).

4a. ii. Explain the following terms:

i. Synchronization:
 Coordination of processes or threads to ensure correct execution order and prevent
data conflicts. It uses mechanisms like locks, semaphores, or barriers to manage
shared resource access and avoid race conditions.

ii. Memory Management:

 The process of allocating, tracking, and reclaiming memory for processes. It includes
virtual memory, paging, segmentation, and protection to ensure efficient use,
isolation, and security of memory resources.

4b. i. State the characteristics common to all approaches to reduced instruction set
architecture.
 Simple, fixed-length instructions for easy decoding.
 Single-cycle execution for most instructions.
 Load/store architecture, limiting memory access to specific instructions.
 Large number of registers to reduce memory operations.
 Pipelining to overlap instruction execution.
 Hardwired control for faster, simpler instruction processing.

Question Five
5a. i. Describe access time relative to a non-random-access memory context.
Access time in non-random-access memory (e.g., sequential access devices like magnetic
tapes) is the time required to locate and retrieve a specific data unit. It varies depending on
the data’s position in the sequence, as all prior data must be traversed, resulting in longer
access times compared to random-access memory.
5b. i. Discuss the term Memory Protection.
Memory protection ensures that processes access only their authorized memory regions,
preventing unauthorized access or data corruption. It is achieved through:
 Virtual Memory: Isolates process address spaces.
 Access Permissions: Enforces read/write restrictions.
 Segmentation/Paging: Divides memory into protected units, ensuring process
isolation and system security.

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5b. ii. Explain accounting information in the context of scheduling.
Accounting information records resource usage by processes (e.g., CPU time, memory
allocation, I/O operations). In scheduling, it is used to:
 Monitor and balance resource allocation among processes.
 Prioritize or terminate processes based on usage patterns.
 Support billing in multi-user systems (e.g., cloud environments).
 Optimize system performance by identifying resource-intensive processes.

5b. iii. Define Operating System and state two of OS Objectives.

 Operating System: Software that manages hardware resources and provides
services for applications, acting as an interface between users and hardware.
 Two Objectives:
 Efficient Resource Utilization: Allocate CPU, memory, and I/O resources
effectively to maximize system performance.
 User-Friendly Interface: Provide intuitive interfaces (e.g., GUI, CLI) to
simplify interaction with the system.

5b. iv. Mention four features to facilitate DMA transfers from I/O processors.
 DMA Controller: Independently manages data transfers between I/O devices and
memory.
 Bus Mastering: Allows the DMA controller to control the system bus for direct
memory access.
 Address Generation: Specifies source and destination memory addresses for
transfers.
 Interrupt Mechanism: Signals the CPU when a DMA transfer is complete.