Data Sheet

ADuM362N
3.0 kV rms 6-Channel Digital Isolator

FEATURES GENERAL DESCRIPTION

► High common-mode transient immunity: 180 kV/µs typical The ADuM362N1 is a 6-channel digital isolator based on Analog
► High robustness to radiated and conducted noise Devices, Inc., iCoupler® technology. Combining high speed, com-
► Low propagation delay plementary metal-oxide semiconductor (CMOS) and back-to-back
monolithic air core transformer technology, these isolation compo-
► 6.2 ns typical (10 ns maximum) for 5 V operation
nents provide outstanding performance characteristics and meet
► Low dynamic power consumption, <1.65 mA/ch at 1 Mbps CISPR 32/EN 55032 Class B limits at 5 Mbps. The maximum
► 2.25 V to 5.5 V level translation propagation delay is 10 ns with a pulse-width distortion of less than
► 150 Mbps maximum guaranteed data rate for 5 V operation 3 ns at 5 V operation. Channel matching is tight at 3.0 ns maximum.
► High temperature operation: 125°C The ADuM362N data channels are independent and are available
► Safety and regulatory approvals in a variety of configurations with a withstand voltage rating of
► RQ-16 [QSOP] package 3 kV rms (see Figure 17). The devices operate with the supply
► UL 1577 (pending) voltage on either side ranging from 2.25 V to 5.5 V, which provides
► VISO = 3000 VRMS for 1 minute compatibility with lower voltage systems as well as enabling voltage
► EN IEC 60747-17 (pending)
translation functionality across the isolation barrier.
► VIORM = 636 VPEAK Two different fail-safe options are available, by which the outputs
► VIOSM = 10,000 VPEAK (reinforced) transition to a predetermined state when the input power supply is
► IEC/EN/CSA 62368-1 (pending) not applied.
► IEC/CSA 60601-1 (pending)
► IEC/CSA 61010-1 (pending)
► CQC GB 4943.1 (pending)
► ±8 kV IEC 61000-4-2 ESD protection across isolation barrier
► ±4 kV HBM ESD protection on input/output pins
► Fail-safe high (N1) or low (N0) options
► 16-lead, RoHS compliant, QSOP package
APPLICATIONS
► Serial-peripheral interface (SPI) data converter isolation
► RS-485 and controller area network with flexible data rate
(CAN FD) industrial field bus isolation
► PWM controller signal isolation
► General-purpose multichannel isolation

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
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 Data Sheet ADuM362N
TABLE OF CONTENTS

Features................................................................ 1 Pin Configurations and Function Descriptions.....13

Applications........................................................... 1 Typical Performance Characteristics................... 14
General Description...............................................1 Theory of Operation.............................................15
Functional Block Diagram......................................3 Truth Table....................................................... 16
Specifications........................................................ 4 Applications Information...................................... 17
Electrical Characteristics—5 V Operation.......... 4 Printed Circuit Board (PCB) Layout..................17
Electrical Characteristics—3.3 V Operation....... 6 Propagation Delay Related Parameters...........17
Electrical Characteristics—2.5 V Operation....... 8 Jitter Measurement...........................................17
Insulation Characteristics ................................ 10 Insulation Lifetime............................................ 17
Regulatory Information..................................... 11 Outline Dimensions............................................. 19
Recommended Operating Conditions.............. 11 Ordering Guide.................................................20
Absolute Maximum Ratings.................................12 Evaluation Boards............................................ 20
Electrostatic Discharge (ESD) Ratings.............12 Automotive Products........................................ 20
ESD Caution.....................................................12

REVISION HISTORY

9/2024—Revision 0: Initial Version

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 Data Sheet ADuM362N
FUNCTIONAL BLOCK DIAGRAM

Figure 1. ADuM362N Functional Block Diagram

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 Data Sheet ADuM362N
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation
range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 1. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within pulse-width distortion (PWD) limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 6.2 10 ns 50% input to 50% output
Pulse-Width Distortion PWD 0.3 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.1 ns Between any two units at the same temperature,
voltage, and load
Channel Matching
Codirectional tPSKCD 0.3 3.0 ns
Opposing Direction tPSKOD 0.3 3.0 ns
Jitter1 For more details, see the Jitter Measurement
section
Random Jitter, RMS (1σ)2 tJIT(RJ) 5.4 ps 1 MHz clock input, all channels switching
Deterministic Jitter, Peak-to-Peak3, 4 tJIT(DJ) 104 ps 100 Mbps, 215 − 1 PRBS input
Total Jitter, Peak-to-Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS input5
(BER) 1 × 10−12
Without Crosstalk 198 ps Single channel switching
With Crosstalk 260 ps All channels switching
DC SPECIFICATIONS
Input Threshold Voltage VIx
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.85 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −4 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6 = 4 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
Quiescent Supply Current
ADuM362N
IDD1 (Q) 1.4 2.1 mA VI9 = 0 (N0), 1 (N1)10
IDD2 (Q) 1.8 2.9 mA VI9 = 0 (N0), 1 (N1)10
IDD1 (Q) 9.3 12.6 mA VI9 = 1 (N0), 0 (N1)10
IDD2 (Q) 7.1 9.7 mA VI9 = 1 (N0), 0 (N1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.052 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.067 mA/Mbps Inputs switching, 50% duty cycle, CL = 0 nF
Undervoltage Lockout UVLO
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time tUVLO 60 μs UVLO release delay after VUVLO+ threshold

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 Data Sheet ADuM362N
SPECIFICATIONS

Table 1. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM ≥ 1000 V, TA = 125°C
|CML| 100 180 kV/µs VIx = 0 V, VCM ≥ 1000 V, TA = 125°C
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
7 VIxH is the input-side logic high.
8 VIxL is the input-side logic low.
9 VI is the voltage input.
10 N0 refers to the ADuM362N0 models, and N1 refers to the ADuM362N1 models. For more details, see the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 2. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM362N
1 Mbps
Supply Current Side 1 IDD1 5.3 7.5 mA CL = 0 nF
Supply Current Side 2 IDD2 4.5 6.4 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 6.4 8.7 mA CL = 0 nF
Supply Current Side 2 IDD2 6.2 8.5 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 10.4 13.9 mA CL = 0 nF
Supply Current Side 2 IDD2 11.5 16.8 mA CL = 0 nF

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 Data Sheet ADuM362N
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation
range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 3. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 10 ns Within PWD limit
Data Rate 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 6.6 10 ns 50% input to 50% output
Pulse-Width Distortion PWD 0.5 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.5 3.0 ns
Opposing Direction tPSKOD 0.5 3.0 ns
Jitter1 For more details, see the Jitter Measurement
section, all channels switching
Random Jitter, RMS (1σ)2 tJIT(RJ) 7.1 ps 1 MHz clock input
Deterministic Jitter, Peak-to-Peak3, 4 tJIT(DJ) 124 ps 100 Mbps, 215 − 1 PRBS input
Total Jitter, Peak-to-Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS input5
(BER) 1 × 10−12
Without Crosstalk 232 ps Single channel switching
With Crosstalk 257 ps All channels switching
DC SPECIFICATIONS
Input Threshold Voltage VIx
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.7 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −2 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6 = 2 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
Quiescent Supply Current
ADuM362N
IDD1 (Q) 1.3 2.2 mA VI9 = 0 (N0), 1 (N1)10
IDD2 (Q) 1.8 2.8 mA VI9 = 1 (N0), 0 (N1)10
IDD1 (Q) 8.7 12.2 mA VI9 = 1 (N0), 0 (N1)10
IDD2 (Q) 6.8 9.5 mA VI9 = 1 (N0), 0 (N1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.036 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.044 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time tUVLO 60 μs UVLO release delay after VUVLO+ threshold

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 Data Sheet ADuM362N
SPECIFICATIONS

Table 3. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM ≥ 1000 V, TA = 125°C
|CML| 100 180 kV/µs VIx = 0 V, VCM ≥ 1000 V, TA = 125°C
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
7 VIxH is the input-side logic high.
8 VIxL is the input-side logic low.
9 VI is the voltage input.
10 N0 refers to ADuM362N0 models, and N1 refers to ADuM362N1 models. For more details, see the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 4. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM362N
1 Mbps
Supply Current Side 1 IDD1 5.3 7.2 mA CL = 0 nF
Supply Current Side 2 IDD2 4.5 6.2 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 6.2 8.1 mA CL = 0 nF
Supply Current Side 2 IDD2 5.7 7.4 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 9.1 11.5 mA CL = 0 nF
Supply Current Side 2 IDD2 9.4 12.7 mA CL = 0 nF

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 Data Sheet ADuM362N
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended operation
range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 5. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 10 ns Within PWD limit
Data Rate 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 7.2 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.3 4.5 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 8.9 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.4 5.0 ns
Opposing Direction tPSKOD 0.4 5.0 ns
Jitter1 For more details, see the Jitter Measurement
section
Random Jitter, RMS (1σ)2 tJIT(RJ) 8.7 ps 1 MHz clock input, all channels switching
Deterministic Jitter, Peak to Peak3, 4 tJIT(DJ) 172 ps 100 Mbps, 215 − 1 PRBS
Total Jitter, Peak to Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS5
(BER) 1 × 10−12
Without Crosstalk 309 ps Single channel switching
With Crosstalk 424 ps All channels switching
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.65 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −2 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6 = 2 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
Quiescent Supply Current
ADuM362N
IDD1 (Q) 1.4 2.2 mA VI9 = 0 (N0), 1 (N1)10
IDD2 (Q) 1.8 2.8 mA VI9 = 0 (N0), 1 (N1)10
IDD1 (Q) 8.7 12.2 mA VI9 = 0 (N0), 1 (N1)10
IDD2 (Q) 6.8 9.8 mA VI9 = 0 (N0), 1 (N1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.032 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.038 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time tUVLO 60 μs UVLO release delay after VUVLO+ threshold

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 Data Sheet ADuM362N
SPECIFICATIONS

Table 5. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM ≥ 1000 V, TA = 125°C
|CML| 100 180 kV/µs VIx = 0 V, VCM ≥ 1000 V, TA = 125°C
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, D, E, or F.
7 VIxH is the input-side logic high.
8 VIxL is the input-side logic low.
9 VI is the voltage input.
10 N0 refers to ADuM362N0 models, and N1 refers to ADuM362N1 models. For more details, see the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 6. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM362N
1 Mbps
Supply Current Side 1 IDD1 5.1 7.2 mA CL = 0 nF
Supply Current Side 2 IDD2 4.5 6.1 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 5.7 7.9 mA CL = 0 nF
Supply Current Side 2 IDD2 5.3 7.1 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 8.4 10.4 mA CL = 0 nF
Supply Current Side 2 IDD2 8.2 10.2 mA CL = 0 nF

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SPECIFICATIONS

INSULATION CHARACTERISTICS
The ADuM362N is suitable for reinforced electrical insulation only within the safety ratings, as shown in Figure 2. Maintenance of the safety
ratings is ensured by protective circuits.
Table 7. RQ-16 Isolation Characteristics
Value
Parameter Symbol Conditions RQ-16 Unit
CLASSIFICATIONS
Overvoltage Category per IEC60664-1 − For rated mains voltage ≤ 150 VRMS I to III −
For rated mains voltage ≤ 300 VRMS I to III −
Climatic Classification − 40/125/21 −
Pollution Degree − Per DIN VDE V 0110 (refer to Table 1 of the DIN VDE 2 −
standard)
VOLTAGE
Maximum Working-Isolation Voltage1 VIOWM Continuous RMS voltage 450 VRMS
Maximum Repetitive-Isolation Voltage1 VIORM Continuous PEAK voltage 636 VPEAK
Maximum Transient-Isolation Voltage1 VIOTM t=1s 4242 VPEAK
Maximum Withstanding-Isolation Voltage1 VISO fTEST = 60 Hz, duration = 60 s 3000 VRMS
Maximum Surge-Isolation Voltage1 VIOSM Test method per IEC 60065, VIOSM ≥ 1.3 × VIMP2 10000 VPEAK
Maximum Impulse Voltage1 VIMP Tested in air, 1.2 μs/50 μs waveform per IEC 62368-1 4000 VPEAK
Input-to-Output Test Voltage VPR 1192 VPEAK
Apparent Charge qPD Method b1, VPR = 1.875 x VIORM, t = 1 s 5 pC
PACKAGE CHARACTERISTICS
External Creepage3 CPG Measured from input terminals to output terminals, shortest ≥3.5 mm
distance path along body
External Clearance3 CLR Measured from input terminals to output terminals, shortest ≥3.5 mm
distance through air4
Internal Clearance DTI Minimum internal clearance 34 μm
Comparative Tracking Index CTI >600 V
Material Group Material Group (IEC 60112) I −
Resistance (Input to Output)5 RIO VIO = 500 V, TA = 25°C 1013 Ω
VIO = 500 V, TA = TS 109 Ω
Capacitance (Input-to-Output)5 CIO f = 1 MHz 4 pF
IC Junction-to-Ambient Thermal Resistance θJA Simulated per JEDEC JESD-51 88.28 °C/W
SAFETY LIMITING VALUES
Maximum Ambient-Safety Temperature TS 150 °C
Maximum Input-Power Dissipation PS Total Power Dissipation at 25°C 1.40 °C/W
1 VISO, VIOTM, VIOWM, VIORM, VIMP, and VIOSM are defined by the IEC 60747-17 standard.
2 Devices are immersed in oil during surge characterization.
3 In accordance with IEC 62368-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m.
4 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
5 Device is measured as a 2-terminal device with Pin 1 through Pin 4 connected and Pin 5 through Pin 8 connected.

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 Data Sheet ADuM362N
SPECIFICATIONS

Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values, per IEC 60747-17

REGULATORY INFORMATION
For details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels, see Table 11.
Certifications available at Safety and Regulatory Certification for Digital Isolation.
Table 8. RQ-16 [QSOP] Package
Regulatory Agency Standard Certification/Approval File
UL (pending) UL1577 Pending
Single protection, 3000 VRMS isolation voltage1
TÜV Süd (pending) EN IEC 60747-17 Pending
Reinforced insulation, 636 VPEAK2
CSA (pending) IEC EN/CSA 62368-1 Pending
Basic insulation at 350 VRMS
Reinforced insulation at 175 VRMS
IEC/CSA 60601-1
Basic insulation (1 MOPP), 187 VRMS
IEC/CSA 61010-1
Basic insulation at 300 VRMS
Reinforced insulation at 150 VRMS
TÜV Süd (pending) EN IEC 62368-1 Pending
Basic insulation at 350 V RMS
Reinforced insulation at 175 VRMS
CQC (pending) CQC GB 4943.1 Pending
Basic insulation at 350 VRMS
Reinforced insulation at 175 VRMS
1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥3600 VRMS for 1 sec.
2 In accordance with IEC 60747-17, each product is proof tested by applying an insulation test voltage ≥1192 VPEAK for 1 sec (partial-discharge detection limit = 5 pC).

RECOMMENDED OPERATING CONDITIONS

Table 9. Recommended Operating Conditions
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages
VDD1 2.25 V to 5.5 V
VDD2 2.25 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms

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 Data Sheet ADuM362N
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. 2 VIOWM is the RMS or equivalent DC voltage characterizing the specified
Table 10. Absolute Maximum Ratings long-term withstand capability of its isolation.
3 VIORM is the maximum repetitive peak-isolation voltage.
Parameter Rating
Supply Voltages ELECTROSTATIC DISCHARGE (ESD) RATINGS
VDD1 to GND1 −0.5 V to +7.0 V
VDD2 to GND2 −0.5 V to +7.0 V The following ESD information is provided for handling of ESD-sen-
Input Voltages (VIA, VIB, VIC, VID, VIE, VIF)1 −0.5 V to VDDI + 0.5 V sitive devices in an ESD protected area only.
Output Voltages (VOA, VOB, VOC, VOD, VOE, −0.5 V to VDDO + 0.5 V Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
VOF)2
Average Output Current per Pin3 Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
Side 1 Output Current (IO1) −10 mA to +10 mA International electrotechnical commission (IEC) electromagnetic
Side 2 Output Current (IO2) −10 mA to +10 mA compatibility: Part 4-2 (IEC) per IEC 61000-4-2.
Common-Mode Transients4 −300 kV/μs to +300 kV/μs
Temperature ESD Ratings for ADuM362N
Storage Range (TST) −65°C to +150°C
Table 12. ADuM362N, 16-Lead [QSOP]
Ambient Operating Range (TA) −40°C to +125°C
ESD Model Withstand Threshold (V) Class
Moisture Sensitivity Level MSL3
HBM1 ±4000 3A
1 VDDI is the input-side supply voltage. CDM1 ±1250 C3
2 VDDO is the output-side supply voltage. IEC2 ±8000 Level 4
3 For the maximum rated current values for various ambient temperatures, see 1 With respect to local VDDx and GNDx pins.
Figure 2. 2
4
Across the isolation barrier between GND1 and GND2.
Refer to the common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause latchup ESD CAUTION
or permanent damage.
ESD (electrostatic discharge) sensitive device. Charged devi-
Stresses at or above those listed under Absolute Maximum Ratings ces and circuit boards can discharge without detection. Although
may cause permanent damage to the product. This is a stress this product features patented or proprietary protection circuitry,
rating only; functional operation of the product at these or any other damage may occur on devices subjected to high energy ESD.
conditions above those indicated in the operational section of this Therefore, proper ESD precautions should be taken to avoid
specification is not implied. Operation beyond the maximum operat- performance degradation or loss of functionality.
ing conditions for extended periods may affect product reliability.
Table 11. Maximum Continuous Working Voltage, RQ-16 [QSOP] Package
Parameter Rating1 Constraint
AC VOLTAGE
Bipolar Waveform
Basic Insulation 450 V rms Rating limited by VIOWM2
(reinforced) rating per IEC60747-17
Reinforced Insulation 347 V rms Rating limited by package creepage
per IEC 60664-1:2020 in Pollution
Degree 2 environment
DC VOLTAGE
Basic Insulation 636 V DC Rating limited by VIORM3
(reinforced) rating per IEC60747-17
Reinforced Insulation 347 V DC Rating limited by package creepage
per IEC 60664-1:2020 in Pollution
Degree 2 environment
1 Maximum continuous working voltage refers to the continuous voltage magni-
tude imposed across the isolation barrier in a Pollution Degree 2 environment.
For more details, see the Insulation Lifetime section.

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 Data Sheet ADuM362N
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. ADuM362N Pin Configuration

Table 13. ADuM362N Pin Function Descriptions

Pin Number Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1. This pin requires a 0.1 µF bypass capacitor.
2 VIA Logic Input A.
3 VIB Logic Input B.
4 VIC Logic Input C.
5 VID Logic Input D.
6 VOE Logic Output E.
7 VOF Logic Output F.
8 GND1 Ground Reference for Isolator Side 1.
9 GND2 Ground Reference for Isolator Side 2.
10 VIF Logic Input F.
11 VIE Logic Input E.
12 VOD Logic Output D.
13 VOC Logic Output C.
14 VOB Logic Output B.
15 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2. This pin requires a 0.1 µF bypass capacitor.

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 Data Sheet ADuM362N
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. ADuM362N IDD1 Supply Current vs. Data Rate at Various Voltages Figure 6. Propagation Delay, tPLH, tPHL vs. Temperature at Various Voltages

Figure 5. ADuM362N IDD2 Supply Current vs. Data Rate at Various Voltages Figure 7. Pulse-Width Distortion, tPWD vs. Temperature at Various Voltages

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 Data Sheet ADuM362N
THEORY OF OPERATION

The ADuM362N utilizes a high frequency carrier to transmit data noise and magnetic interference. Radiated emissions are minimized
across the isolation barrier by iCoupler chip-scale transformer coils with a spread spectrum OOK carrier and other techniques.
separated by layers of polyimide isolation. Using an on/off keying
(OOK) technique and the differential architecture, as shown in Figure 8 shows the waveforms for the ADuM362N when the condi-
Figure 8 and Figure 9, the ADuM362N has very-low propagation tion of the fail-safe output state equal to low, where the carrier
delay and supports high speed operation. waveform is off when the input state is low. If the input side is off
or not operating, the low fail-safe output state ADuM362N0 sets the
There is no interdependency between the VDD1 and VDD2 supplies. output to low. For the ADuM362N that have a high fail-safe output
The device can simultaneously operate at any voltage within the state, Figure 9 shows the conditions where the carrier waveform
specified operating ranges and can sequence in any order. This is off when the input state is high. When the input side is off or
feature enables the isolator to perform voltage translation of 2.5 V, not operating, the high fail-safe output state ADuM362N1 sets the
3.3 V, and 5 V logic. The architecture is designed for high common- output to high. For the model numbers that have the fail-safe output
mode transient (CMTI) immunity and high immunity to electrical state of low or the fail-safe output state of high, see Figure 17.

Figure 8. Operational Block Diagram of a Single-Channel with a Low Fail-Safe Output State

Figure 9. Operational Block Diagram of a Single-Channel with a High Fail-Safe Output State

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 Data Sheet ADuM362N
THEORY OF OPERATION

TRUTH TABLE
Table 14. ADuM362N Truth Table (Positive Logic)
Default Low (N0), VOx Default High (N1), VOx Output1,
VIx Input1, 2 VDDI State2 VDDO State2 Output1, 2, 3 2, 3 Test Conditions/ Comments
L Powered Powered L L Normal operation
H Powered Powered H H Normal operation
L Undervoltage Powered L H Fail-safe output
X4 Powered Undervoltage Indeterminate Indeterminate

1 L means low, H means high, X means don’t care, NC means not connected, and Z means high impedance within one diode drop of GNDx.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, E, or F). VDDI and VDDO refer to the supply voltages on the input and output sides of the
given channel, respectively.
3 N0 refers to ADuM362N0 models, and N1 refers to ADuM362N1 models. For more details, see the Ordering Guide section.
4 Input pins (VIx on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry).

I/O Schematics

Figure 10. VIA, VIB, VIC, VID, VIE, VIF Input Schematics

Figure 11. VOA, VOB, VOC, VOD, VOE, VOF Output Schematics

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 Data Sheet ADuM362N
APPLICATIONS INFORMATION

PRINTED CIRCUIT BOARD (PCB) LAYOUT JITTER MEASUREMENT

The ADuM362N digital isolator requires no external interface circui- Figure 14 shows the resulting eye diagram for the ADuM362N.
try for the logic interfaces. Power supply bypassing is strongly The measurement is taken by using a Keysight 81160A pulse
recommended at the input and output supply pins (see Figure 12). pattern generator at 100 Mbps with a pseudorandom bit sequence
Connect the bypass capacitors in between Pin 1 and Pin 8 for (PRBS15) input. Jitter is measured using the Tektronix 6 Series
VDD1 and between Pin 9 and Pin 16 for VDD2. The required bypass B mixed-signal oscilloscope, with a TAP1500 probe and using the
capacitor value is between 0.01 µF and 0.1 µF. The total lead Tektronix jitter and analysis software. The 10% to 90% rise and fall
length between both ends of the capacitor and the input power times of the input signal from the generator approximately equals
supply pin must not exceed 10 mm. Low ESR capacitors are 1.2 ns. The result shows a typical output eye diagram measured
important for direct power injection (DPI) and CMTI performance. on the ADuM362N. Figure 14 shows the random and deterministic
jitter characteristics for a PRBS input.
Total Jitter is evaluated at a BER of 1 × 10−12 and calculated
for a PRBS input with and without the effects of crosstalk. The
total jitter measurement without crosstalk consists of examining one
channels input, while the adjacent channels inputs are grounded.
The jitter measurement with crosstalk consists of all channels
switching simultaneously at the same rate.
Figure 12. Recommended PCB Layout

In applications involving high common-mode transients, ensure that

board coupling across the isolation barrier is minimized. Further-
more, design the board layout such that any coupling that does
occur equally affects all pins on a given component side. Failure
to ensure this design can cause voltage differentials between pins
exceeding the absolute maximum ratings of the device, thereby
leading to latchup or permanent damage (see Table 10).
PROPAGATION DELAY RELATED
PARAMETERS
Propagation delay is a parameter that describes the time required
for a logic signal to propagate through a component. The propaga-
tion delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output. Figure 14. ADuM362N Output-Channel Eye Diagram (VDD1 = VDD2 = 3.3 V,
100 Mbps, TA = 25°C, CL = 15 pF, PRBS15 Input)

INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
Figure 13. Propagation Delay Parameters degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
PWD is the maximum difference between these two propagation and material interfaces.
delay values and is an indication of how accurately the timing of the
input signal is preserved. The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
Channel matching is the maximum amount the propagation delay out. Surface breakdown is the phenomenon of surface tracking,
differs between channels within a single ADuM362N component. and the primary determinant of surface creepage requirements in
Propagation delay skew is the maximum amount the propagation system level standards. Insulation wear out is the phenomenon
delay differs between multiple ADuM362N components operating where charge injection or displacement currents inside the insula-
under the same conditions. tion material cause long-term insulation degradation.

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 Data Sheet ADuM362N
APPLICATIONS INFORMATION

Surface Tracking Calculation and Use of Parameters Example

Surface tracking is addressed in electrical safety standards by The following example frequently arises in power-conversion appli-
setting a minimum surface creepage based on the working voltage, cations. Assume that the line voltage on one side of the isolation
the environmental conditions, and the properties of the insulation is 240 V AC rms and a 400 V DC bus voltage is present on the
material. Safety agencies perform characterization testing on the other side of the isolation barrier. The isolator material is polyimide.
surface insulation of components that allows the components to To establish the critical voltages in determining the creepage, clear-
be categorized in different material groups. Lower material group ance, and lifetime of a device, see Figure 15 and the following
ratings are more resistant to surface tracking and, therefore, can equations.
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in
each system level standard and is based on the total RMS voltage
across the isolation, pollution degree, and material group. The
material group and creepage for the ADuM362N isolator are shown
in Table 7.

Insulation Wear Out

The lifetime of insulation caused by wear out is determined by its
thickness, material properties, and the voltage stress applied. It
is important to verify that the product lifetime is adequate at the
application working voltage. The working voltage supported by an Figure 15. Critical Voltage Example
isolator for wear out may not be the same as the working voltage
supported for tracking. The working voltage applicable to tracking is The working voltage across the barrier from Equation 1 is:
specified in most standards.
VRMS = VAC RMS2 + VDC2
Testing and modeling have shown that the primary driver of long-
term degradation is displacement current in the polyimide insulation VRMS = 2402 + 4002 (3)
causing incremental damage. The stress on the insulation can be VRMS = 466 V
broken down into broad categories, such as DC stress, which caus-
es very little wear out because there is no displacement current, This VRMS value is the working voltage used together with the
and an AC component time varying voltage stress, which causes material group and pollution degree when looking up the creepage
wear out. required by a system standard.

The ratings in certification documents are usually based on 60 Hz To determine if the lifetime is adequate, obtain the time varying
sinusoidal stress because this reflects isolation from line voltage. portion of the working voltage. To obtain the AC RMS voltage, use
However, many practical applications have combinations of 60 Hz Equation 2:
AC and DC across the barrier as shown in Equation 1. Because VAC RMS = VRMS2 − VDC2
only the AC portion of the stress causes wear out, the equation
can be rearranged to solve for the AC RMS voltage, as is shown VAC RMS = 4662 − 4002 (4)
in Equation 2. For insulation wear out with the polyimide materials VAC RMS = 240 V rms
used in these products, the AC RMS voltage determines the prod-
uct lifetime. In this case, the AC RMS voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform
VRMS = VAC RMS2 + VDC2 (1) is not sinusoidal. The value is compared to the limits for working
voltage in Table 11 for the expected lifetime, less than a 60 Hz sine
or wave, and it is well within the limit for a 50-year service life.
VAC RMS = VRMS2 − VDC2 (2) Note that the DC working voltage limit in Table 11 is set by the
creepage of the package as specified in IEC 60664-1. This value
where: can differ for specific system level standards.
VRMS is the total RMS working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the DC offset of the working voltage.

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 Data Sheet ADuM362N
OUTLINE DIMENSIONS

0.197 (5.00)
0.189 (4.80)

16 9

0.157 (3.99) 0.244 (6.20)

0.150 (3.81) 0.228 (5.79)
1
8

PIN 1
INDICATOR
TOP VIEW
0.025 (0.635)
BSC

0.020 (0.51)
0.069 (1.75) 0.059 (1.50) 0.010 (0.25) 0.010 (0.25)
SIDE VIEW
0.053 (1.35) 0.054 (1.37) 0.006 (0.18)

END VIEW 0.050 (1.27)

0.010 (0.25) 8°
SEATING 0.016 (0.41)
PLANE 0.012 (0.30) 0.004 (0.10) 0°
0.008 (0.20) COPLANARITY
0.004 (0.10)

05-21-2024-C
PKG-001086

COMPLIANT TO JEDEC STANDARDS MO-137-AB

Figure 16. 16-Lead Shrink Small-Outline Package [QSOP]

(RQ-16)
Dimensions Shown in inches and (millimeters)

Figure 17. Product Selector Guide

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 Data Sheet ADuM362N
OUTLINE DIMENSIONS

Updated: September 17, 2024

ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
ADuM362N0BRQZ −40°C to +125°C 16-Lead [QSOP] Tube, 98 RQ-16
ADuM362N0BRQZ-RL7 −40°C to +125°C 16-Lead [QSOP] Reel, 1000 RQ-16
ADuM362N1BRQZ −40°C to +125°C 16-Lead [QSOP] Tube, 98 RQ-16
ADuM362N1BRQZ-RL7 −40°C to +125°C 16-Lead [QSOP] Reel, 1000 RQ-16
1 Z = RoHS-Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-ADuM36xNEBZ Evaluation Board for the ADuM362N
1 Z = RoHS-Compliant Part.

AUTOMOTIVE PRODUCTS
The ADuM362N0W/ADuM362N1W models will be available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers must review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use
in automotive applications. Contact the local Analog Devices account representative for specific product ordering information and to obtain the
specific Automotive Reliability reports for these models.

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registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.

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