a Low Cost Quad

Voltage Controlled Amplifier

SSM2164
FEATURES FUNCTIONAL BLOCK DIAGRAM
Four High Performance VCAs in a Single Package
0.02% THD
No External Trimming VC
120 dB Gain Range
0.07 dB Gain Matching (Unity Gain)
Class A or AB Operation
IIN VCA1 IIOUT
APPLICATIONS
Remote, Automatic, or Computer Volume Controls
Automotive Volume/Balance/Faders
VC
Audio Mixers
Compressor/Limiters/Compandors
Noise Reduction Systems
Automatic Gain Controls IIN VCA2 IIOUT
Voltage Controlled Filters
Spatial Sound Processors
Effects Processors VC

GENERAL DESCRIPTION
The SSM2164 contains four independent voltage controlled IIN VCA3 IIOUT
amplifiers (VCAs) in a single package. High performance
(100 dB dynamic range, 0.02% THD) is provided at a very low
cost-per-VCA, resulting in excellent value for cost sensitive gain VC
control applications. Each VCA offers current input and output
for maximum design flexibility, and a ground referenced
–33 mV/dB control port.
IIN VCA4 IIOUT
All channels are closely matched to within 0.07 dB at unity gain,
and 0.24 dB at 40 dB of attenuation. A 120 dB gain range is
possible.
A single resistor tailors operation between full Class A and AB POWER SUPPLY
AND BIASING CIRCUITRY
modes. The pinout allows upgrading of SSM2024 designs with
minimal additional circuitry.
The SSM2164 will operate over a wide supply voltage range of V+ GND V– MODE
± 4 V to ± 18 V. Available in 16-pin P-DIP and SOIC packages,
the device is guaranteed for operation over the extended
industrial temperature range of –40°C to +85°C.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
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use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
SSM2164–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (V = ±15 V, A = 0 dB, 0 dBu = 0.775 V rms, V
S V IN = 0 dBu, RIN = ROUT = 30 kΩ, f = 1 kHz,
–40°C < TA < +85°C using Typical Application Circuit (Class AB), unless otherwise noted. Typical specifications apply at TA = +25°C.)

SSM2164
Parameter Conditions Min Typ Max Units
AUDIO SIGNAL PATH
Noise VIN = GND, 20 kHz Bandwidth –94 dBu
Headroom Clip Point = 1% THD+N 22 dBu
Total Harmonic Distortion 2nd and 3rd Harmonics Only
AV = 0 dB, Class A 0.02 .1 %
AV = ± 20 dB, Class A1 0.15 %
AV = 0 dB, Class AB 0.16 %
AV = ± 20 dB, Class AB1 0.3 %
Channel Separation –110 dB
Unity Gain Bandwidth CF = 10 pF 500 kHz
Slew Rate CF = 10 pF 0.7 mA/µs
Input Bias Current ± 10 nA
Output Offset Current VIN = 0 ± 50 nA
Output Compliance ± 0.1 V
CONTROL PORT
Input Impedance 5 kΩ
Gain Constant (Note 2) –33 mV/dB
Gain Constant Temperature Coefficient –3300 ppm/°C
Control Feedthrough 0 dB to –40 dB Gain Range3 1.5 8.5 mV
Gain Matching, Channel-to-Channel AV = 0 dB 0.07 dB
AV = –40 dB 0.24 dB
Maximum Attenuation –100 dB
Maximum Gain +20 dB
POWER SUPPLIES
Supply Voltage Range ±4 ± 18 V
Supply Current Class AB 6 8 mA
Power Supply Rejection Ratio 60 Hz 90 dB
NOTES
1
–10 dBu input @ 20 dB gain; +10 dBu input @ –20 dB gain.
2
After 60 seconds operation.
3
+25°C to +85°C.
Specifications subject to change without notice.

TYPICAL APPLICATION AND TEST CIRCUIT

VC 100pF
14
VC4

30kΩ
IIN 15 13 IIOUT
VCA4
30kΩ 1/2
VIN4 OP275 VOUT4

500Ω
560pF POWER SUPPLY
AND BIASING CIRCUITRY
9 8 16 1
V– GND V+ MODE

0.1µF 0.1µF
RB (7.5kΩ CLASS A)
(OPEN CLASS AB)

–15V +15V

Figure 1. RIN = ROUT = 30 kΩ, CF = 100 pF. Optional RB = 7.5 kΩ, Biases Gain Core to Class A Opera-
tion. For Class AB, Omit RB.

–2– REV. 0
 SSM2164
ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input, Output, Control Voltages . . . . . . . . . . . . . . . . V– to V+ Temperature Package Package
Output Short Circuit Duration to GND . . . . . . . . . Indefinite Model Range Description Options
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C SSM2164P –40°C to +85°C Plastic DIP N-16
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C SSM2164S –40°C to +85°C Narrow SOIC R-16A
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

Package Type θJA* θJC Units PIN CONFIGURATION

16-Pin Plastic DIP (P Suffix) 76 33 °C/W 16-Lead Epoxy DIP and SOIC
16-Pin SOIC (S Suffix) 92 27 °C/W
*θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for P-DIP packages, θJA is specified for device soldered in circuit board for SOIC
package. MODE 1 16 V+

IIN1 2 15 IIN4

VC1 3 14 VC4
IOUT1 4 SSM2164 13 IOUT4
TOP VIEW
IOUT2 5 12 IOUT3
(Not to Scale)
VC2 6 11 VC3

IIN2 7 10 IIN3
GND 8 9 V–

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the SSM2164 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 –3–
SSM2164
Typical Performance Characteristics
1.0 210
200
CLASS A 190 VS = ±15V
VS = ±15V 180 TA = +25°C
LPF = 80kHz 170 1200 CHANNELS
160
150
140
AV = + 20dB 130
THD + N – %

120

UNITS
110
0.1
100
AV = – 20dB 90
80
70
60
50
AV = 0dB 40
30
20
10
0.01 0
20 100 1k 10k 20k 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
FREQUENCY – Hz THD – %

Figure 2. THD+N vs. Frequency, Class A Figure 5. THD Distribution, Class AB

1.0 1.0

CLASS AB VS ±15V
VS = ±15V AV = 0dB
LPF = 80kHz LPF = 22kHz
AV = –20dB
AV = +20dB
THD + N – %
THD + N – %

CLASS AB
0.1 AV = 0dB 0.1

CLASS A

0.01 0.01
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY – Hz AMPLITUDE – VRMS

Figure 3. THD+N vs. Frequency Class, AB Figure 6. THD+N vs. Amplitude

0.10
300
280
VS = ±15V LPF = 80kHz
260 TA = +25°C
240 1200 CHANNELS 0.08
220
200
THD + N – %

180 0.06
160
UNITS

140
120 0.04

100
80
60 0.02

40
20
0 0
0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0 ±4 ±8 ±12 ±16 ±20
THD – % SUPPLY – Volts

Figure 4. THD Distribution, Class A Figure 7. THD+N vs. Supply Voltage, Class A

–4– REV. 0
 SSM2164
1000

VS = ±15V VS = ±15V

Hz
0.030 VIN = 0dBu TA = +25°C
AV = 0dB

VOLTAGE NOISE DENSITY – nV/

0.025
% THD

0.020 100

0.015

0.010

10
–40 –20 0 20 40 60 80 1k 10k 100k 1M
RBIAS – Ω
TEMPERATURE – °C

Figure 8. THD vs. Temperature, Class A Figure 11. Voltage Noise Density vs. RBIAS

1.0

VS = ±15V
VS = ±15V
0.30 TA = +25°C
VIN = 0dBu
AV = 0dB

0.25
% THD

THD – %

0.20 0.1

0.15

0.10

0.01
–40 –20 0 20 40 60 80 1k 10k 100k 1M
TEMPERATURE – °C RBIAS – Ω

Figure 9. THD vs. Temperature, Class AB Figure 12. THD vs. RBIAS

500 10

VS = ±15V VS = ±15V
RIN = RF = 30kΩ TA = +25°C
5
400 TA = +25°C
CONTROL FEEDTHROUGH – mV

0
Hz

300
NOISE – nV/

–5

200
–10

100
–15

0 –20
1 10 100 1k 10k 100k 1k 10k 100k 1M
FREQUENCY – Hz RBIAS – Ω

Figure 10. Voltage Noise Density vs. Frequency, Class AB Figure 13. Control Feedthrough vs. RBIAS

REV. 0 –5–
SSM2164
Typical Performance Characteristics
15 10M

PHASE VS = ±15V
10 180 TA = +25°C
VS = ±15V

–3dB BANDWIDTH – Hz
TA = +25°C
5 90 1M

PHASE – Degrees
AV = 0dB
CF = 10pF
GAIN – dB

GAIN
0 0

–5 –90 100k

–10 –180

–15 10k

1k 10k 100k 1M 10M 1 10 100 1000

FREQUENCY – Hz I TO V FEEDBACK CAPACITOR – pF

Figure 14. Gain/Phase vs. Frequency Figure 17. –3 dB Bandwidth vs. I-to-V Feedback Capacitor

0.1 30

CF = 10pF ±SLEW RATE

25 VS = ±15V
0
TA = +25°C

20
SLEW RATE – V/µs

CF = 100pF
–0.1 OP275 OUTPUT
GAIN – dB

AMPLIFIER

VS = ±15V 15
TA = +25°C
–0.2
AV = 0dB
10

–0.3
5

–0.4 0
10 100 1k 10k 100k 1 10 100
FREQUENCY – Hz I TO V FEEDBACK CAPACITOR – pF

Figure 15. Gain Flatness vs. Frequency Figure 18. Slew Rate vs. I-to-V Feedback Capacitor

40 20
VS = ±15V
TA = +25°C VS = ±15V
AV = +20dB TA = +25°C
CF = 10pF
20 0
CONTROL FEEDTHROUGH – dB

VIN = 0V
RF = RIN = 30kΩ

AV = 0dB
GAIN – dB

0 –20

AV = –20dB
–20 –40

–40 –60

–60 –80
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz

Figure 16. Bandwidth vs. Gain Figure 19. Control Feedthrough vs. Frequency

–6– REV. 0
 SSM2164
0 APPLICATIONS INFORMATION
Circuit Description
VS = ±15V The SSM2164 is a quad Voltage Controlled Amplifier (VCA)
–20 TA = +25°C with 120 dB of gain control range. Each VCA is a current-in,
current-out device with a separate –33 mV/dB voltage input
–40
control port. The class of operation (either Class A or Class
PSRR – dB

+PSRR
AB) is set by a single external resistor allowing optimization of
the distortion versus noise tradeoff for a particular application.
–60 The four independent VCAs in a single 16-pin package make
–PSRR the SSM2164 ideal for applications where multiple volume
control elements are needed.
–80

V+

–100
10 100 1k 10k 100K 1M
FREQUENCY – Hz

Figure 20. PSRR vs. Frequency

IIN Q5 Q6 Q7 Q8

25

VS = ±15V
TA = +25°C IOUT
20
4.5kΩ
SUPPLY CURRENT – mA

MODE
Q1 Q2 Q3 Q4 VC
+ISY
15 500Ω
450Ω

–ISY
10

0
V–
1k 10k 100k 1M
RBIAS – Ω

Figure 23. Simplified Schematic (One Channel)

Figure 21. Supply Current vs. RBIAS
The simplified schematic in Figure 23 shows the basic structure
of one of the four VCAs in the device. The gain core is com-
prised of the matched differential pairs Q1-Q4 and the current
–45
mirrors of Q5, Q6 and Q7, Q8. The current input pin, IIN, is
CLASS A AND
CLASS AB connected to the collectors of Q1 and Q7, and the difference in
–40 current between these two transistors is equivalent to IIN. For
example, if 100 µA is flowing into the input, Q1’s collector
GAIN CONSTANT – mV/dB

VS = ±15V
current will be 100 µA higher than Q7’s collector current.
–35
Varying the control voltage VC, steers the signal current from
one side of each differential pair to the other, resulting in either
–30 gain or attenuation. For example, a positive voltage on VC
steers more current through Q1 and Q4 and decreases the
current in Q2 and Q3. The current output pin, IOUT, is con-
–25
nected to the collector of Q3 and the current mirror (Q6) from
Q2. With less current flowing through these two transistors, less
–20 current is available at the output. Thus, a positive VC attenuates
–50 –25 0 25 50 75 100
TEMPERATURE – °C
the input and a negative VC amplifies the input. The VCA has
unity gain for a control voltage of 0.0 V where the signal current
is divided equally between the gain core differential pairs.
Figure 22. Gain Constant vs. Temperature The MODE pin allows the setting of the quiescent current in
the gain core of the VCA to trade off the SSM2164’s THD and
noise performance to an optimal level for a particular applica-
tion. Higher current through the core results in lower distortion

REV. 0 –7–
SSM2164
but higher noise, and the opposite is true for less current. The a low cutoff frequency. The main exception to this is in
increased noise is due to higher current noise in the gain core dynamic processing applications, where faster attack or decay
transistors as their operating current is increased. THD has the times may be needed.
opposite relationship to collector current. The lower distortion
is due to the decrease in the gain core transistors’ emitter
+5V 100pF
impedance as their operating current increases. VC 3

This classical tradeoff between THD and noise in VCAs is 100k

1µF 30k
usually expressed as the choice of using a VCA in either Class A IIN 2 4 IIOUT
VCA1
or Class AB mode. Class AB operation refers to running a VCA VIN1
30k 1/4
OP482 VOUT1
with less current in the gain core, resulting in lower noise but 500
higher distortion. More current in the core corresponds to
+5V 560pF 100pF
Class A performance with its lower THD but higher noise. VC 6

Figures 11 and 12 show the THD and noise performance of the 100k
SSM2164 as the bias current is adjusted. Notice the two 1µF
7 IIOUT 30k
IIN 5
characteristics have an inverse characteristic. 30k
VCA2
1/4
VIN2 OP482 VOUT2
The quiescent current in the core is set by adding a single
500
resistor from the positive supply to the MODE pin. As the
+5V 560pF 100pF
simplified schematic shows, the potential at the MODE pin is VC 11

one diode drop above the ground pin. Thus, the formula for the 100k
MODE current is: 1µF 30k
IIN 10 12 IIOUT
VCA3
30k 1/4
(V +) − 0.6V VIN3 OP482 VOUT3
I MODE =
500
RB
+5V 560pF 100pF
VC 14
With ± 15 V supplies, an RB of 7.5k gives Class A biasing with a
100k
current of 1.9 mA. Leaving the MODE pin open sets the
1µF
SSM2164 in Class AB with 30 µA of current in the gain core. IIN 15
VCA4
13 IIOUT 30k

30k 1/4
Basic VCA Configuration VIN4 OP482 VOUT4

Figure 24 shows the basic application circuit for the SSM2164. 500

Each of the four channels is configured identically. A 30 kΩ 560pF POWER SUPPLY

AND BIASING CIRCUITRY
resistor converts the input voltage to an input current for the
VCA. Additionally, a 500 Ω resistor in series with a 560 pF 9 8 16 1
V– GND V+ MODE
capacitor must be added from each input to ground to ensure
0.1µF 0.1µF
stable operation. The output current pin should be maintained RB (7.5kΩ CLASS A)
(OPEN CLASSAB)
at a virtual ground using an external amplifier. In this case the
OP482 quad JFET input amplifier is used. Its high slew rate,
–15V +15V
wide bandwidth, and low power make it an excellent choice for
the current-to-voltage converter stage. A 30 kΩ feedback
resistor is chosen to match the input resistor, giving unity gain Figure 24. Basic Quad VCA Configuration
for a 0.0 V control voltage. The 100 pF capacitors ensure
stability and reduce high frequency noise. They can be Low Cost, Four-Channel Mixer
increased to reduce the low pass cutoff frequency for further The four VCAs in a single package can be configured to create a
noise reduction. simple four-channel mixer as shown in Figure 25. The inputs
and control ports are configured the same as for the basic VCA,
For this example, the control voltage is developed using a but the outputs are summed into a single output amplifier. The
100 kΩ potentiometer connected between +5 V and ground. OP176 is an excellent amplifier for audio applications because
This configuration results in attenuation only. To produce both of its low noise and distortion and high output current drive.
gain and attenuation, the potentiometer should be connected The amount of signal from each input to the common output
between a positive and negative voltage. The control input has can be independently controlled using up to 20 dB of gain or as
an impedance of 5 kΩ. Because of this, any resistance in series much as 100 dB of attenuation. Additional SSM2164s could be
with VC will attenuate the control signal. If precise control of added to increase the number of mixer channels by simply
the gain and attenuation is required, a buffered control voltage summing their outputs into the same output amplifier. Another
should be used. possible configuration is to use a dual amplifier such as the
Notice that a capacitor is connected from the control input to OP275 to create a stereo, two channel mixer with a single
ground. Because the control port is connected directly to the SSM2164.
gain core transistors, any noise on the VC pin will increase the
output noise of the VCA. Filtering the control voltage ensures
that a minimal amount of noise is introduced into the VCA,
allowing its full performance to be realized. In general, the
largest possible capacitor value should be used to set the filter at

–8– REV. 0
 SSM2164
If additional SSM2164s are added, the 100 pF capacitor may
VC need to be increased to ensure stability of the output amplifier.
30k Most op amps are sensitive to capacitance on their inverting
IIOUT inputs. The capacitance forms a pole with the feedback resistor,
500 VCA1
IIN which reduces the high frequency phase margin. As more
560pF
SSM2164’s are added to the mixer circuit, their output capaci-
VC 100pF tance and the parasitic trace capacitance add, increasing the
30k overall input capacitance. Increasing the feedback capacitor will
IIOUT maintain the stability of the output amplifier.
500 VCA2 30kΩ
IIN
560pF Digital Control of the SSM2164
OP176 VOUT One option for controlling the gain and attenuation of the
VC
30k
SSM2164 is to use a voltage output digital-to-analog converter
such as the DAC8426 (Figure 26), whose 0 V to +10 V output
IIOUT
500
IIN
VCA3 controls the SSM2164’s attenuation from 0 dB to –100 dB. Its
560pF simple 8-bit parallel interface can easily be connected to a
VC
microcontroller or microprocessor in any digitally controlled
30k
system. The voltage output configuration of the DAC8426
IIOUT
provides a low impedance drive to the SSM2164 so the attenua-
500 VCA4 tion can be controlled accurately. The 8-bit resolution of the
IIN
560pF DAC and its full-scale voltage of +10 V gives an output of
FROM ADDITIONAL SSM2164s 3.9 mV/bit. Since the SSM2164 has a –33 mV/dB gain con-
POWER SUPPLY FOR > 4 CHANNELS
AND BIASING CIRCUITRY stant, the overall control law is 0.12 dB/bit or approximately
8 bits/dB. The input and output configuration for the
V+ GND V– MODE SSM2164 is the same as for the basic VCA circuit shown
earlier. The 4-to-1 mixer configuration could also be used.
Figure 25. Four-Channel Mixer (4 to 1)

+15V VC

VREFOUT +10V VDD

IIN IIOUT
4 18 VCA1

DAC8426 10V
REFERENCE VC

2
LATCH A DAC A VOUTA
IIN IIOUT
1 VCA2
LATCH B DAC B VOUTB
7
MSB VC
14 DATA BUS
LSB 20
LATCH C DAC C VOUTC
IIN IIOUT
19 VCA3
LATCH D DAC D VOUTD

15 VC
WR
16 LOGIC
A1
17 CONTROL
A0
IIOUT
VCA4
3 5 6 IIN
VSS AGND DGND

POWER SUPPLY
AND BIASING CIRCUITRY

V+ GND V– MODE

+15V –15V

Figure 26. Digital Control of VCA Gain

REV. 0 –9–
SSM2164
Single Supply Operation Upgrading SSM2024 Sockets
The SSM2164 can easily be operated from a single power The SSM2164 is intended to replace the SSM2024, an earlier
supply as low as +8 V or as high as +36 V. The key to using a generation quad VCA. The improvements in the SSM2164
single supply is to reference all ground connections to a voltage have resulted in a part that is not a drop-in replacement to the
midway between the supply and ground as shown in Figure 27. SSM2024, but upgrading applications with the SSM2024 is a
The OP176 is used to create a pseudo-ground reference for the simple task. The changes are shown in Figure 28. Both parts
SSM2164. Both the OP482 and OP176 are single supply have identical pinouts with one small exception. The MODE
amplifiers and can easily operate over the same voltage range as input (Pin 1) does not exist on the SSM2024. It has fixed
the SSM2164 with little or no change in performance. internal biasing, whereas flexibility was designed into the
SSM2164. A MODE set resistor should be added for Class A
operation, but if the SSM2164 is going to be operated in Class
V+ = +8V
AB, no external resistor is needed.
(1.8kΩ FOR
CLASS A)
RB (OPEN FOR
CLASS B) 100pF 10kΩ
VC1 V+
16 30kΩ 3 NC
V+ 1 16
10kΩ
V+
10µF 30kΩ 1
MODE 10kΩ
VIN 2 4
1/4 VIN1 SSM2024
GND VOUT VOUT1
500Ω OP482
V– 200Ω 8
560pF 8
9
9
V+ V+ V–
VC
(0dB GAIN AT VC = V+ )
2 V+/2 10kΩ
OP176 V+
VC1

3
TO ADDITIONAL 10kΩ 10µF 16 RB
OP482 AMPLIFIERS 30kΩ
1
30kΩ 2 4
VIN1 SSM2164
VOUT1
500Ω 8

Figure 27. Single Supply Operation of the SSM2164 560pF

9

(One Channel Shown)

V–

The reference voltage is set by the resistor divider from the

positive supply. Two 10 kΩ resistors create a voltage equal to
the positive supply divided by 2. The 10 µF capacitor filters the Figure 28. Upgrading SSM2024 Sockets with SSM2164
supply voltage, providing a low noise reference to the circuit.
This reference voltage is then connected to the GND pin of the Since both parts are current output devices, the output configu-
SSM2164 and the noninverting inputs of all the output amplifi- ration is nearly identical, except that the 10 kΩ resistors should
ers. It is important to buffer the resistor divider with the OP176 be increased to 30 kΩ to operate the SSM2164 in its optimum
to ensure a low impedance pseudo-ground connection for the range. The 10 kΩ input resistor for the SSM2024 should also
SSM2164. be increased to 30 kΩ to match the output resistor. Addition-
The input can either be referenced to this same mid-supply ally, the 200 Ω resistor should be replaced by a 500 Ω resistor in
voltage or ac coupled as is done in this case. If the entire system series with 560 pF for the SSM2164 circuit.
is single supply, then the input voltage will most likely already One last change is the control port configuration. The
be referenced to the midpoint; if this is the case, the 10 µF SSM2024’s control input is actually a current input. Thus, a
input capacitor can be eliminated. Unity gain is set when VC resistor was needed to change the control voltage to a current.
equals the voltage on the GND pin. Thus, the control voltage This resistor should be removed for the SSM2164 to provide a
should also be referenced to the same midsupply voltage. direct voltage input. In addition, the SSM2024 has a log/log
The value of the MODE setting resistor may also change control relationship in contrast to the SSM2164’s linear/log gain
depending on the total supply voltage. Because the GND pin is constant. The linear input is actually much easier to control,
at a pseudo-ground potential, the equation to set the MODE but the difference may necessitate adjusting a SSM2024 based
current now becomes: circuit’s control voltage gain curve. By making these relatively
simple changes, the superior performance of the SSM2164 can
(V +) −V GND − 0.6V easily be realized.
I MODE =
RB
The value of 1.8 kΩ results in Class A biasing for the case of
using a +8 V supply.

–10– REV. 0
 SSM2164
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

16-Pin Plastic DIP (N-16)

16 9
0.280 (7.11)
PIN 1 0.240 (6.10)
1 8

0.840 (21.33) 0.325 (8.25)

0.745 (18.93) 0.300 (7.62)

0.060 (1.52)
0.210 0.015 (0.38) 0.195 (4.95)
(5.33) 0.115 (2.93)
MAX

0.130
0.160 (4.06) (3.30) 0.015 (0.381)
0.115 (2.93) MIN 0.008 (0.204)

0.022 (0.558) SEATING

0.100 0.070 (1.77)
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC

16-Pin Narrow SOIC (R-16A)

16 9
0.1574 (4.00)
0.1497 (3.80)
PIN 1
1 8 0.2440 (6.20)
0.2284 (5.80)

0.3937 (10.00) 0.0196 (0.50)

0.3859 (9.80) x 45 °
0.0099 (0.25)
0.0688 (1.75)
0.0532 (1.35)
8°
0.0098 (0.25) 0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
0.0099 (0.25)
0.0040 (0.10) (1.27) 0.0138 (0.35) 0.0160 (0.41)
BSC 0.0075 (0.19)

REV. 0 –11–
–12–
PRINTED IN U.S.A. C1969–10–10/94