MCP660/1/2/3/4/5/9

60 MHz, 32 V/µs Rail-to-Rail Output (RRO) Op Amps

Features: Description:
• Gain-Bandwidth Product: 60 MHz (typical) The Microchip Technology Inc. MCP660/1/2/3/4/5/9
• Slew Rate: 32 V/µs (typical) family of operational amplifiers (op amps) features high
• Noise: 6.8 nV/Hz (typical, at 1 MHz) gain-bandwidth product and high slew rate. Some also
provide a Chip Select pin (CS) that supports a low-
• Short Circuit Current: 90 mA (typical)
power mode of operation. These amplifiers are
• Low Input Bias Current: 4 pA (typical) optimized for high speed, low noise and distortion,
• Ease of Use: single-supply operation with rail-to-rail output and an
- Unity-Gain Stable input that includes the negative rail.
- Rail-to-Rail Output This family is offered in single (MCP661), single with
- Input Range including Negative Rail CS pin (MCP663), dual (MCP662) and dual with two
- No Phase Reversal CS pins (MCP665), triple (MCP660), quad (MCP664)
and quad with two CS pins (MCP669). All devices are
• Supply Voltage Range: +2.5V to +5.5V
fully specified from -40°C to +125°C.
• High Output Current: ±70 mA
• Supply Current: 6.0 mA/ch (typical) Typical Application Circuit
• Low-Power Mode: 1 µA/ch
• Small Packages: SOT23-5, DFN RG RF RISO
VREF VOUT
• Extended Temperature Range: -40°C to +125°C
- CL RL
Typical Applications: VIN +
• Multi-Pole Active Filter
MCP66X
• Driving A/D Converters
• Power Amplifier Control Loops 100
• Line Driver
Recommended RISO (ȍ

• Video Amplifier
• Barcode Scanners
• Optical Detector Amplifier 10

Design Aids: GN = +1
GN •
• SPICE Macro Models
• FilterLab® Software 1
10p 100p 1n 10n
• Microchip Advanced Part Selector (MAPS) 1.E-11 1.E-10 1.E-09 1.E-08
Normalized Capacitance; CL/GN (F)
• Analog Demonstration and Evaluation Boards
- MCP661DM-LD
• Application Notes

High Gain-Bandwidth Op Amp Portfolio

Model Family Channels/Package Gain-Bandwidth VOS (max.) IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9 1, 2, 4 20 MHz 0.2 mV 2.5 mA
MCP631/2/3/4/5/9 1, 2, 4 24 MHz 8.0 mV 2.5 mA
MCP651/1S/2/3/4/5/9 1, 2, 4 50 MHz 0.2 mV 6.0 mA
MCP660/1/2/3/4/5/9 1, 2, 3, 4 60 MHz 8.0 mV 6.0 mA

 2009-2014 Microchip Technology Inc. DS20002194E-page 1

MCP660/1/2/3/4/5/9
Package Types

MCP660 MCP660 MCP661

4x4 QFN* SOIC, TSSOP SOT-23-5

VOUTC
NC 1 14 VOUTC

VINC-
VOUT 1 5 VDD
NC
NC
NC 2 13 VINC-
16 15 14 13 NC 3 12 VINC+ VSS 2
NC 1 12 VINC+ VDD 4 11 VSS VIN+ 3 4 VIN-
NC 2 EP 11 VSS VINA+ 5 10 VINB+
VDD 3 17 10 VINB+ VINA- 6 9 VINB-
VINA+ 4 9 VINB- VOUTA 7 8 VOUTB
5 6 7 8
VOUTA

VOUTB
VINA-

NC

MCP661 MCP661 MCP662 MCP662

SOIC 2x3 TDFN* MSOP, SOIC 3x3 DFN*
NC 1 8 NC NC 1 8 CS VOUTA 1 8 VDD VOUTA 1 8 VDD
VIN- 2 7 VDD VIN– 2 EP 7 VDD VINA- 2 7 VOUTB VINA- 2 7 VOUTB
EP
VIN+ 3 6 VOUT VIN+ 3 9 VINA+ 3 6 VINB- VINA+ 3 9 6 VINB-
6 VOUT
VSS 4 5 NC VSS 4 5 NC VSS 4 5 VINB+ VSS 4 5 VINB+

MCP663 MCP663 MCP664

SOIC SOT-23-6 SOIC, TSSOP
NC 1 8 CS VOUT 1 6 VDD VOUTA 1 14 VOUTD
VIN- 2 7 VDD VINA- 2 13 VIND-
VIN+ 3 6 VOUT VSS 2 5 CS VINA+ 3 12 VIND+
VSS 4 5 NC VDD 4 11 VSS
VIN+ 3 4 VIN-
VINB+ 5 10 VINC+
VINB- 6 9 VINC-
VOUTB 7 8 VOUTC

MCP665 MCP665 MCP669

3x3 DFN* MSOP 4x4 QFN*
VOUTD

10 VDD
VOUTA

VOUTA 1 10 VDD VOUTA 1

CSAD

VIND-

VINA- 2 9 VOUTB VINA- 2 9 VOUTB

EP
VINA+ 3 8 VINB- VINA+ 3
11 8 VINB- 16 15 14 13
VSS 4 7 VINB+
5 6
VSS 4 7 VINB+ VINA- 1 12 VIND+
CSA CSB
CSA 5 6 CSB VINA+ 2 EP 11 VSS
VDD 3 17 10 VINC+
VINB+ 4 9 VINC-
5 6 7 8
VOUTB
CSBC
VOUTC
VINB-

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS20002194E-page 2  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
CHARACTERISTICS
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
1.1 Absolute Maximum Ratings † above those indicated in the operational listings of this
VDD – VSS .......................................................................6.5V specification is not implied. Exposure to maximum rat-
ing conditions for extended periods may affect device
Current at Input Pins ....................................................±2 mA
reliability.
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V †† See Section 4.1.2 “Input Voltage and Current
Output Short Circuit Current ................................ Continuous Limits”.
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Maximum Junction Temperature ................................ +150°C
ESD protection on all pins (HBM, MM)  1 kV, 200V

1.2 Specifications

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CS = VSS (refer to Figure 1-2).

Parameters Sym. Min. Typ. Max. Units Conditions

Input Offset
Input Offset Voltage VOS -8 ±1.8 +8 mV
Input Offset Voltage Drift VOS/TA — ±2.0 — µV/°C TA = -40°C to +125°C
Power Supply Rejection Ratio PSRR 61 76 — dB
Input Current and Impedance
Input Bias Current IB — 6 — pA
Across Temperature IB — 130 — TA = +85°C
Across Temperature IB — 1700 5000 TA = +125°C
Input Offset Current IOS — ±10 — pA
Common-Mode Input ZCM — 1013||9 — ||pF
Impedance
Differential Input Impedance ZDIFF — 1013||2 — ||pF
Common Mode
Common-Mode Input Voltage VCMR VSS  — VDD  V Note 1
Range 0.3 1.3
Common-Mode Rejection Ratio CMRR 64 79 — dB VDD = 2.5V, VCM = -0.3V to 1.2V
66 81 — dB VDD = 5.5V, VCM = -0.3V to 4.2V
Open-Loop Gain
DC Open-Loop Gain AOL 88 117 — dB VDD = 2.5V, VOUT = 0.3V to 2.2V
(large signal) 94 126 — dB VDD = 5.5V, VOUT = 0.3V to 5.2V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD  25 mV VDD = 2.5V, G = +2,
0.5V Input Overdrive
VSS + 50 — VDD  50 VDD = 5.5V, G = +2,
0.5V Input Overdrive
Output Short-Circuit Current ISC ±45 ±90 ±145 mA VDD = 2.5V (Note 2)
±40 ±80 ±150 VDD = 5.5V (Note 2)
Note 1: See Figure 2-5 for temperature effects.
2: The ISC specifications are for design guidance only; they are not tested.

 2009-2014 Microchip Technology Inc. DS20002194E-page 3

MCP660/1/2/3/4/5/9
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CS = VSS (refer to Figure 1-2).

Parameters Sym. Min. Typ. Max. Units Conditions

Power Supply
Supply Voltage VDD 2.5 — 5.5 V
Quiescent Current per Amplifier IQ 3 6 9 mA No Load Current
Note 1: See Figure 2-5 for temperature effects.
2: The ISC specifications are for design guidance only; they are not tested.

AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figure 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions
AC Response
Gain-Bandwidth Product GBWP — 60 — MHz
Phase Margin PM — 65 — ° G = +1
Open-Loop Output Impedance ROUT — 10 — 
AC Distortion
Total Harmonic Distortion plus Noise THD + N — 0.003 — % G = +1, VOUT = 2VP-P, f = 1 kHz,
VDD = 5.5V, BW = 80 kHz
Differential Gain, Positive Video DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V,
(Note 1) G = +2, VL = 0V,
DC VIN = 0V to 0.7V
Differential Gain, Negative Video DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V,
(Note 1) G = +2, VL = 0V,
DC VIN = 0V to -0.7V
Differential Phase, Positive Video DP — 0.3 — ° NTSC, VDD = +2.5V, VSS = -2.5V,
(Note 1) G = +2, VL = 0V,
DC VIN = 0V to 0.7V
Differential Phase, Negative Video DP — 0.9 — ° NTSC, VDD = +2.5V, VSS = -2.5V,
(Note 1) G = +2, VL = 0V,
DC VIN = 0V to -0.7V
Step Response
Rise Time, 10% to 90% tr — 5 — ns G = +1, VOUT = 100 mVP-P
Slew Rate SR — 32 — V/µs G = +1
Noise
Input Noise Voltage Eni — 14 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 6.8 — nV/Hz f = 1 MHz
Input Noise Current Density ini 4 — fA/Hz f = 1 kHz
Note 1: These specifications are described in detail in Section 4.3 “Distortion”. (NTSC refers to a National
Television Standards Committee signal.)

DS20002194E-page 4  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figures 1-1 and 2-1).
Parameters Sym. Min. Typ. Max. Units Conditions

CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2VDD V
CS Input Current, Low ICSL — -0.1 — nA CS = 0V

CS High Specifications
CS Logic Threshold, High VIH 0.8VDD — VDD V
CS Input Current, High ICSH — -0.7 — µA CS = VDD
GND Current ISS -2 -1 — µA
CS Internal Pull-Down Resistor RPD — 5 — M
Amplifier Output Leakage IO(LEAK) — 40 — nA CS = VDD, TA = +125°C

CS Dynamic Specifications
CS Input Hysteresis VHYST — 0.25 — V
CS High to Amplifier Off Time tOFF — 200 — ns G = +1 V/V, VL = VSS
(output goes High Z) CS = 0.8VDD to VOUT = 0.1(VDD/2)
CS Low to Amplifier On Time tON — 2 10 µs G = +1 V/V, VL = VSS
CS = 0.2VDD to VOUT = 0.9(VDD/2)

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +2.5V to +5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 201.0 — °C/W
Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W
Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W Note 2
Thermal Resistance, 8L-MSOP θJA — 211 — °C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W
Thermal Resistance, 10L-3x3 DFN θJA — 54.0 — °C/W Note 2
Thermal Resistance, 10L-MSOP θJA — 202 — °C/W
Thermal Resistance, 14L-SOIC θJA — 90.8 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Thermal Resistance, 16L-QFN θJA — 52.1 — °C/W
Note 1: Operation must not cause TJ to exceed the Maximum Junction Temperature specification (+150°C).
2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.

 2009-2014 Microchip Technology Inc. DS20002194E-page 5

MCP660/1/2/3/4/5/9
1.3 Timing Diagram
CF
6.8 pF
1 µA 0 nA
ICS 1 µA
(typical) (typical) (typical) RG RF
10 k 10 k
CS VIL VIH
VP VDD/2
VDD
tON tOFF VIN+

VOUT + CB1 CB2

High Z On High Z
MCP66X 100 nF 2.2 µF
-
-6 mA
-1 µA (typical) -1 µA VIN-
ISS
(typical) (typical)
VM VOUT
RG RF RL CL
FIGURE 1-1: Timing Diagram.
10 k 10 k 1 k 20 pF

1.4 Test Circuits

CF
The circuit used for most DC and AC tests is shown in 6.8 pF VL
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the FIGURE 1-2: AC and DC Test Circuit for
circuit’s common-mode voltage ((VP + VM)/2) and that Most Specifications.
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:
RF
G DM = -------
RG
V DD
VP + -----------
2
V CM = -------------------------
2
V OST = V IN- – V IN+
VDD
VOUT = ----------- +  VP – VM  + V OST  1 + G DM 
2
Where:
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common-Mode (V)
Input Voltage
VOST = Op Amp’s Total Input (mV)
Offset Voltage

DS20002194E-page 6  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.1 DC Signal Inputs

22% 1.4
100 Samples Representative Part
20%
Percentage of Occurrences

TA = +25°C 1.3

Input Offset Voltage (mV)

18% VDD = 2.5V and 5.5V
16% 1.2
14% VDD = 5.5V
1.1
12%
1.0
10%
8% 0.9
6% 0.8 VDD = 2.5V
4%
2% 0.7
0% 0.6
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Offset Voltage (mV) Output Voltage (V)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs.
Output Voltage.

24% 0.0
100 Samples 1 Lot
22%
Percentage of Occurrences

VDD = 2.5V and 5.5V Low (VCMR_L – VSS)

20% TA = -40°C to +125°C -0.1
Mode Headroom (V)
Low Input Common

18%
16%
14% -0.2
VDD = 2.5V
12%
10% -0.3
8%
VDD = 5.5V
6%
4% -0.4
2%
0% -0.5
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125
Input Offset Voltage Drift (µV/°C) Ambient Temperature (°C)

FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Low-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.

0.0 1.4
Representative Part 1 Lot
-0.2 VCM = VSS High (VDD – VCMR_H)
Input Offset Voltage (mV)

-0.4
High Input Common
Mode Headroom (V)

1.3
-0.6
-0.8 VDD = 2.5V
-1.0 1.2
-1.2
+125°C
-1.4 +85°C
+25°C 1.1
-1.6 VDD = 5.5V
-40°C
-1.8
-2.0 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V) Ambient Temperature (°C)

FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: High-Input Common-Mode
Power Supply Voltage with VCM = 0V. Voltage Headroom vs. Ambient Temperature.

 2009-2014 Microchip Technology Inc. DS20002194E-page 7

MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.0 130
VDD = 2.5V
Input Offset Voltage (mV)

1.5

DC Open-Loop Gain (dB)

Representative Part 125
VDD = 5.5V
1.0
-40°C
0.5 +25°C
120
+85°C
0.0 +125° 115 VDD = 2.5V
C
-0.5
110
-1.0
-1.5 105
-2.0
100
0.0

2.0

2.5
-0.5

0.5

1.0

1.5

3.0
-50 -25 0 25 50 75 100 125
Input Common Mode Voltage (V) Ambient Temperature (°C)

FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: DC Open-Loop Gain vs.
Common-Mode Voltage with VDD = 2.5V. Ambient Temperature.

2.0 130
VDD = 5.5V VDD = 5.5V
Input Offset Voltage (mV)

1.5 Representative Part 125

1.0 DC Open-Loop Gain (dB) 120
0.5
+125°
115 VDD = 2.5V
0.0 C
+85°C
-0.5 +25°C 110
40°C
-1.0 105
-1.5
100
-2.0
95
1.0

2.5

4.0

5.5
-0.5
0.0
0.5

1.5
2.0

3.0
3.5

4.5
5.0

6.0

100 1k 10k 100k

1.E+02 1.E+03 1.E+04 1.E+05
Input Common Mode Voltage (V) Load Resistance (Ω)

FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: DC Open-Loop Gain vs.
Common-Mode Voltage with VDD = 5.5V. Load Resistance.

110 1.E-08
10n
VDD = 5.5V
105
Input Bias, Offset Currents

VCM = VCMR_H
100
CMRR, PSRR (dB)

1n
1.E-09
95
90 IB
PSRR
(pA)

85 100p
1.E-10
80
75
CMRR, VDD = 2.5V 10p
1.E-11
70 CMRR, VDD = 5.5V
65 | IOS |
60 1p
1.E-12
-50 -25 0 25 50 75 100 125 25 45 65 85 105 125
Ambient Temperature (°C) Ambient Temperature (°C)

FIGURE 2-9: CMRR and PSRR vs. FIGURE 2-12: Input Bias and Offset
Ambient Temperature. Currents vs. Ambient Temperature with
VDD = 5.5V.

DS20002194E-page 8  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

1.E-03
1m 1000
IB
Input Current Magnitude (A)

Input Bias, Offset Currents

100µ
1.E-04 800
10µ
1.E-05
600
1µ
1.E-06
Representative Part
100n
1.E-07 400

(pA)
TA = +125°C
10n
1.E-08 VDD = 5.5V
200
1n
1.E-09 +125°C
+85°C 0
100p
1.E-10 IOS
+25°C
10p
1.E-11 -40°C -200
1p
1.E-12 -400

1.0

3.5

6.0
0.0
0.5

1.5
2.0
2.5
3.0

4.0
4.5
5.0
5.5
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-13: Input Bias Current vs. Input FIGURE 2-15: Input Bias and Offset
Voltage (below VSS). Currents vs. Common-Mode Input Voltage with
TA = +125°C.

60
IB
Input Bias, Offset Currents

40
20
0
IOS
-20
(pA)

-40
-60
Representative Part
-80
TA = +85°C
-100 VDD = 5.5V

-120
5.0
5.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5

Common Mode Input Voltage (V)

FIGURE 2-14: Input Bias and Offset

Currents vs. Common-Mode Input Voltage with
TA = +85°C.

 2009-2014 Microchip Technology Inc. DS20002194E-page 9

MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.2 Other DC Voltages and Currents

1000 9
Output Voltage Headroom

8
VDD = 5.5V
7

Supply Current
(mA/amplifier)
100 6
5
(mV)

VOL – VSS VDD = 2.5V

4
10 3 +125°C
+85°C
2 +25°C
1 -40°C
VDD – VOH
1 0

0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.1 1 10 100
Output Current Magnitude (mA) Power Supply Voltage (V)

FIGURE 2-16: Output Voltage Headroom FIGURE 2-19: Supply Current vs. Power
vs. Output Current. Supply Voltage.

45 7
RL = 1 kΩ
40
6
Output Headroom (mV)

VOL – VSS
35 VDD = 5.5V
Supply Current

5
(mA/amplifier)

VDD = 5.5V
30 VDD = 2.5V
25 4

20 3
15 2
10 1
5 VDD = 2.5V VDD – VOH
0
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Common Mode Input Voltage (V)

FIGURE 2-17: Output Voltage Headroom FIGURE 2-20: Supply Current vs.
vs. Ambient Temperature. Common-Mode Input Voltage.

100
Output Short Circuit Current

80
60
+125°C
40 +85°C
20 +25°C
(mA)

-40°C
0
-20
-40
-60
-80
-100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5

Power Supply Voltage (V)

FIGURE 2-18: Output Short Circuit Current

vs. Power Supply Voltage.

DS20002194E-page 10  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.3 Frequency Response

100 80 80
90 75 75

Gain Bandwidth Product

80 70 70
CMRR, PSRR (dB)

Phase Margin (°)

70 65 PM 65

(MHz)
60 VDD = 5.5V
60 VDD = 2.5V 60
50 55 55
CMRR
40 50 50
PSRR+
30 PSRR-
45
GBWP
45
20 40 40
10

-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
100
1.E+2 1k
1.E+3 10k
1.E+4 100k
1.E+5 1M
1.E+6 10M
1.E+7
Frequency (Hz) Common Mode Input Voltage (V)

FIGURE 2-21: CMRR and PSRR vs. FIGURE 2-24: Gain-Bandwidth Product
Frequency. and Phase Margin vs. Common-Mode Input
Voltage.

140 0 80 80
120 -30 Gain Bandwidth Product 75 75
Open-Loop Gain (dB)

Open-Loop Phase (°)

100 -60 70 70

Phase Margin (°)

AOL PM
80 -90 65 65
VDD = 5.5V
(MHz)

60 VDD = 2.5V 60
60 -120
55 55
40 -150
50 GBWP
50
20 | AOL | -180
45 45
0 -210
40 40
-20 -240 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1 1.E+
1.E+ 10 1.E+
100 1.E+
1k 10k
1.E+ 100k 1M 10M
1.E+ 1.E+ 1.E+ 100M 1G
1.E+ 1.E+
0 1 2 Frequency (Hz)
3 4 5 6 7 8 9 Output Voltage (V)

FIGURE 2-22: Open-Loop Gain vs. FIGURE 2-25: Gain-Bandwidth Product

Frequency. and Phase Margin vs. Output Voltage.
Closed-Loop Output Impedance (Ω)

80 80 100

75 75
Gain Bandwidth Product

70 70
Phase Margin (°)

10 G = 101 V/V
65 PM 65
G = 11 V/V
(MHz)

60 VDD = 5.5V 60 G = 1 V/V

VDD = 2.5V
55 55
1
50 50
45 GBWP 45
40 40
0.1
-50 -25 0 25 50 75 100 125 10k 100k 1M 10M 100M
1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
Ambient Temperature (°C) Frequency (Hz)

FIGURE 2-23: Gain-Bandwidth Product FIGURE 2-26: Closed-Loop Output

and Phase Margin vs. Ambient Temperature. Impedance vs. Frequency.

 2009-2014 Microchip Technology Inc. DS20002194E-page 11

MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

10 150
RS = 0Ω
9 140 RS = 100Ω
8 130 RS = 1 kΩ

Separation; RTI (dB)

Channel-to-Channel
Gain Peaking (dB)

7 120 VCM = VDD/2

GN = 1 V/V G = +1 V/V
6 GN = 2 V/V 110
5 GN  4 V/V 100
4 90
3 80
2 70
RS = 10 kΩ
1 60 RS = 100 kΩ
0 50
10p 100p 1n 1k 10k 100k 1M 10M
1.0E-11 1.0E-10 1.0E-09 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Normalized Capacitive Load; CL/GN (F) Frequency (Hz)

FIGURE 2-27: Gain Peaking vs. FIGURE 2-28: Channel-to-Channel

Normalized Capacitive Load. Separation vs. Frequency.

DS20002194E-page 12  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.4 Noise and Distortion

10µ
1.E+4
Input Noise Voltage Density (V/Hz)

20
Representative Part
15

Input Noise; eni(t) (µV)

1µ
1.E+3 10
5

100n
1.E+2 0
-5

10n
1.E+1
-10 Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
-15 VOS = -953 µV
-20
1n
1.E+0
0.1
1.E-1 1
1.E+0 10
1.E+1 100
1.E+2 1k
1.E+3 10k
1.E+4 100k 1M 1.E+7
1.E+5 1.E+6 10M 0 5 10 15 20 25 30 35 40 45 50 55 60 65
Frequency (Hz) Time (min)

FIGURE 2-29: Input Noise Voltage Density FIGURE 2-32: Input Noise vs. Time with
vs. Frequency. 0.1 Hz Filter.

200 1
VDD = 5.0V
Input Noise Voltage Density

180 VOUT = 2 VP-P

160 VDD = 2.5V
THD + Noise (%) 0.1
140
(nV/Hz)

120 G = 1 V/V
VDD = 5.5V BW = 22 Hz to > 500 kHz
100 0.01
G = 11 V/V
80
60
40 0.001 BW = 22 Hz to 80 kHz
20 f = 100 Hz
0
0.0001
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0

100
1.E+2 1k
1.E+3 10k
1.E+4 100k
1.E+5
Common Mode Input Voltage (V) Frequency (Hz)

FIGURE 2-30: Input Noise Voltage Density FIGURE 2-33: THD+N vs. Frequency.
vs. Input Common-Mode Voltage with
f = 100 Hz.

20 0.2 0.2
Positive Video
Input Noise Voltage Density

0.1 Negative Video 0.1

18
16 0.0 0.0
Gain Magnitude (%)

-0.1 -0.1
14
Gain Phase (°)
-0.2 -0.2
Change in

Change in
(nV/Hz)

12 VDD = 2.5V VDD = 5.5V -0.3 -0.3

∆(|G|)
10 -0.4 Representative Part -0.4
VDD = 2.5V
8 -0.5 -0.5
VSS = -2.5V
-0.6 -0.6
6 VL = 0V
-0.7 RL = 150Ω -0.7
4 -0.8 Normalized to DC VIN = 0V -0.8
2 -0.9 NTSC -0.9
f = 1 MHz ∆(G)
0 -1.0 -1.0
0.5

3.0

5.5
-0.5
0.0

1.0
1.5
2.0
2.5

3.5
4.0
4.5
5.0

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

Common Mode Input Voltage (V) DC Input Voltage (V)

FIGURE 2-31: Input Noise Voltage Density FIGURE 2-34: Change in Gain Magnitude
vs. Input Common-Mode Voltage with f = 1 MHz. and Phase vs. DC Input Voltage.

 2009-2014 Microchip Technology Inc. DS20002194E-page 13

MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.5 Time Response

VDD = 5.5V 5.5

VDD = 5.5V
5.0
Output Voltage (10 mV/div)

G=1 G = -1
4.5 RF = 402Ω

Output Voltage (V)

4.0
3.5 VIN
3.0
VIN VOUT
2.5
2.0
1.5 VOUT

1.0
0.5
0.0
0 20 40 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600
Time (ns) Time (ns)

FIGURE 2-35: Non-Inverting Small Signal FIGURE 2-38: Inverting Large Signal Step
Step Response. Response.

5.5 7
VDD = 5.5V VDD = 5.5V
5.0 Input, Output Voltages (V)
G=1 6 G=2
4.5
VOUT
Output Voltage (V)

4.0 5
3.5 VIN
4
3.0
3
2.5
VIN VOUT
2.0 2
1.5 1
1.0
0.5 0
0.0 -1
0 100 200 300 400 500 600 700 800 0 1 2 3 4 5 6 7 8 9 10
Time (ns) Time (µs)

FIGURE 2-36: Non-Inverting Large Signal FIGURE 2-39: The MCP660/1/2/3/4/5/9

Step Response. Family Shows No Input Phase Reversal with
Overdrive.

50
VIN Falling Edge
45
Output Voltage (10 mV/div)

VDD = 5.5V
40
Slew Rate (V/µs)

35
VDD = 5.5V 30
G = -1 25
RF = 402Ω VDD = 2.5V
20
15 Rising Edge
10
VOUT 5
0
0 50 100 150 200 250 300 350 400 450 500 -50 -25 0 25 50 75 100 125
Time (ns) Ambient Temperature (°C)

FIGURE 2-37: Inverting Small Signal Step FIGURE 2-40: Slew Rate vs. Ambient
Response. Temperature.

DS20002194E-page 14  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

10
Maximum Output Voltage

VDD = 5.5V
Swing (VP-P)

VDD = 2.5V

0.1
100k
1.E+05 1M
1.E+06 10M
1.E+07 100M
1.E+08
Frequency (Hz)

FIGURE 2-41: Maximum Output Voltage

Swing vs. Frequency.

 2009-2014 Microchip Technology Inc. DS20002194E-page 15

MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

2.6 Chip Select Response

1.0 0.40
CS = VDD
0.9 0.35
0.8
0.30

CS Hysteresis (V)
CS Current (µA)

0.7 VDD = 5.5V

0.6 0.25
0.5 0.20
0.4 0.15 VDD = 2.5V
0.3
0.10
0.2
0.1 0.05
0.0 0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V) Ambient Temperature (°C)

FIGURE 2-42: CS Current vs. Power FIGURE 2-45: CS Hysteresis vs. Ambient
Supply Voltage. Temperature.

3.0 5
VDD = 2.5V
2.5 G=1
CS Turn On Time (µs)
CS VL = 0V 4
2.0

1.5 3
VDD = 2.5V
VOUT
1.0
CS, VOUT (V)

2
On
0.5
1
VDD = 5.5V
0.0
Off Off
-0.5 0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
Time (µs) Ambient Temperature (°C)

FIGURE 2-43: CS and Output Voltages vs. FIGURE 2-46: CS Turn-On Time vs.
Time with VDD = 2.5V. Ambient Temperature.

6 8
VDD = 5.5V Representative Part
CS G= 1 7
5
CS Pull-down Resistor

VL = 0V
6
4
5
3
(MΩ)

VOUT 4
2
CS, VOUT (V)

On 3
1 2
0 1
Off Off
-1 0
0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125
Time (µs) Ambient Temperature (°C)

FIGURE 2-44: CS and Output Voltages vs. FIGURE 2-47: CS’s Pull-Down Resistor
Time with VDD = 5.5V. (RPD) vs. Ambient Temperature.

DS20002194E-page 16  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS.

0.0 1.E-06
1µ
CS = VDD CS = VDD = 5.5V

Output Leakage Current (A)

-0.2
Negative Power Supply

-0.4 100n
1.E-07
Current; ISS (µA)

-0.6
+125°C
-0.8 10n
1.E-08
-1.0
+85°C
-1.2 +125°C 1n
1.E-09
-1.4 +85°C
+25°C
-1.6 -40°C 100p
1.E-10
-1.8
+25°C
-2.0 10p
1.E-11
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Power Supply Voltage (V) Output Voltage (V)

FIGURE 2-48: Quiescent Current in FIGURE 2-49: Output Leakage Current vs.
Shutdown vs. Power Supply Voltage. Output Voltage.

 2009-2014 Microchip Technology Inc. DS20002194E-page 17

MCP660/1/2/3/4/5/9
NOTES:

DS20002194E-page 18  2009-2014 Microchip Technology Inc.

 3.0 PIN DESCRIPTIONS
 2009-2014 Microchip Technology Inc.

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP660 MCP661 MCP662 MCP663 MCP664 MCP665 MCP669

2x3 TDFN
4x4 QFN

4x4 QFN
SOT-23

SOT-23
TSSOP

TSSOP
Symbol Description

MSOP,

MSOP
SOIC,

SOIC,
SOIC

SOIC

SOIC
DFN

DFN
5 6 2 2 4 2 2 2 4 2 2 2 1 VIN-, VINA- Inverting Input (op amp A)
4 5 3 3 3 3 3 3 3 3 3 3 2 VIN+, VINA+ Non-inverting Input (op amp A)
3 4 7 7 5 8 8 7 6 4 10 10 3 VDD Positive Power Supply
10 10 — — — 5 5 — — 5 7 7 4 VINB+ Non-inverting Input (op amp B)
9 9 — — — 6 6 — — 6 8 8 5 VINB- Inverting Input (op amp B)
8 8 — — — 7 7 — — 7 9 9 6 VOUTB Output (op amp B)
— — — — — — — — — — — — 7 CSBC Chip Select Digital Input (op amps B and C)
14 14 — — — — — — — 8 — — 8 VOUTC Output (op amp C)
13 13 — — — — — — — 9 — — 9 VINC- Inverting Input (op amp C)
12 12 — — — — — — — 10 — — 10 VINC+ Non-inverting Input (op amp C)

MCP660/1/2/3/4/5/9
11 11 4 4 2 4 4 4 2 11 4 4 11 VSS Negative Power Supply
— — — — — — — — — 12 — — 12 VIND+ Inverting Input (op amp D)
— — — — — — — — — 13 — — 13 VIND- Inverting Input (op amp D)
— — — — — — — — — 14 — — 14 VOUTD Output (op amp D)
— — — — — — — — — — — — 15 CSAD Chip Select Digital Input (op amps A and D)
6 7 6 6 1 1 1 6 1 1 1 1 16 VOUT, VOUTA Output (op amp A)
17 — — 9 — — 9 — — — — 11 17 EP Exposed Thermal Pad (EP); must be
DS20002194E-page 19

connected to VSS
— — — 8 — — — 8 5 — 5 5 — CS, CSA Chip Select Digital Input (op amp A)
— — — — — — — — — — 6 6 — CSB Chip Select Digital Input (op amp B)
1, 2, 7, 1, 2, 3 1, 5, 8 1, 5 — — — 1, 5 — — — — — NC No Internal Connection
15, 16
MCP660/1/2/3/4/5/9
3.1 Analog Outputs 3.4 Chip Select Digital Input (CS)
The analog output pins (VOUT) are low-impedance The input (CS) is a CMOS, Schmitt-triggered input that
voltage sources. places the part into a low-power mode of operation.

3.2 Analog Inputs 3.5 Exposed Thermal Pad (EP)

The non-inverting and inverting inputs (VIN+, VIN-, …) There is an internal connection between the exposed
are high-impedance CMOS inputs with low bias thermal pad (EP) and the VSS pin; they must be
currents. connected to the same potential on the printed circuit
board (PCB).
3.3 Power Supply Pins This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
The positive power supply (VDD) is 2.5V to 5.5V higher
thermal resistance (JA).
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In that case, VSS is connected to
Ground and VDD is connected to the supply. VDD will
need bypass capacitors.

DS20002194E-page 20  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
4.0 APPLICATIONS When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
The MCP660/1/2/3/4/5/9 family is manufactured using
the Microchip state-of-the-art CMOS process. It is
designed for low-cost, low-power and high-speed VDD
applications. Its low supply voltage, low quiescent
current and wide bandwidth make the
D1 D2
MCP660/1/2/3/4/5/9 ideal for battery-powered
R1
applications. MCP66X
V1
VOUT
4.1 Input V2
R2
4.1.1 PHASE REVERSAL
V SS –  minimum expected V1 
The input devices are designed to not exhibit phase R1  ------------------------------------------------------------------------
inversion when the input pins exceed the supply 2 mA
voltages. Figure 2-39 shows an input voltage V SS –  minimum expected V2 
exceeding both supplies with no phase inversion. R2  ------------------------------------------------------------------------
2 mA
4.1.2 INPUT VOLTAGE AND CURRENT FIGURE 4-2: Protecting the Analog
LIMITS Inputs.
The electrostatic discharge (ESD) protection on the
It is also possible to connect the diodes to the left of the
inputs can be depicted as shown in Figure 4-1. This
resistors R1 and R2. If so, the currents through the
structure was chosen to protect the input transistors
diodes D1 and D2 need to be limited by some other
and to minimize input bias current (IB). The input ESD
mechanism. The resistors then serve as in-rush current
diodes clamp the inputs when they try to go more than
limiters; the DC current into the input pins (VIN+ and
one diode drop below VSS. They also clamp any
VIN-) should be very small.
voltages that go too far above VDD; their breakdown
voltage is high enough to allow normal operation and A significant amount of current can flow out of the
low enough to bypass quick ESD events within the inputs (through the ESD diodes) when the
specified limits. common-mode voltage (VCM) is below ground (VSS);
see Figure 2-13. Applications that are high-impedance
may need to limit the usable voltage range.

Bond 4.1.3 NORMAL OPERATION

VDD
Pad
The input stage of the MCP660/1/2/3/4/5/9 op amps
uses a differential PMOS input stage. It operates at low
common-mode input voltages (VCM), with VCM
VIN+ Bond Input Bond V -
IN
between VSS – 0.3V and VDD – 1.3V. To ensure proper
Pad Stage Pad operation, the input offset voltage (VOS) is measured at
both VCM = VSS – 0.3V and VCM = VDD – 1.3V. See
Figures 2-5 and 2-6 for temperature effects.

VSS Bond When operating at very low non-inverting gains, the

Pad output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-3.
FIGURE 4-1: Simplified Analog Input ESD
Structures. VDD
In order to prevent damage and/or improper operation VIN MCP66X
+
of these amplifiers, the circuit must limit the currents VOUT
-
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-2 shows
the recommended approach to protecting these inputs. V SS  V IN
The internal ESD diodes prevent the input pins (VIN+ V OUT  V DD – 1.3V
and VIN-) from going too far below ground, while the
resistors R1 and R2 limit the possible current drawn out FIGURE 4-3: Unity-Gain Voltage
of the input pins. Diodes D1 and D2 prevent the input Limitations for Linear Operation.
pins (VIN+ and VIN-) from going too far above VDD and
dump any currents onto VDD.

 2009-2014 Microchip Technology Inc. DS20002194E-page 21

MCP660/1/2/3/4/5/9
4.2 Rail-to-Rail Output Figure 4-5 shows the power calculations used for a
single op amp:
4.2.1 MAXIMUM OUTPUT VOLTAGE • RSER is 0 in most applications and can be used
The Maximum Output Voltage (see Figures 2-16 to limit IOUT.
and 2-17) describes the output range for a given load. • VOUT is the op amp’s output voltage.
For example, the output voltage swings to within 50 mV • VL is the voltage at the load.
of the negative rail with a 1 k load tied to VDD/2.
• VLG is the load’s ground point.
4.2.2 OUTPUT CURRENT • VSS is usually ground (0V).

Figure 4-4 shows the possible combinations of output The input currents are assumed to be negligible. The
voltage (VOUT) and output current (IOUT), when currents shown in Figure 4-5 can be approximated
VDD = 5.5V. using Equation 4-1:

IOUT is positive when it flows out of the op amp into the

EQUATION 4-1:
external circuit.
V OUT – V LG
I OUT = IL = ------------------------------
R SER + R L
6.0
5.5 VOH Limited
5.0 (VDD = 5.5V) I DD  I Q + max  0, IOUT 
4.5
4.0 RL = 1 kΩ
RL = 100Ω I SS  – I Q + min  0, IOUT 
-ISC Limited

3.5
+ISC Limited
VOUT (V)

3.0
2.5
RL = 10Ω Where:
2.0
1.5 IQ = Quiescent supply current
1.0
0.5
0.0 VOL Limited
The instantaneous op amp power (POA(t)), RSER power
-0.5 (PRSER(t)) and load power (PL(t)) are calculated in
Equation 4-2:
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120

IOUT (mA)
EQUATION 4-2:
FIGURE 4-4: Output Current.
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT)
4.2.3 POWER DISSIPATION PRSER(t) = IOUT2RSER
Since the output short circuit current (ISC) is specified PL(t) = IL2RL
at ±90 mA (typical), these op amps are capable of both
delivering and dissipating significant power. The maximum op amp power, for resistive loads,
occurs when VOUT is halfway between VDD and VLG or
halfway between VSS and VLG.
VDD
VOUT EQUATION 4-3:
IDD
2
IOUT max  V DD – V LG – V SS 
RSER POAmax  ------------------------------------------------------------
+ 4  RSER + RL 
VL
- MCP66X
IL RL The maximum ambient to junction temperature rise
ISS (TJA) and junction temperature (TJ) can be calculated
VLG using POAmax, the ambient temperature (TA), the
VSS package thermal resistance (JA, found in the
Temperature Specifications table) and the number of
FIGURE 4-5: Diagram for Power op amps in the package (assuming equal power
Calculations. dissipations), as shown in Equation 4-4:

EQUATION 4-4:
TJA = POA  t   JA  nP OAmax  JA
T J = T A + T JA
Where:
n = Number of op amps in the package (1, 2)

DS20002194E-page 22  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
The power derating across temperature for an op amp 4.4 Improving Stability
in a particular package can be easily calculated
(assuming equal power dissipations): 4.4.1 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
EQUATION 4-5: problems for voltage feedback op amps. As the load
T Jmax – T A capacitance increases, the phase margin (stability) of
P OAmax  -------------------------- the feedback loop decreases and the closed-loop
n  JA
bandwidth is reduced. This produces gain peaking in
Where: the frequency response, with overshoot and ringing in
the step response. A unity-gain buffer (G = +1) is the
TJmax = Absolute maximum junction temperature most sensitive to capacitive loads, though all gains
show the same general behavior.
Several techniques are available to reduce TJA for a When driving large capacitive loads with these op
given POAmax: amps (e.g., > 20 pF when G = +1), a small series
• Lower JA resistor at the output (RISO in Figure 4-6) improves the
- Use another package phase margin of the feedback loop by making the
output load resistive at higher frequencies. The
- PCB layout (ground plane, etc.)
bandwidth will generally be lower than bandwidth
- Heat sinks and air flow without the capacitive load.
• Reduce POAmax
- Increase RL
RG RF RISO
- Limit IOUT (using RSER)
VOUT
- Decrease VDD
- CL
4.3 Distortion +
RN MCP66X
Differential gain (DG) and differential phase (DP) refer
to the nonlinear distortion produced by an NTSC or a FIGURE 4-6: Output Resistor, RISO,
phase-alternating line (PAL) video component. The AC
Stabilizes Large Capacitive Loads.
Electrical Specifications table and Figure 2-34 show
the typical performance of the MCP661, configured as Figure 4-7 gives recommended RISO values for
a gain of +2 amplifier (see Figure 4-10), when driving different capacitive loads and gains. The x-axis is the
one back-matched video load (150, for 75 cable). normalized load capacitance (CL/GN), where GN is the
Microchip tests use a sine wave at NTSC’s color circuit’s noise gain. For non-inverting gains, GN and the
sub-carrier frequency of 3.58 MHz, with a 0.286VP-P Signal Gain are equal. For inverting gains, GN is
magnitude. The DC input voltage is changed over a 1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
+0.7V range (positive video) or a -0.7V range (negative
video). 100
DG is the peak-to-peak change in the AC gain
Recommended RISO (Ω)

magnitude (color hue), as the DC level (luminance) is

changed, in percentile units (%). DP is the
peak-to-peak change in the AC gain phase (color
saturation), as the DC level (luminance) is changed, in 10
degree (°) units.
GN = +1
GN  +2

1
10p 100p 1n 10n
1.E-11 1.E-10 1.E-09 1.E-08
Normalized Capacitance; CL/GN (F)

FIGURE 4-7: Recommended RISO Values

for Capacitive Loads.
After selecting RISO for the circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify the value of RISO until the
response is reasonable. Bench evaluation and
simulations with the MCP660/1/2/3/4/5/9 SPICE macro
model are helpful.

 2009-2014 Microchip Technology Inc. DS20002194E-page 23

MCP660/1/2/3/4/5/9
4.4.2 GAIN PEAKING Figures 2-35 and 2-36 show the small signal and large
signal step responses at G = +1 V/V. The unity-gain
Figure 4-8 shows an op amp circuit that represents
buffer usually has RF = 0 and RG open.
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage Figures 2-37 and 2-38 show the small signal and large
and VM is the input). The capacitances CN and CG signal step responses at G = -1 V/V. Since the noise
represent the total capacitance at the input pins; they gain is 2 V/V and CG  10 pF, the resistors were
include the op amp’s common-mode input capacitance chosen to be RF = RG = 401 and RN = 200.
(CCM), board parasitic capacitance and any capacitor It is also possible to add a capacitor (CF) in parallel with
placed in parallel. RF to compensate for the destabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-6.

CN
RN EQUATION 4-6:
MCP66X
VP + Given:
VOUT RF
-
G N1 = 1 + -------
VM RG
RG RF CG
CG G N2 = 1 + -------
CF
1
f F = ---------------------
FIGURE 4-8: Amplifier with Parasitic 2  R F CF
G N1
Capacitance. fZ = f F  ----------
 G N2
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
We need:
CG also reduces the phase margin of the feedback
f GBWP
loop, which becomes less stable. This effect can be fF  ---------------, G N1  G N2
reduced by either reducing CG or RF. 2G N2
CN and RN form a low-pass filter that affects the signal f GBWP
fF  ---------------, G N1  G N2
at VP. This filter has a single real pole at 1/(2RN/CN). 4G N1
The largest value of RF that should be used depends
on the noise gain (see GN in Section 4.4.1
“Capacitive Loads”), CG and the open-loop gain’s
phase shift. Figure 4-9 shows the maximum
recommended RF for several CG values. Some
applications may modify these values to reduce either
output loading or gain peaking (step response
overshoot).

1.E+05
100k
F

GN > +1 V/V
Maximum Recommended R

CG = 10 pF
CG = 32 pF
CG = 100 pF
10k
1.E+04 CG = 320 pF
CG = 1 nF
(Ω)

1k
1.E+03

100
1.E+02
1 10 100
Noise Gain; GN (V/V)

FIGURE 4-9: Maximum Recommended

RF vs. Gain.

DS20002194E-page 24  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
4.5 MCP663 and MCP665 Chip Select 4.7 High Speed PCB Layout
The MCP663 is a single amplifier with Chip Select These op amps are fast enough that a little extra care
(CS). When CS is pulled high, the supply current drops in the printed circuit board (PCB) layout can make a
to 1 µA (typical) and flows through the CS pin to VSS. significant difference in performance. Good PC board
When this happens, the amplifier output is put into a layout techniques will help you achieve the
high-impedance state. By pulling CS low, the amplifier performance shown in the specifications and typical
is enabled. The CS pin has an internal 5 M (typical) performance curves; it will also help minimize
pulldown resistor connected to VSS, so it will go low if electromagnetic compatibility (EMC) issues.
the CS pin is left floating. Figures 1-1, 2-43 and 2-44 Use a solid ground plane. Connect the bypass local
show the output voltage and supply current response to capacitor(s) to this plane with minimal length traces.
a CS pulse. This cuts down inductive and capacitive crosstalk.
The MCP665 is a dual amplifier with two CS pins; CSA Separate digital from analog, low-speed from
controls op amp A and CSB controls op amp B. These high-speed and low-power from high-power. This will
op amps are controlled independently, with an enabled reduce interference.
quiescent current (IQ) of 6 mA/amplifier (typical) and a
disabled IQ of 1 µA/amplifier (typical). The IQ seen at Keep sensitive traces short and straight. Separate
the supply pins is the sum of the two op amps’ IQ; the them from interfering components and traces. This is
typical value for the IQ of the MCP665 will be 2 µA, especially important for high-frequency (low rise time)
6 mA or 12 mA when there are 0, 1 or 2 amplifiers signals.
enabled, respectively. Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim trace
4.6 Power Supply and as close as possible. Connect guard traces to
ground plane at both ends and in the middle for long
With this family of operational amplifiers, the power traces.
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm Use coax cables, or low inductance wiring, to route
for good high-frequency performance. Surface mount, signal and power to and from the PCB. Mutual and self
multilayer ceramic capacitors, or their equivalent, inductance of power wires is often a cause of crosstalk
should be used. and unusual behavior.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
power supplies does not prove to be a problem.

 2009-2014 Microchip Technology Inc. DS20002194E-page 25

MCP660/1/2/3/4/5/9
4.8 Typical Applications 4.8.3 H-BRIDGE DRIVER
Figure 4-12 shows the MCP662 dual op amp used as
4.8.1 50 LINE DRIVER an H-bridge driver. The load could be a speaker or a
Figure 4-10 shows the MCP661 driving a 50 line. The DC motor.
large output current (e.g., see Figure 2-18) makes it
possible to drive a back-matched line (RM2, the 50
line and the 50 load at the far end) to more than ±2V ½ MCP662
VIN +
(the load at the far end sees ±1V). It is worth
mentioning that the 50 line and the 50 load at the far -
end together can be modeled as a simple 50 resistor VOT
to ground. RF RF

RGT RL
MCP66X +2.5V 50
+ Line RGB RF
RM1 VOB
- RM2 -
49.9
-2.5V 49.9 50
VDD/2 + ½ MCP662
RG RF
301 301 FIGURE 4-12: H-Bridge Driver.
This circuit automatically makes the noise gains (GN)
FIGURE 4-10: 50 Line Driver. equal, when the gains are set properly, so that the
frequency responses match well (in magnitude and in
The output headroom limits would be VOL = -2.3V and phase). Equation 4-7 shows how to calculate RGT and
VOH = +2.3V (see Figure 2-16), leaving some design RGB so that both op amps have the same DC gains;
room for the ±2V signal. The open-loop gain (AOL) GDM needs to be selected first.
typically does not decrease significantly with a 100
load (see Figure 2-11). The maximum power dissipated
EQUATION 4-7:
is about 48 mW (see Section 4.2.3 “Power
Dissipation”), so the temperature rise (for the VOT – V OB
G DM  --------------------------  1 V/V
MCP661 in the SOIC-8 package) is under 8°C. VDD
V IN – -----------
2
4.8.2 OPTICAL DETECTOR AMPLIFIER
RF
Figure 4-11 shows a transimpedance amplifier, using R GT = ---------------------
G DM
the MCP661 op amp, in a photo detector circuit. The ------------ – 1
photo detector is a capacitive current source. RF 2
provides enough gain to produce 10 mV at VOUT. CF RF
stabilizes the gain and limits the transimpedance R GB = ------------
GDM
bandwidth to about 1.1 MHz. The parasitic capacitance ------------
2
of RF (e.g., 0.2 pF for a 0805 SMD) acts in parallel with
CF.
Equation 4-8 gives the resulting common-mode and
differential mode output voltages.
CF
1.5 pF EQUATION 4-8:
Photo VOT + V OB
Detector RF VDD
--------------------------- = -----------
100 k 2 2
VOUT V DD
ID CD V OT – VOB = G DM  V IN – -----------
-  2 
100 nA 30 pF
+
MCP661
VDD/2

FIGURE 4-11: Transimpedance Amplifier

for an Optical Detector.

DS20002194E-page 26  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
5.0 DESIGN AIDS 5.4 Analog Demonstration and
Evaluation Boards
Microchip provides the basic design aids needed for
the MCP660/1/2/3/4/5/9 family of op amps. Microchip offers a broad spectrum of analog
demonstration and evaluation boards that are
5.1 SPICE Macro Model designed to help customers achieve faster time to
market. For a complete listing of these boards and their
The latest SPICE macro model for the corresponding user’s guides and technical information,
MCP660/1/2/3/4/5/9 op amps is available on the visit the Microchip web site at
Microchip web site at www.microchip.com. This model www.microchip.com/analog tools.
is intended to be an initial design tool that works well in
the linear region of operation over the temperature Some boards that are especially useful are:
range of the op amp. See the model file for information • MCP6XXX Amplifier Evaluation Board 1,
on its capabilities. part number: MCP6XXXEV-AMP1
Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 2,
cannot be replaced with simulations. Also, simulation part number: MCP6XXXEV-AMP2
results using this macro model need to be validated, by • MCP6XXX Amplifier Evaluation Board 3,
comparing them to the data sheet specifications and part number: MCP6XXXEV-AMP3
characteristic curves. • MCP6XXX Amplifier Evaluation Board 4,
part number: MCP6XXXEV-AMP4
5.2 FilterLab® Software • Active Filter Demo Board Kit,
part number: MCP6XXXDM-FLTR
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation
op amps) design. Available at no cost from the Board, part number: SOIC8EV
Microchip web site at www.microchip.com/filterlab, the • MCP661 Line Driver Demo Board,
FilterLab design tool provides full schematic diagrams part number: MCP661DM-LD
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be 5.5 Design and Application Notes
used with the macro model to simulate actual filter
performance. The following Microchip Analog Design Note and
Application Notes are recommended as supplemental
reference resources. They are available on the
5.3 Microchip Advanced Part Selector
Microchip web site at www.microchip.com/appnotes.
(MAPS)
• ADN003: “Select the Right Operational Amplifier
MAPS is a software tool that helps efficiently identify for your Filtering Circuits”, DS21821
Microchip devices that fit a particular design • AN722: “Operational Amplifier Topologies and DC
requirement. Available at no cost from the Microchip Specifications”, DS00722
web site at www.microchip.com/maps, the MAPS is an
• AN723: “Operational Amplifier AC Specifications
overall selection tool for Microchip’s product portfolio
and Applications”, DS00723
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a filter can be defined to sort features for a • AN884: “Driving Capacitive Loads With Op
parametric search of device and export side-by-side Amps”, DS00884
technical comparison reports. Helpful links are also • AN990: “Analog Sensor Conditioning Circuits –
provided for data sheets, purchase and sampling of An Overview”, DS00990
Microchip parts. • AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the “Signal Chain Design Guide”, DS21825.

 2009-2014 Microchip Technology Inc. DS20002194E-page 27

MCP660/1/2/3/4/5/9
NOTES:

DS20002194E-page 28  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

5-Lead SOT-23 (MCP661) Example

XXNN YX25

6-Lead SOT-23 (MCP663) Example

XXNN JE25

8-Lead TDFN (2x3x0.75 mm) (MCP661) Example

ABJ
423
25

8-Lead DFN (3x3x0.9 mm) (MCP662) Example

Device Code DABQ

1423
MCP662T-E/MF DABQ 256
Note 1: Applies to 8-lead 3x3 DFN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2009-2014 Microchip Technology Inc. DS20002194E-page 29

MCP660/1/2/3/4/5/9
8-Lead MSOP (3x3 mm) (MCP662) Example

662E
423256

8-Lead SOIC (3.90 mm) (MCP661, MCP662, MCP663) Example

MCP661E
SN^^1423
e3
256
NNN

10-Lead DFN (3x3x0.9 mm) (MCP665) Example

Device Code BAFD

1423
MCP665T-E/MF BAFD 256
Note 1: Applies to 10-lead 3x3 DFN

10-Lead MSOP (3x3 mm) (MCP665) Example

665EUN
423256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS20002194E-page 30  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

14-Lead SOIC (3.90 mm) (MCP660, MCP664) Example

MCP660
e3
E/SL^^
1423256

14-Lead TSSOP (4.4 mm) (MCP660, MCP664) Example

XXXXXXXX 664E/ST
YYWW 14/23
256
NNN

16-Lead QFN (4x4x0.9 mm) (MCP669) Example

PIN 1 PIN 1 669

e3
E/ML^^
1423256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2009-2014 Microchip Technology Inc. DS20002194E-page 31

MCP660/1/2/3/4/5/9

     

  .#  #$ # / ! - 0   #  1 /   % # # ! #
## +22--- 2 / 

b
N

E1

1 2 3
e

e1
D

A A2 c φ

A1 L

L1

3# 44""
  4# 5 56 7
5$8 %1 5 (
4 !1# ()*
6$# ! 4 !1#  )*
6,  9  #   : (
! !1 / /  ; : 
# !%%   : (
6,  <!# "  : 
! !1 / <!# "  : ;
6,  4  #   : 
.#4  # 4  : =
.# # 4 ( : ;
.#   > : >
4 !/  ; : =
4 !<!# 8  : (
  
     !"!#$! !%  #$  !%  #$    # & !  ! 
     !#    "'(
)*+ )     #  & #, $  --#$##   
     - * )

DS20002194E-page 32  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 33

MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

N 4

E
E1

PIN 1 ID BY
LASER MARK
1 2 3

e
e1

A A2 c φ

L
A1
L1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 6
Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0.89 – 1.30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0.60
Footprint L1 0.35 – 0.80
Foot Angle I 0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-028B

DS20002194E-page 34  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 35

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 36  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 37

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 38  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 39

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 40  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 41

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 42  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 43

MCP660/1/2/3/4/5/9

    !"#$%&'*+,

  .#  #$ # / ! - 0   #  1 /   % # # ! #
## +22--- 2 / 

DS20002194E-page 44  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 45

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 46  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

  . /  # 014!55&$7'*./

  .#  #$ # / ! - 0   #  1 /   % # # ! #
## +22--- 2 / 

 2009-2014 Microchip Technology Inc. DS20002194E-page 47

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 48  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 49

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 50  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 51

MCP660/1/2/3/4/5/9

UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 52  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 53

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 54  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 55

MCP660/1/2/3/4/5/9

  .#  #$ # / ! - 0   #  1 /   % # # ! #
## +22--- 2 / 

DS20002194E-page 56  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 57

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20002194E-page 58  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 59

MCP660/1/2/3/4/5/9

89  ;/  # 014!<5<5&$%'*;/

  .#  #$ # / ! - 0   #  1 /   % # # ! #
## +22--- 2 / 

D D2

EXPOSED
PAD

E E2
2 2 b

1 1

K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW

A A3

A1

3# 44""
  4# 5 56 7
5$8 %1 5 =
1# =()*
6,  9  #  ;  
# !%%    (
*# #/  ".
6,  <!# " )*
"&  !1 !<!# " ( =( ;
6,  4  #  )*
"&  !1 !4  #  ( =( ;
*# #<!# 8 (  (
*# #4  # 4   (
*# # # "&  !1 ! {  : :
  
 1, $ ! &% #$  , 08$#$ #8  # !-##  # !  
 1 /   -  $ # !
     !#    "'(
)*+ )     #  & #, $  --#$##   
".+  %     0$ $ -#$##   0%% # $  
     - * )

DS20002194E-page 60  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc. DS20002194E-page 61

MCP660/1/2/3/4/5/9
NOTES:

DS20002194E-page 62  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
APPENDIX A: REVISION HISTORY Revision B (September 2011)
The following is the list of modifications:
Revision E (July 2014)
1. Added the MCP660, MCP664 and MCP669
The following is the list of modifications: amplifiers to the product family and the related
1. Updated the Features: list. information throughout the document.
2. Updated the Typical Application Circuit and 2. Added the 4x4 QFN (16L) package option for
added the High Gain-Bandwidth Op Amp MCP660 and MCP669, SOIC and TSSOP (14L)
Portfolio table in the Features: section. package options for MCP660 and MCP665 and
the related information throughout the
3. Updated Figures 4-6, 4-10 and 4-11.
document. Updated the Package Types
4. Updated the Section 6.0 “Packaging drawing with pin designation for each new
Information” and Section 6.1 “Package package.
Marking Information” sections.
3. Updated the Temperature Specifications table to
5. Minor typographical changes. show the temperature specifications for new
packages.
Revision D (March 2012) 4. Updated Table 3-1 to show all the pin functions.
The following is the list of modifications: 5. Updated Section 6.0 “Packaging
Information” with markings for the new
Added the MSOP (8L) package for MCP662 and
additions. Added the corresponding SOIC and
all related information throughout the document.
TSSOP (14L), and 4x4 QFN (16L) package
options and related information.
Revision C (November 2011) 6. Updated table description and examples in
The following is the list of modifications: Product Identification System.
1. Added the SOT-23 (5L) and TDFN (8L) package
option for MCP661 and SOT-23 (6L) package Revision A (July 2009)
options for MCP663 and the related information Original release of this document.
throughout the document. Updated Package
Types drawing with pin designation for each
new package.
2. Updated the Temperature Specifications table to
show the temperature specifications for new
packages.
3. Updated Table 3-1 to show all the pin functions.
4. Updated Section 6.0 “Packaging
Information” with markings for the new
additions. Added the corresponding SOT-23 (5L
and 6L) and 2x3 TDFN (8L) package options
and related information.
5. Updated table description and examples in the
Product Identification System section.

 2009-2014 Microchip Technology Inc. DS20002194E-page 63

MCP660/1/2/3/4/5/9
NOTES:

DS20002194E-page 64  2009-2014 Microchip Technology Inc.

 MCP660/1/2/3/4/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:
PART NO. -X /XX
a) MCP660T-E/ML: Tape and Reel
Device Temperature Package Extended temperature,
Range 16LD QFN package
b) MCP660T-E/SL: Tape and Reel
Extended temperature,
Device: MCP660 Triple Op Amp 14LD SOIC package
MCP660T Triple Op Amp (Tape and Reel) c) MCP660T-E/ST: Tape and Reel
(SOIC, TSSOP, QFN) Extended temperature,
MCP661 Single Op Amp 14LD TSSOP package
MCP661T Single Op Amp (Tape and Reel)
(SOIC, SOT-23 and TDFN) d) MCP661T-E/SN: Tape and Reel
MCP662 Dual Op Amp Extended temperature,
MCP662T Dual Op Amp (Tape and Reel) 8LD SOIC package
(DFN, MSOP and SOIC) e) MCP661T-E/MNY: Tape and Reel,
MCP663 Single Op Amp with CS Extended Temperature,
MCP663T Single Op Amp with CS (Tape and Reel) 8LD TDFN package
(SOIC and SOT-23)
MCP664 Quad Op Amp f) MCP662T-E/MF: Tape and Reel
MCP664T Quad Op Amp (Tape and Reel) Extended temperature,
(SOIC, TSSOP) 8LD DFN package
MCP665 Dual Op Amp with CS
g) MCP662T-E/MS: Tape and Reel
MCP665T Dual Op Amp with CS (Tape and Reel)
Extended temperature,
(DFN and MSOP)
8LD MSOP package
MCP669 Quad Op Amp with CS
MCP669T Quad Op Amp with CS (Tape and Reel) h) MCP662T-E/SN: Tape and Reel
(QFN) Extended temperature,
8LD SOIC package

Temperature E = -40°C to +125°C i) MCP663T-E/SN: Tape and Reel

Range: Extended temperature,
8LD SOIC package
j) MCP663T-E/CHY: Tape and Reel,
Package: CHY = Plastic Small Outline (SOT-23), 6-lead Extended Temperature,
MF = Plastic Dual Flat, No Lead (3×3 DFN), 6LD SOT-23 package
8-lead, 10-lead
ML = Plastic Quad Flat, No Lead Package (4x4 QFN), k) MCP664T-E/SL: Tape and Reel
(4x4x0.9 mm), 16-lead Extended temperature,
MNY= Plastic Dual Flat, No Lead (2x3 TDFN), 14LD SOIC package
8-lead l) MCP664T-E/ST: Tape and Reel
MS = Plastic Micro Small Outline (MSOP), 8-lead Extended temperature,
OT = Plastic Small Outline (SOT-23), 5-lead 14LD TSSOP package
SL = Plastic Small Outline, Narrow, (3.90 mm SOIC),
14-lead m) MCP665T-E/MF: Tape and Reel
SN = Plastic Small Outline (3.90 mm), 8-lead Extended temperature,
ST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP), 10LD DFN package
14-lead n) MCP665T-E/UN: Tape and Reel
UN = Plastic Micro Small Outline (MSOP), 10-lead Extended temperature,
10LD MSOP package
* Y = Nickel palladium gold manufacturing designator.
Only available on the TDFN package.
o) MCP669T-E/ML: Tape and Reel
Extended temperature,
16LD QFN package

 2009-2014 Microchip Technology Inc. DS20002194E-page 65

MCP660/1/2/3/4/5/9
NOTES:

DS20002194E-page 66  2009-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-368-6

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2009-2014 Microchip Technology Inc. DS20002194E-page 67

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2943-5100 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-3019-1500 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 33-1-69-30-90-79
www.microchip.com Japan - Osaka
Fax: 61-2-9868-6755 Germany - Dusseldorf
Atlanta Tel: 81-6-6152-7160
China - Beijing Tel: 49-2129-3766400
Duluth, GA Fax: 81-6-6152-9310
Tel: 86-10-8569-7000 Germany - Munich
Tel: 678-957-9614 Japan - Tokyo
Fax: 86-10-8528-2104 Tel: 49-89-627-144-0
Fax: 678-957-1455 Tel: 81-3-6880- 3770
China - Chengdu Fax: 49-89-627-144-44
Austin, TX Fax: 81-3-6880-3771
Tel: 86-28-8665-5511 Germany - Pforzheim
Tel: 512-257-3370 Korea - Daegu
Fax: 86-28-8665-7889 Tel: 49-7231-424750
Boston Tel: 82-53-744-4301
Westborough, MA China - Chongqing Fax: 82-53-744-4302 Italy - Milan
Tel: 774-760-0087 Tel: 86-23-8980-9588 Tel: 39-0331-742611
Korea - Seoul
Fax: 774-760-0088 Fax: 86-23-8980-9500 Fax: 39-0331-466781
Tel: 82-2-554-7200
Chicago China - Hangzhou Fax: 82-2-558-5932 or Italy - Venice
Itasca, IL Tel: 86-571-8792-8115 82-2-558-5934 Tel: 39-049-7625286
Tel: 630-285-0071 Fax: 86-571-8792-8116 Netherlands - Drunen
Malaysia - Kuala Lumpur
Fax: 630-285-0075 China - Hong Kong SAR Tel: 60-3-6201-9857 Tel: 31-416-690399
Cleveland Tel: 852-2943-5100 Fax: 60-3-6201-9859 Fax: 31-416-690340
Independence, OH Fax: 852-2401-3431 Poland - Warsaw
Malaysia - Penang
Tel: 216-447-0464 China - Nanjing Tel: 48-22-3325737
Tel: 60-4-227-8870
Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 60-4-227-4068 Spain - Madrid
Dallas Fax: 86-25-8473-2470 Tel: 34-91-708-08-90
Philippines - Manila
Addison, TX China - Qingdao Fax: 34-91-708-08-91
Tel: 63-2-634-9065
Tel: 972-818-7423 Tel: 86-532-8502-7355 Fax: 63-2-634-9069 Sweden - Stockholm
Fax: 972-818-2924
Fax: 86-532-8502-7205 Tel: 46-8-5090-4654
Singapore
Detroit China - Shanghai Tel: 65-6334-8870 UK - Wokingham
Novi, MI Tel: 86-21-5407-5533 Fax: 65-6334-8850 Tel: 44-118-921-5800
Tel: 248-848-4000 Fax: 86-21-5407-5066
Taiwan - Hsin Chu Fax: 44-118-921-5820
Houston, TX
China - Shenyang Tel: 886-3-5778-366
Tel: 281-894-5983
Tel: 86-24-2334-2829 Fax: 886-3-5770-955
Indianapolis Fax: 86-24-2334-2393
Noblesville, IN Taiwan - Kaohsiung
China - Shenzhen Tel: 886-7-213-7830
Tel: 317-773-8323
Tel: 86-755-8864-2200
Fax: 317-773-5453 Taiwan - Taipei
Fax: 86-755-8203-1760 Tel: 886-2-2508-8600
Los Angeles
China - Wuhan Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 86-27-5980-5300 Thailand - Bangkok
Tel: 949-462-9523
Fax: 86-27-5980-5118 Tel: 66-2-694-1351
Fax: 949-462-9608
China - Xian Fax: 66-2-694-1350
New York, NY
Tel: 631-435-6000 Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110 China - Xiamen
Tel: 86-592-2388138
Canada - Toronto
Fax: 86-592-2388130
Tel: 905-673-0699
Fax: 905-673-6509 China - Zhuhai
Tel: 86-756-3210040
03/25/14
Fax: 86-756-3210049

DS20002194E-page 68  2009-2014 Microchip Technology Inc.