MCP6401/1R/1U/2/4/6/7/9

1 MHz, 45 µA Op Amps
Features Description
• Low Quiescent Current: 45 µA (typical) The Microchip Technology Inc.
• Gain Bandwidth Product: 1 MHz (typical) MCP6401/1R/1U/2/4/6/7/9 family of operational
• Rail-to-Rail Input and Output amplifiers (op amps) has low quiescent current
(45 µA, typical) and rail-to-rail input and output
• Supply Voltage Range: 1.8V to 6.0V
operation. This family is unity gain stable and has a
• Unity Gain Stable gain bandwidth product of 1 MHz (typical). These
• Extended Temperature Ranges: devices operate with a power supply voltage of 1.8V to
- -40°C to +125°C (E temp) 6.0V. These features make the family of op amps well
- -40°C to +150°C (H temp) suited for single-supply, battery-powered applications.
• No Phase Reversal The MCP6401/1R/1U/2/4/6/7/9 family is designed with
Microchip’s advanced CMOS process and offered in
Applications single, dual and quad packages. The devices are
available in two extended temperature ranges (E temp
• Portable Equipment
and H temp) with different package types, which
• Battery Powered System
makes them well-suited for automotive and industrial
• Medical Instrumentation
applications.
• Automotive Electronics
• Data Acquisition Equipment
• Sensor Conditioning
• Analog Active Filters

Design Aids
• SPICE Macro Models
• FilterLab® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes

Typical Application

R2

D2

VIN R1
VOUT
MCP6401
D1

Precision Half-Wave Rectifier

© 2009-2011 Microchip Technology Inc. DS22229D-page 1

MCP6401/1R/1U/2/4/6/7/9
E Temp Package Types H Temp Package Types

MCP6401 MCP6401R MCP6401 MCP6402

SC70-5, SOT-23-5 SOT-23-5 SOT-23-5 SOIC
VOUT 1 5 VDD VOUT 1 5 VSS VOUT 1 5 VDD VOUTA 1 8 VDD
VSS 2 VDD 2 VSS 2 VINA– 2 7 VOUTB
VIN+ 3 4 VIN– VIN+ 3 4 VIN– VIN+ 3 4 VIN– V + 3 6 VINB–
INA
VSS 4 5 VINB+

MCP6402 MCP6401U
SOIC SOT-23-5 MCP6404 MCP6406
SOIC SOT-23-5
VOUTA 1 8 VDD VIN+ 1 5 VDD
VINA– 2
VOUTA 1 14 VOUTD VOUT 1 5 VDD
7 VOUTB VSS 2
VINA– 2 13 V – VSS 2
VINA+ 3 IND
6 VINB– VIN– 3 4 VOUT
VINA+ 3 12 VIND+ VIN+ 3 4 VIN–
VSS 4 5 VINB+
VDD 4 11 VSS
VINB+ 5 10 VINC+
MCP6402 MCP6404 VINB– 6 9 VINC–
2x3 TDFN SOIC, TSSOP
VOUTB 7 8 VOUTC
VOUTA 1 8 VDD VOUTA 1 14 VOUTD
V – 13 VIND–
VINA– 2 EP 7 VOUTB INA 2 MCP6409
MCP6407
9 V + 12 VIND+
VINA+ 3 6 VINB– INA 3 SOIC
SOIC
VSS 4 5 V + VDD 4
INB
11 VSS
VOUTA 1 8 VDD VOUTA 1 14 VOUTD
VINB+ 5 10 VINC+
VINA– 2 7 V VINA– 2 13 VIND–
VINB– 6 9 VINC– OUTB
VINA+ 3 6 VINB– VINA+ 3 12 VIND+
VOUTB 7 8 VOUTC
VSS 4 5 V + VDD 4
INB
11 VSS
VINB+ 5 10 VINC+
* Includes Exposed Thermal Pad (EP); see Table 3-1.
VINB– 6 9 VINC–
E temp: -40°C to +125°C
VOUTB 7 8 VOUTC

H temp: -40°C to +150°C

DS22229D-page 2 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
CHARACTERISTICS
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
1.1 Absolute Maximum Ratings † above those indicated in the operational listings of this
VDD – VSS ........................................................................7.0V specification is not implied. Exposure to maximum rat-
ing conditions for extended periods may affect device
Current at Input Pins .....................................................±2 mA
reliability.
Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V
†† See Section 4.1.2 “Input Voltage Limits”.
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ) .......................... +155°C
ESD Protection on All Pins (HBM; MM; CDM)....≥ 4 kV; 300V,
1500V

1.2 MCP6401/1R/1U/2/4 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8v to +6.0v, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, VL = VDDD/2 and RL = 100 kΩ to VL (Refer to Figure 1-1).
Parts
Parameters Sym Min Typ Max Units Temp Conditions
(Note 1)
Input Offset
Input Offset Voltage VOS -4.5 ±0.8 +4.5 mV E, H VCM = VSS
— ±1.0 — mV +125°C E
— ±1.5 — mV +150°C H
Input Offset Drift with ΔVOS/ΔTA — ±2.0 — µV/°C -40°C E VCM = VSS
Temperature to
+125°C
— ±2.5 — µV/°C -40°C H
to
+150°C
Power Supply PSRR 63 78 — dB E, H VCM = VSS
Rejection Ratio — 75 — dB +125°C E
— 73 — dB +150°C H
Input Bias Current and Impedance
Input Bias Current IB — 1 100 pA E, H
— 30 — pA +85°C E, H
— 800 — pA +125°C E
— 7 — nA +150°C H
Input Offset Current IOS — 1 — pA E, H
— 5 — pA +85°C E, H
— 20 — pA +125°C E
— 45 — pA +150°C H
Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands
for the one whose operating temperature range is from -40°C to +150°C.
2: Figure 2-14 shows how VCMR changes across temperature.

© 2009-2011 Microchip Technology Inc. DS22229D-page 3

MCP6401/1R/1U/2/4/6/7/9
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8v to +6.0v, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, VL = VDDD/2 and RL = 100 kΩ to VL (Refer to Figure 1-1).
Parts
Parameters Sym Min Typ Max Units Temp Conditions
(Note 1)
Common Mode Input ZCM — 1013||6 — Ω||pF E, H
Impedance
Differential Input ZDIFF — 1013||6 — Ω||pF E, H
Impedance
Common Mode
Common Mode Input VCMR VSS-0.20 — VDD+0.20 V E, H VDD = 1.8V
Voltage Range VSS-0.05 — VDD+0.05 V +125°C E
(Note 2)
VSS — VDD V +150°C H
VSS-0.30 — VDD+0.30 V E, H VDD = 6.0V
VSS-0.15 — VDD+0.15 V +125°C E
VSS-0.10 — VDD+0.10 V +150°C H
Common Mode CMRR 56 71 — dB E, H VCM = -0.2V to 2.0V,
Rejection Ratio VDD = 1.8V
— 68 — dB +125°C E VCM = -0.05V to 1.85V,
VDD = 1.8V
— 65 — dB +150°C H VCM = 0V to 1.8V,
VDD = 1.8V
63 78 — dB E, H VCM = -0.3V to 6.3V,
VDD = 6.0V
— 76 — dB +125°C E VCM = -0.15V to 6.15V,
VDD = 6.0V
— 75 — dB +150°C H VCM = -0.1V to 6.1V,
VDD = 6.0V
Open-Loop Gain
DC Open-Loop Gain AOL 90 110 — dB E, H VOUT = 0.3V to VDD-
(Large Signal) — 105 — dB +125°C E 0.3V,
VCM = VSS
— 100 — dB +150°C H
Output
High-Level Output VOH 1.790 1.792 — V E, H VDD = 1.8V
Voltage — 1.788 — V +125°C E RL = 10 kΩ
0.5V input overdrive
— 1.785 — V +150°C H
5.980 5.985 — V E, H VDD = 6.0V
— 5.980 — V +125°C E RL = 10 kΩ
0.5V input overdrive
— 5.975 — V +150°C H
Low-Level Output VOL — 0.008 0.010 V E, H VDD = 1.8V
Voltage — 0.012 — V +125°C E RL = 10 kΩ
0.5V input overdrive
— 0.015 — V +150°C H
— 0.015 0.020 V E, H VDD = 6.0V
— 0.020 — V +125°C E RL = 10 kΩ
0.5V input overdrive
— 0.025 — V +150°C H
Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands
for the one whose operating temperature range is from -40°C to +150°C.
2: Figure 2-14 shows how VCMR changes across temperature.

DS22229D-page 4 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8v to +6.0v, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, VL = VDDD/2 and RL = 100 kΩ to VL (Refer to Figure 1-1).
Parts
Parameters Sym Min Typ Max Units Temp Conditions
(Note 1)
Output Short-Circuit ISC — ±5 — mA E, H VDD = 1.8V
Current — ±15 — mA E, H VDD = 6.0V
Power Supply
Supply Voltage VDD 1.8 — 6.0 V E, H
Quiescent Current IQ 20 45 70 µA E, H IO = 0, VDD = 5.0V
per Amplifier — 55 — µA +125°C E VCM = 0.2VDD
— 60 — µA +150°C H
Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands
for the one whose operating temperature range is from -40°C to +150°C.
2: Figure 2-14 shows how VCMR changes across temperature.

AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Parts Conditions
AC Response
Gain Bandwidth Product GBWP — 1 — MHz E, H
Phase Margin PM — 65 — ° E, H G = +1 V/V
Slew Rate SR — 0.5 — V/µs E, H
Noise
Input Noise Voltage Eni — 3.6 — µVp-p E, H f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 28 — nV/√Hz E, H f = 1 kHz
Input Noise Current Density ini — 0.6 — fA/√Hz E, H f = 1 kHz

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C E temp parts (Note 1)
TA -40 — +150 °C H temp parts (Note 1)
Storage Temperature Range TA -65 — +155 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W
Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +155°C.

© 2009-2011 Microchip Technology Inc. DS22229D-page 5

MCP6401/1R/1U/2/4/6/7/9
1.3 MCP6406/7/9 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND,
VCM = VDD/2, VOUT » VDD/2, VL = VDD/2 and RL = 100 kΩ to VL (Refer to Figure 1-1).
Parts
Parameters Sym Min Typ Max Units Temp Conditions
(Note 1)
Input Offset
Input Offset Voltage VOS -4.5 — +4.5 mV E, H VCM = VSS
-5.0 ±1.0 +5.0 mV +125°C E
-5.5 ±1.5 +5.5 mV +150°C H
Input Offset Drift ΔVOS/DTA — ±2.0 — µV/°C -40°C E VCM = VSS
with Temperature to
+125°C
— ±2.5 — µV/°C -40°C H
to
+150°C
Power Supply PSRR 63 78 — dB E, H VCM = VSS
Rejection Ratio 60 75 — dB +125°C E
58 73 — dB +150°C H
Input Bias Current and Impedance
Input Bias Current IB — ±1 100 pA E, H
— 30 — pA +85°C E, H
— 800 2000 pA +125°C E
— 7 12 nA +150°C H
Input Offset Current IOS — 1 — pA E, H
— 5 — pA +85°C E, H
— 20 — pA +125°C E
— 45 — pA +150°C H
Common Mode ZCM — 1013||6 — Ω||pF E, H
Input Impedance
Differential Input ZDIFF — 1013||6 — Ω||pF E, H
Impedance
Common Mode
Common Mode VCMR VSS-0.20 — VDD+0.20 V E, H VDD = 1.8V
Input Voltage Range VSS-0.05 — VDD+0.05 V +125°C E
(Note 2)
VSS — VDD V +150°C H
VSS-0.30 — VDD+0.30 V E, H VDD = 6.0V
VSS-0.15 — VDD+0.15 V +125°C E
VSS-0.10 — VDD+0.10 V +150°C H
Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands
for the one whose operating temperature range is from -40°C to +150°C.
2: Figure 2-14 shows how VCMR changes across temperature.

DS22229D-page 6 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND,
VCM = VDD/2, VOUT » VDD/2, VL = VDD/2 and RL = 100 kΩ to VL (Refer to Figure 1-1).
Parts
Parameters Sym Min Typ Max Units Temp Conditions
(Note 1)
Common Mode CMRR 56 71 — dB E, H VCM = -0.2V to 2.0V,
Rejection Ratio VDD = 1.8V
53 68 — dB +125°C E VCM = -0.05V to 1.85V,
VDD = 1.8V
50 65 — dB +150°C H VCM = 0V to 1.8V,
VDD = 1.8V
63 78 — dB E, H VCM = -0.3V to 6.3V,
VDD = 6.0V
61 76 — dB +125°C E VCM = -0.15V to 6.15V,
VDD = 6.0V
60 75 — dB +150°C H VCM = -0.1V to 6.1V,
VDD = 6.0V
Open-Loop Gain
DC Open-Loop Gain AOL 90 110 — dB E, H VOUT = 0.3V to
(Large Signal) 88 105 — dB +125°C E VDD-0.3V, VCM = VSS
85 100 — dB +150°C H
Output
High-Level Output VOH 1.790 1.792 — V E, H VDD = 1.8V
Voltage 1.785 1.788 — V +125°C E RL = 10 kΩ
0.5V input overdrive
1.782 1.785 — V +150°C H
5.980 5.985 — V E, H VDD = 6.0V
5.970 5.980 — V +125°C E RL = 10 kΩ
0.5V input overdrive
5.965 5.975 — V +150°C H
Low-Level Output VOL — 0.008 0.010 V E, H VDD = 1.8V
Voltage — 0.012 0.015 V +125°C E RL = 10 kΩ
0.5V input overdrive
— 0.015 0.018 V +150°C H
— 0.015 0.020 V E, H VDD = 6.0V
— 0.020 0.030 V +125°C E RL = 10 kΩ
0.5V input overdrive
— 0.025 0.035 V +150°C H
Output Short-Circuit ISC — ±5 — mA E, H VDD = 1.8V
Current — ±15 — mA E, H VDD = 6.0V
Power Supply
Supply Voltage VDD 1.8 — 6.0 V E, H
Quiescent Current IQ 20 45 70 µA E, H IO = 0, VDD = 5.0V
per Amplifier 30 55 80 µA +125°C E VCM = 0.2VDD
35 60 90 µA +150°C H
Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands
for the one whose operating temperature range is from -40°C to +150°C.
2: Figure 2-14 shows how VCMR changes across temperature.

© 2009-2011 Microchip Technology Inc. DS22229D-page 7

MCP6401/1R/1U/2/4/6/7/9
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Part Conditions
AC Response
Gain Bandwidth Product GBWP — 1 — MHz E, H
Phase Margin PM — 65 — ° E, H G = +1 V/V
Slew Rate SR — 0.5 — V/µs E, H
Noise
Input Noise Voltage Eni — 3.6 — µVp-p E, H f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 28 — nV/√Hz E, H f = 1 kHz
Input Noise Current Density ini — 0.6 — fA/√Hz E, H f = 1 kHz

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C E temp parts (Note 1)
TA -40 — +150 °C H temp parts (Note 1)
Storage Temperature Range TA -65 — +155 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +155°C.

1.4 Test Circuits

CF
The circuit used for most DC and AC tests is shown in
6.8 pF
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common Mode voltage ((VP + VM)/2), and that RG RF
VOST includes VOS plus the effects (on the input offset 100 kΩ 100 kΩ
error, VOST) of temperature, CMRR, PSRR and AOL. VP VDD/2
VDD
VIN+
EQUATION 1-1:
CB1 CB2
G DM = RF ⁄ RG MCP640x 100 nF 1 µF
V CM = ( V P + VDD ⁄ 2 ) ⁄ 2
V OST = VIN– – V IN+ VIN–
V OUT = ( VDD ⁄ 2 ) + ( VP – V M ) + V OST ( 1 + GDM ) VM VOUT
RG RF RL CL
Where: 100 kΩ 60 pF
100 kΩ 100 kΩ
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common Mode (V) CF
Input Voltage 6.8 pF VL
VOST = Op Amp’s Total Input Offset (mV) FIGURE 1-1: AC and DC Test Circuit for
Voltage
Most Specifications.

DS22229D-page 8 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

24% 45%
1760 Samples 1760 Samples
Percentage of Occurences

Percentage of Occurences
21% 40%
VCM = VSS VCM = VSS
35% TA = -40°C to +125°C
18%
30%
15%
25%
12% 20%
9% 15%
6% 10%
3% 5%
0%
0%
-10 -8 -6 -4 -2 0 2 4 6 8 10
-5 -4 -3 -2 -1 0 1 2 3 4 5
Input Offset Voltage Drift (μV/°C)
Input Offset Voltage (mV)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift.

24% 50%
Percentage of Occurences

Percentage of Occurences
45%
21% 1200 Samples
1200 Samples
VCM = VSS
40% VCM = VSS
18% TA = -40°C to +150°C
TA = +125ºC 35%
15% 30%
12% 25%
9% 20%
6% 15%
10%
3%
5%
0%
0%
-5 -4 -3 -2 -1 0 1 2 3 4 5
-10 -8 -6 -4 -2 0 2 4 6 8 10
Input Offset Voltage (mV) Input Offset Voltage Drift (μV/°C)

FIGURE 2-2: Input Offset Voltage. FIGURE 2-5: Input Offset Voltage Drift.

24% 1000
800
Percentage of Occurences

Input Offset Voltage (μV)

21% 1200 Samples VDD = 6.0V TA = +25°C

VCM = VSS 600 Representative TA = -40°C
18% TA = +150ºC Part
400
15% 200
12% 0
-200
9%
-400 TA = +150°C
6% -600 TA = +125°C
TA = +85°C
3% -800
0% -1000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5

-5 -4 -3 -2 -1 0 1 2 3 4 5
Input Offset Voltage (mV) Common Mode Input Voltage (V)

FIGURE 2-3: Input Offset Voltage. FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 6.0V.

© 2009-2011 Microchip Technology Inc. DS22229D-page 9

MCP6401/1R/1U/2/4/6/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

1400 1,000
1200 VDD = 1.8V

Input Noise Voltage Density

Input Offset Voltage (μV)

Representative
1000 Part
800
600

(nV/√Hz)
400
200 TA = +150°C 100
0 TA = +125°C
TA = +85°C
-200 TA = +25°C
-400 TA = -40°C
-600
-800
10
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
0.1
0.1 11 1010 100
100 1k
1000 10k
10000 100k
100000
Common Mode Input Voltage (V) Frequency (Hz)

FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Noise Voltage Density
Common Mode Input Voltage with VDD = 1.8V. vs. Frequency.

1000
40

Input Noise Voltage Density

750
Input Offset Voltage (µV)

35
500 30
250 25
(nV/√Hz)
VDD = 6.0V
0 20
-250 VDD = 1.8V 15
-500 10
Representative Part f = 1 kHz
-750 5 VDD = 6.0 V

-1000 0
0.0
0.5

5.5
6.0
6.5
-0.5

1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0

Output Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Noise Voltage Density
Output Voltage. vs. Common Mode Input Voltage.

200 100
Representative Part
Input Offset Voltage (μV)

100 TA = +150°C 90 PSRR+

Representative Part
TA = +125°C
80
CMRR, PSRR (dB)

0
CMRR
-100 70 PSRR-
60
-200
50
-300 TA = +85°C
TA = +25°C 40
-400 TA = -40°C
30
-500
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
10
10 100
100 1k
1000 10k
10000 100k
100000 1M
1000000
Power Supply Voltage (V) Frequency (Hz)

FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: CMRR, PSRR vs.
Power Supply Voltage. Frequency.

DS22229D-page 10 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

90 10000
PSRR (VDD = 1.8V to 6.0V)
85 TA = +150°C

Input Bias Current (pA)

1000
CMRR,PSRR (dB)

80
75 TA = +125°C

70 100

65 CMRR (VDD = 6.0V)

60 10 TA = +85°C
CMRR (VDD = 1.8V)
55 VDD = 6.0V

50 1

0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50 -25 0 25 50 75 100 125 150
Ambient Temperature (°C) Common Mode Input Voltage (V)

FIGURE 2-13: CMRR, PSRR vs. Ambient FIGURE 2-16: Input Bias Current vs.
Temperature. Common Mode Input Voltage.

0.4 65
Common Mode Input Voltage

0.3 60
VDD = 6.0V

Quiescent Current
0.2 55 VDD = 5.0V
Range Limits (V)

VCMR_H - VOH @ VDD = 6.0V

(μA/Amplifier)
VDD = 1.8V
@ VDD = 1.8V 50
0.1
0.0 45
-0.1 VCMR_L - VSS @ VDD = 1.8V
40
VOL - VSS @ VDD = 6.0V 35
-0.2
-0.3 30 VCM = 0.2VDD

-0.4 25
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Ambient Temperature (°C) Ambient Temperature (°C)

FIGURE 2-14: Common Mode Input FIGURE 2-17: Quiescent Current vs.
Voltage Range Limits vs. Ambient Temperature. Ambient Temperature.

10000 80
Input Bias Current, Input Offset

70 VCM = 0.2VDD TA = +150°C

VDD = 6.0V
Quiescent Current

1000 60
(μA/Amplifier)
Current (pA)

50
Input Bias Current 40
100
30 TA = +125°C
TA = +85°C
20 TA = +25°C
10
TA = -40°C
10
Input Offset Current
0
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0

25 50 75 100 125 150

Ambient Temperature (°C) Power Supply Voltage (V)

FIGURE 2-15: Input Bias, Offset Current FIGURE 2-18: Quiescent Current vs.
vs. Ambient Temperature. Power Supply Voltage.

© 2009-2011 Microchip Technology Inc. DS22229D-page 11

MCP6401/1R/1U/2/4/6/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

120 0 1.6 90

Gain Bandwidth Product (MHz)

Open-Loop Gain 1.5 85
100 -30
Open-Loop Gain (dB)

Open-Loop Phase (°)

1.4 80

Phase Margin (°)

Phase Margin
80 -60
1.3 75
Open-Loop Phase
60 -90 1.2 70

40 -120 1.1 65
1.0 60
20 -150 Gain Bandwidth Product
0.9 55
0 -180 0.8 VDD = 6.0V 50
VDD = 6.0V
-20 -210 0.7 45
1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
0.1 1 10 100 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125 150
Frequency (Hz) Temperature (°C)

FIGURE 2-19: Open-Loop Gain, Phase vs. FIGURE 2-22: Gain Bandwidth Product,
Frequency. Phase Margin vs. Ambient Temperature.

150 1.6 90

Gain Bandwidth Product (MHz)

145 1.5 85
DC Open-Loop Gain (dB)

140 1.4 Phase Margin 80

Phase Margin (°)

135 1.3 75
130 1.2 70
125
1.1 65
120
1.0 60
115
R L = 10 kΩ 0.9 55
110 Gain Bandwidth Product
VSS + 0.3V < V OUT < V DD - 0.3V
105 0.8 VDD = 1.8V 50
100 0.7 45
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 150
Power Supply Voltage (V) Temperature (°C)

FIGURE 2-20: DC Open-Loop Gain vs. FIGURE 2-23: Gain Bandwidth Product,
Power Supply Voltage. Phase Margin vs. Ambient Temperature.

150 25
Output Short Circuit Current

145
DC Open-Loop Gain (dB)

VDD = 6.0V
140 20 TA = -40°C
135 TA = +25°C
TA = +85°C
130 15 TA = +125°C
(mA)

125 TA = +150°C
120 VDD = 1.8V 10
115
110 5
105 Large Signal AOL
100 0
0.00 0.05 0.10 0.15 0.20 0.25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0

Output Voltage Headroom

Power Supply Voltage (°V)
VDD - VOH or VOL-VSS (V)

FIGURE 2-21: DC Open-Loop Gain vs. FIGURE 2-24: Output Short Circuit Current
Output Voltage Headroom. vs. Power Supply Voltage.

DS22229D-page 12 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

10 0.9
VDD = 6.0V
Output Voltage Swing (V P-P)

0.8 Falling Edge, VDD = 6.0V

Rising Edge, VDD = 6.0V
0.7

Slew Rate (V/μs)

VDD = 1.8V
0.6

1 0.5
0.4
0.3
Falling Edge, VDD = 1.8V
0.2 Rising Edge, VDD = 1.8V

0.1
0.1
100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 150
100 1000 10000 100000 1000000 Temperature (°C)
Frequency (Hz)

FIGURE 2-25: Output Voltage Swing vs. FIGURE 2-28: Slew Rate vs. Ambient
Frequency. Temperature.

1000
Output Voltage Headroom

Output Voltage (20 mv/div)

VDD - VOH @ VDD = 1.8V
100
VOL - VSS @ VDD = 1.8V
(mV)

10

VDD = 6.0V
1 VDD - VOH @ VDD = 6.0V
VOL - VSS @ VDD = 6.0V G = +1 V/V
RL = 10 kΩ
0.1
0.01
10 0.1
100 1
1000 10
10000
Output Current (mA) Time (2 µs/div)

FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Small Signal Non-Inverting
vs. Output Current. Pulse Response.

24
VDD - VOH @ VDD = 6.0V
Output Voltage Headroom
VDD - VOH or VOL - VSS (mV)

21
Output Voltage (20 mv/div)

VOL - VSS@ VDD = 6.0V

18
VDD = 6.0V
15
G = -1 V/V
12
9
6
VDD - VOH @ VDD = 1.8V
3 VOL - VSS @ VDD = 1.8V

0
-50 -25 0 25 50 75 100 125 150
Ambient Temperature (°C) Time (2 µs/div)

FIGURE 2-27: Output Voltage Headroom FIGURE 2-30: Small Signal Inverting Pulse
vs. Ambient Temperature. Response.

© 2009-2011 Microchip Technology Inc. DS22229D-page 13

MCP6401/1R/1U/2/4/6/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF.

6.0 10000
5.5
5.0

Closed Loop Output

1000
4.5

Impedance ()
Output Voltage (V)

4.0
3.5 100
3.0
2.5 VDD = 6.0V GN:
2.0 G = +1 V/V 10 101 V/V
1.5 11 V/V
1 V/V
1.0
0.5 1
1.0E+01 1.0E+02 1.0E+031.0E+04 1.0E+05 1.0E+06
0.0 10 100 1k 10k 100k 1M
Time (20 µs/div) Frequency (Hz)

FIGURE 2-31: Large Signal Non-Inverting FIGURE 2-34: Closed Loop Output
Pulse Response. Impedance vs. Frequency.

6.0 1m
1.00E-03

5.5 100μ
1.00E-04

5.0 10μ
1.00E-05

4.5
Output Voltage (V)

VDD = 6.0V 1μ
1.00E-06

4.0 G = -1 V/V -IIN (A)

TA = -40°C
100n
1.00E-07

3.5 TA = +25°C
3.0 10n
1.00E-08
TA = +85°C
TA = +125°C
2.5 1n
1.00E-09
TA = +150°C
2.0 100p
1.00E-10

1.5 10p
1.00E-11

1.0
1p
1.00E-12

0.5
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
0.0 VIN (V)
Time (20 µs/div)

FIGURE 2-32: Large Signal Inverting Pulse FIGURE 2-35: Measured Input Current vs.
Response. Input Voltage (below VSS).

7.0 150
Channel to Channel Separation

6.0 140
Input, Output Voltages (V)

VOUT
5.0 130
VIN
4.0
120
(dB)

3.0
110
2.0
100
1.0 VDD = 6.0V
Input Referred
0.0 G = +2 V/V 90

-1.0 80
100
100
1k
1000
10k
10000
100k
100000

Time (0.1 ms/div) Frequency (Hz)

FIGURE 2-33: The FIGURE 2-36: Channel-to-Channel

MCP6401/1R/1U/2/4/6/7/9 Shows No Phase Separation vs. Frequency (MCP6402/4/7/9 only).
Reversal.

DS22229D-page 14 © 2009-2011 Microchip Technology Inc.

 3.0 PIN DESCRIPTIONS
© 2009-2011 Microchip Technology Inc.

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE 1

MCP6401 MCP6401R MCP6401U MCP6402 MCP6404 MCP6406 MCP6407 MCP6409
SC70-5, 2x3 SOIC, Symbol Description
SOT-23-5 SOT-23-5 SOIC SOT-23-5 SOIC SOIC
SOT-23-5 TDFN TSSOP
1 1 4 1 1 1 1 1 1 VOUT, VOUTA Analog Output (op amp A)
4 4 3 2 2 2 4 2 2 VIN–, VINA– Inverting Input (op amp A)
3 3 1 3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A)
5 2 5 8 8 4 5 8 4 VDD Positive Power Supply
— — — 5 5 5 — 5 5 VINB+ Non-inverting Input (op amp B)
— — — 6 6 6 — 6 6 VINB– Inverting Input (op amp B)
— — — 7 7 7 — 7 7 VOUTB Analog Output (op amp B)
— — — — — 8 — — 8 VOUTC Analog Output (op amp C)
— — — — — 9 — — 9 VINC– Inverting Input (op amp C)

MCP6401/1R/1U/2/4/6/7/9
— — — — — 10 — — 10 VINC+ Non-inverting Input (op amp C)
2 5 2 4 4 11 2 4 11 VSS Negative Power Supply
— — — — — 12 — — 12 VIND+ Non-inverting Input (op amp D)
— — — — — 13 — — 13 VIND– Inverting Input (op amp D)
— — — — — 14 — — 14 VOUTD Analog Output (op amp D)
— — — — 9 — — — — EP Exposed Thermal Pad (EP); must be
connected to VSS.
DS22229D-page 15
MCP6401/1R/1U/2/4/6/7/9
3.1 Analog Output (VOUT)
The output pin is low-impedance voltage source.

3.2 Analog Inputs (VIN+, VIN-)

The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.

3.3 Power Supply Pin (VDD, VSS)

The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.

DS22229D-page 16 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
4.0 APPLICATION INFORMATION
VDD
The MCP6401/1R/1U/2/4/6/7/9 family of op amps is
manufactured using Microchip’s state-of-the-art CMOS
process and is specifically designed for low-power, D1 D2 U1
high-precision applications.
V1
VOUT
4.1 Rail-to-Rail Input MCP640x
V2
4.1.1 PHASE REVERSAL
The MCP6401/1R/1U/2/4/6/7/9 op amps are designed
to prevent phase reversal when the input pins exceed FIGURE 4-2: Protecting the Analog
the supply voltages. Figure 2-33 shows the input Inputs.
voltage exceeding the supply voltage with no phase A significant amount of current can flow out of the
reversal. inputs when the Common Mode voltage (VCM) is below
ground (VSS); See Figure 2-35.
4.1.2 INPUT VOLTAGE LIMITS
4.1.3 INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at In order to prevent damage and/or improper operation
the input pins (see Section 1.1 “Absolute Maximum of these amplifiers, the circuit must limit the currents
Ratings †”). into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to Figure 4-3 shows one approach to protecting these
protect the input transistors against many (but not all) inputs. The resistors R1 and R2 limit the possible
over-voltage conditions, and to minimize the input bias currents in or out of the input pins (and the ESD diodes,
current (IB). D1 and D2). The diode currents will go through either
VDD or VSS.

VDD
VDD Bond
Pad

D1 D2 U1
Bond Bond V1
VIN+ Input VIN– VOUT
Pad Stage Pad R1
MCP640x
V2
R2
VSS Bond VSS – min(V1, V2)
Pad min(R1,R2) >
2 mA
FIGURE 4-1: Simplified Analog Input ESD max(V1,V2) – VDD
min(R1,R2) >
Structures. 2 mA
The input ESD diodes clamp the inputs when they try FIGURE 4-3: Protecting the Analog
to go more than one diode drop below VSS. They also Inputs.
clamp any voltages that go well above VDD; their
4.1.4 NORMAL OPERATION
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow The input stage of the MCP6401/1R/1U/2/4/6/7/9 op
over-voltage (beyond VDD) events. Very fast ESD amps use two differential input stages in parallel. One
events (that meet the spec) are limited so that damage operates at a low Common Mode input voltage (VCM),
does not occur. while the other operates at a high VCM. With this
topology, the device operates with a VCM up to 300 mV
In some applications, it may be necessary to prevent above VDD and 300 mV below VSS (see Figure 2-14).
excessive voltages from reaching the op amp inputs; The input offset voltage is measured at VCM = VSS –
Figure 4-2 shows one approach to protecting these 0.3V and VDD + 0.3V to ensure proper operation.
inputs.
The transition between the input stages occurs when
VCM is near VDD – 1.1V (see Figures 2-6 and 2-7). For
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.

© 2009-2011 Microchip Technology Inc. DS22229D-page 17

MCP6401/1R/1U/2/4/6/7/9
4.2 Rail-to-Rail Output After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
The output voltage range of the response overshoot. Modify RISO’s value until the
MCP6401/1R/1U/2/4/6/7/9 op amps is VSS + 20 mV response is reasonable. Bench evaluation and
(minimum) and VDD – 20 mV (maximum) when simulations with the MCP6401/1R/1U/2/4/6/7/9 SPICE
RL = 10 kΩ is connected to VDD/2 and VDD = 6.0V. macro model are very helpful.
Refer to Figures 2-26 and 2-27 for more information.
4.4 Supply Bypass
4.3 Capacitive Loads
With this family of operational amplifiers, the power
Driving large capacitive loads can cause stability supply pin (VDD for single-supply) should have a local
problems for voltage feedback op amps. As the load bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
capacitance increases, the feedback loop’s phase for good high frequency performance. It can use a bulk
margin decreases and the closed-loop bandwidth is capacitor (i.e., 1 µF or larger) within 100 mm to provide
reduced. This produces gain peaking in the frequency large, slow currents. This bulk capacitor can be shared
response, with overshoot and ringing in the step with other analog parts.
response. While a unity-gain buffer (G = +1 V/V) is the
most sensitive to capacitive loads, all gains show the
4.5 Unused Op Amps
same general behavior.
When driving large capacitive loads with these op An unused op amp in quad packages (MCP6404 or
amps (e.g., > 100 pF when G = +1 V/V), a small series MCP6409) should be configured as shown in Figure 4-
resistor at the output (RISO in Figure 4-4) improves the 6. These circuits prevent the output from toggling and
feedback loop’s phase margin (stability) by making the causing crosstalk. Circuit A sets the op amp at its
output load resistive at higher frequencies. The minimum noise gain. The resistor divider produces any
bandwidth will be generally lower than the bandwidth desired reference voltage within the output voltage
with no capacitance load. range of the op amp, which buffers that reference
voltage. Circuit B uses the minimum number of
components and operates as a comparator, but it may
draw more current.
– RISO
MCP640x VOUT
¼ MCP6404 (A) ¼ MCP6404 (B)
VIN +
CL VDD
VDD
R1 VDD
FIGURE 4-4: Output Resistor, RISO
Stabilizes Large Capacitive Loads. VREF
R2
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the R2
VREF = VDD × -------------------
Signal Gain are equal. For inverting gains, GN is R 1 + R2
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-6: Unused Op Amps.
10000
VDD = 6.0 V
(Ω)

RL = 10 kΩ
1000
ISO
Recommended R

100 GN:
1 V/V
2 V/V
10 ≥ 5 V/V

1
10p
1.E-11 100p 1.E-09
1.E-10 1n 10n
1.E-08 0.1µ
1.E-07 1µ
1.E-06
Normalized Load Capacitance; CL/GN (F)

FIGURE 4-5: Recommended RISO Values

for Capacitive Loads.

DS22229D-page 18 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
4.6 PCB Surface Leakage 4.7 Application Circuits
In applications where low input bias current is critical, 4.7.1 PRECISION HALF-WAVE
Printed Circuit Board (PCB) surface leakage effects
RECTIFIER
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board. The precision half-wave rectifier, which is also known
Under low humidity conditions, a typical resistance as a super diode, is a configuration obtained with an
between nearby traces is 1012Ω. A 5V difference would operational amplifier in order to have a circuit behave
cause 5 pA of current to flow; which is greater than the like an ideal diode and rectifier. It effectively cancels the
MCP6401/1R/1U/2/4/6/7/9 family’s bias current at forward voltage drop of the diode so that very low level
+25°C (±1.0 pA, typical). signals can still be rectified with minimal error. This can
be useful for high-precision signal processing. The
The easiest way to reduce surface leakage is to use a
MCP6401/1R/1U/2/4/6/7/9 op amps have high input
guard ring around sensitive pins (or traces). The guard
impedance, low input bias current and rail-to-rail
ring is biased at the same voltage as the sensitive pin.
input/output, which makes this device suitable for
An example of this type of layout is shown in
precision rectifier applications.
Figure 4-7.
Figure 4-8 shows a precision half-wave rectifier and its
transfer characteristic. The rectifier’s input impedance
is determined by the input resistor R1. To avoid loading
Guard Ring VIN– VIN+ VSS
effect, it must be driven from a low-impedance source.
When VIN is greater than zero, D1 is OFF, D2 is ON, and
VOUT is zero. When VIN is less than zero, D1 is ON, D2
is OFF, and VOUT is the VIN with an amplification of
-R2/R1.
The rectifier circuit shown in Figure 4-8 has the benefit
that the op amp never goes in saturation, so the only
FIGURE 4-7: Example Guard Ring Layout thing affecting its frequency response is the
amplification and the gain bandwidth product.
for Inverting Gain.
.

1. Non-inverting Gain and Unity-Gain Buffer:

a) Connect the non-inverting pin (VIN+) to the R2
input with a wire that does not touch the
PCB surface. D2
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the VIN R1
Common Mode input voltage.
VOUT
2. Inverting Gain and Transimpedance Gain
MCP6401
Amplifiers (convert current to voltage, such as
photo detectors): D1
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
Precision Half-Wave Rectifier
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
VOUT
with a wire that does not touch the PCB
surface.
-R2/R1

VIN

Transfer Characteristic

FIGURE 4-8: Precision Half-Wave

Rectifier.

© 2009-2011 Microchip Technology Inc. DS22229D-page 19

MCP6401/1R/1U/2/4/6/7/9
4.7.2 BATTERY CURRENT SENSING 4.7.3 INSTRUMENTATION AMPLIFIER
The MCP6401/1R/1U/2/4/6/7/9 op amps’ Common The MCP6401/1R/1U/2/4/6/7/9 op amps are well
Mode Input Range, which goes 0.3V beyond both suited for conditioning sensor signals in battery-
supply rails, supports their use in high-side and low- powered applications. Figure 4-10 shows a two op amp
side battery current sensing applications. The low instrumentation amplifier, using the MCP6402, that
quiescent current (45 µA, typical) helps prolong battery works well for applications requiring rejection of
life, and the rail-to-rail output supports detection of low Common Mode noise at higher gains. The reference
currents. voltage (VREF) is supplied by a low impedance source.
Figure 4-9 shows a high-side battery current sensor In single supply applications, VREF is typically VDD/2.
circuit. The 10Ω resistor is sized to minimize power
losses. The battery current (IDD) through the 10Ω RG
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the Common VREF R1 R2 R2 R1 VOUT
Mode input voltage of the op amp below VDD, which is
within its allowed range. The output of the op amp will
also be below VDD, which is within its Maximum Output
V2
Voltage Swing specification.
½ MCP6402 ½ MCP6402
IDD V1
To load
1.8V
10Ω VDD R 1 2R 1
to
VOUT VOUT = ( V 1 – V 2 ) ⎛ 1 + ------ + ---------⎞ + V REF
6.0V ⎝ R 2 RG ⎠
100 kΩ MCP6401
FIGURE 4-10: Two Op Amp
1 MΩ Instrumentation Amplifier.

V DD – VOUT
I DD = ------------------------------------------
( 10 V/V ) ⋅ ( 10 Ω )

FIGURE 4-9: Supply Current Sensing.

DS22229D-page 20 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
5.0 DESIGN AIDS 5.4 Analog Demonstration and
Evaluation Boards
Microchip provides the basic design tools needed for
the MCP6401/1R/1U/2/4/6/7/9 family of op amps. Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
5.1 SPICE Macro Model designed to help you achieve faster time to market. For
a complete listing of these boards and their
The latest SPICE macro model for the corresponding user’s guides and technical information,
MCP6401/1R/1U/2/4/6/7/9 op amp is available on the visit www.microchip.com/analogtools, the Microchip
Microchip web site at www.microchip.com. The model web site.
was written and tested in official Orcad (Cadence)
owned PSPICE. For other simulators, translation may Some boards that are especially useful are:
be required. • MCP6XXX Amplifier Evaluation Board 1
The model covers a wide aspect of the op amp's • MCP6XXX Amplifier Evaluation Board 2
electrical specifications. Not only does the model cover • MCP6XXX Amplifier Evaluation Board 3
voltage, current, and resistance of the op amp, but it • MCP6XXX Amplifier Evaluation Board 4
also covers the temperature and noise effects on the • Active Filter Demo Board Kit
behavior of the op amp. The model has not been
• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
conditions cannot be guaranteed to match the actual P/N SOIC8EV
op amp performance. • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also, 5.5 Application Notes
simulation results using this macro model need to be The following Microchip Analog Design Note and
validated by comparing them to the data sheet Application Notes are available on the Microchip web
specifications and characteristic curves. site at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
5.2 FilterLab® Software
• ADN003: “Select the Right Operational Amplifier
Microchip’s FilterLab® software is an innovative for your Filtering Circuits”, DS21821
software tool that simplifies analog active filter (using • AN722: “Operational Amplifier Topologies and DC
op amps) design. Available at no cost from the Specifications”, DS00722
Microchip web site at www.microchip.com/filterlab, the • AN723: “Operational Amplifier AC Specifications
FilterLab design tool provides full schematic diagrams and Applications”, DS00723
of the filter circuit with component values. It also
• AN884: “Driving Capacitive Loads With Op
outputs the filter circuit in SPICE format, which can be
Amps”, DS00884
used with the macro model to simulate actual filter
performance. • AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
5.3 Microchip Advanced Part Selector • AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
(MAPS)
• AN1228: “Op Amp Precision Design: Random
MAPS is a software tool that helps semiconductor Noise”, DS01228
professionals efficiently identify Microchip devices that • AN1297: “Microchip’s Op Amp SPICE Macro
fit a particular design requirement. Available at no cost Models”, DS01297
from the Microchip website at • AN1332: “Current Sensing Circuit Concepts and
www.microchip.com/maps, the MAPS is an overall Fundamentals”, DS01332
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this These application notes and others are listed in the
tool, you can define a filter to sort features for a design guide:
parametric search of devices and export side-by-side • “Signal Chain Design Guide”, DS21825
technical comparison reports. Helpful links are also
provided for Datasheets, Purchase, and Sampling of
Microchip parts.

© 2009-2011 Microchip Technology Inc. DS22229D-page 21

MCP6401/1R/1U/2/4/6/7/9
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

5-Lead SC70 (MCP6401 only) Example:

BL25

5-Lead SOT-23 Part Number Code

(MCP6401/1R/1U, MCP6406) Example:
MCP6401T-E/OT NLNN
MCP6401T-H/OT U8NN
MCP6401RT-E/OT NMNN
MCP6401RT-H/OT U9NN NL25
MCP6401UT-E/OT NPNN
MCP6401UT-H/OT V8NN
MCP6406T-E/OT ZXNN
MCP6406T-H/OT ZYNN

8-Lead TDFN (2 x 3) (MCP6402 only) Example:

AAW
Part Number Code
129
MCP6402T-E/MNY AAW 25

8-Lead SOIC (150 mil) (MCP6401, MCP6402, MCP6407) Example:

MCP6402E
SN ^^1129
e3

256
NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS22229D-page 22 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
Package Marking Information (Continued)

14-Lead SOIC (150 mil) (MCP6404, MCP6409) Example:

MCP6404
H/SL e
^^3
1129256

and

14-Lead TSSOP (MCP6404 only) Example:

XXXXXXXX 6404E/ST
1129
YYWW 256
NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2009-2011 Microchip Technology Inc. DS22229D-page 23

MCP6401/1R/1U/2/4/6/7/9

     

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

3 2 1

E1

4 5
e e

A A2 c

A1
L

3# 44" "

  4# 5 56 7
5$8  %1 5 (
1#  9()*
6, : #  ; < 
 !!1/ /  ; < 
#! %%   < 
6, =!# " ;  
 !!1/=!# " ( ( (
6, 4#  ;  (
. #4# 4   9
4! /  ; < 9
4!=!# 8 ( < 
  
    !"!  #$! !%   # $    !%   # $     #&!   !
   !#    "'(
)*+ )     #&#,$ --# $##   

        - *9)

DS22229D-page 24 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

© 2009-2011 Microchip Technology Inc. DS22229D-page 25

MCP6401/1R/1U/2/4/6/7/9

      !

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

b
N

E1

1 2 3
e

e1
D

A A2 c φ

A1 L

L1

3# 44" "

  4# 5 56 7
5$8  %1 5 (
4!1#  ()*
6$# !4!1#  )*
6, : #   < (
 !!1/ /  ; < 
#! %%   < (
6, =!# "  < 
 !!1/=!# "  < ;
6, 4#   < 
. #4# 4  < 9
. # # 4 ( < ;
. #  > < >
4! /  ; < 9
4!=!# 8  < (
  
    !"!  #$! !%   # $    !%   # $     #&!   !
   !#    "'(
)*+ )     #&#,$ --# $##   
        - *)

DS22229D-page 26 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 27

MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22229D-page 28 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 29

MCP6401/1R/1U/2/4/6/7/9

"    #$%!&'()*

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

DS22229D-page 30 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 31

MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22229D-page 32 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

"  + ,  % -./# 0!0&()+,

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

© 2009-2011 Microchip Technology Inc. DS22229D-page 33

MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22229D-page 34 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 35

MCP6401/1R/1U/2/4/6/7/9

  . #  #$ # /! - 0   #    1/ %#  #!#
## +22---    2 /

DS22229D-page 36 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 37

MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22229D-page 38 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

© 2009-2011 Microchip Technology Inc. DS22229D-page 39

MCP6401/1R/1U/2/4/6/7/9
APPENDIX A: REVISION HISTORY Revision B (June 2010)
The following is the list of modifications:
Revision D (September 2011) 1. Added the MCP6402 and MCP6404 package
The following is the list of modifications: information.
1. Section 1.0 “Electrical Characteristics”: 2. Updated the ESD protection value on all pins in
Updated minor typographical corrections in Section 1.1 “Absolute Maximum Ratings †”.
both “DC Electrical Specifications” tables to 3. Added Figure 2-36.
show the correct unit for RL (kΩ instead of kW). 4. Updated Table 3-1.
5. Updated Section 4.1.2 “Input Voltage Limits”.
Revision C (August 2011) 6. Added Section 4.1.3 “Input Current Limits”.
The following is the list of modifications: 7. Added Section 4.5 “Unused Op Amps”.
8. Updated Section 5.4 “Analog Demonstration
1. Added new MCP6406, MCP6407 and
and Evaluation Boards”.
MCP6409 devices and the related information
throughout the document. 9. Updated the package markings information and
drawings.
2. Created two package type drawings based on
the temperature characterization (see E Temp 10. Updated the Product Identification System
Package Types and H Temp Package Types). page.
3. Added MCP6406/7/9 specification tables in
Section 1.3 “MCP6406/7/9 Electrical Specifi- Revision A (December 2009)
cations”. Original data sheet for the MCP6401/1R/1U/2/4/6/7/9
4. Updated characterization graphics in family of devices.
Section 2.0 “Typical Performance Curves”.
5. Updated Table 3-1 in Section 3.0 “Pin
Descriptions” to show all the devices.
6. Updated markings examples in Section 6.1
“Package Marking Information”.
7. Updated the package markings information to
show all drawings available for each type of
package.
8. Updated the Product Identification System
page with the new devices and temperature
specifications.

DS22229D-page 40 © 2009-2011 Microchip Technology Inc.

 MCP6401/1R/1U/2/4/6/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. -X /XX Examples:

a) MCP6401T-E/LT: Tape and Reel,
Device Temperature Package Extended Temperature,
Range 5LD SC70 pkg
b) MCP6401T-E/OT: Tape and Reel,
Extended Temperature,
Device: MCP6401T: Single Op Amp (Tape and Reel) 5LD SOT-23 pkg
(SC70, SOT-23) c) MCP6401RT-E/OT: Tape and Reel,
MCP6401RT: Single Op Amp (Tape and Reel) 5LD SOT-23 pkg
(SOT-23) d) MCP6401UT-E/OT: Tape and Reel,
MCP6401UT: Single Op Amp (Tape and Reel) Extended Temperature,
(SOT-23) 5LD SOT-23 pkg
MCP6402: Dual Op Amp
MCP6402T: Dual Op Amp (Tape and Reel) e) MCP6402-E/SN: Extended Temperature,
(SOIC, 2x3 TDFN) 8LD SOIC pkg
MCP6404: Quad Op Amp f) MCP6402T-E/SN: Tape and Reel,
MCP6404T: Quad Op Amp (Tape and Reel) Extended Temperature,
(SOIC, TSSOP) 8LD SOIC pkg
MCP6406T: Single Op Amp (Tape and Reel) g) MCP6402T-E/MNY: Tape and Reel,
(SOT-23) Extended Temperature,
MCP6407: Dual Op Amp 8LD 2x3 TDFN pkg
MCP6407T: Dual Op Amp (Tape and Reel)
(SOIC) h) MCP6404-E/SL: Extended Temperature,
MCP6409: Quad Op Amp 14LD SOIC pkg
MCP6409T: Quad Op Amp (Tape and Reel) i) MCP6404T-E/SL: Tape and Reel,
(SOIC) Extended Temperature,
14LD SOIC pkg
j) MCP6404-E/ST: Extended Temperature,
Temperature Range: E = -40°C to +125°C (Extended Temperature) 14LD TSSOP pkg
H = -40°C to +150°C (High Temperature) k) MCP6404T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP pkg.
Package: LT = Plastic Package (SC70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead a) MCP6401T-H/OT: Tape and Reel,
SN = Plastic SOIC, (3.90 mm body), 8-lead High Temperature,
MNY* = Plastic Dual Flat, No Lead, (2x3 TDFN), 8-lead 5LD SOT-23 pkg
SL = Plastic SOIC (3.90 mm body), 14-lead
ST = Plastic TSSOP (4.4mm body), 14-lead b) MCP6402-H/SN: High Temperature,
8LD SOIC pkg
* Y = Nickel palladium gold manufacturing designator. c) MCP6402T-H/SN: Tape and Reel,
Only available on the TDFN package. High Temperature,
8LD SOIC pkg
d) MCP6404-H/SL: High Temperature,
14LD SOIC pkg
e) MCP6404T-H/SL: Tape and Reel,
High Temperature,
14LD SOIC pkg
f) MCP6406T-H/OT: Tape and Reel,
High Temperature,
5LD SOT-23 pkg
g) MCP6407-H/SN: High Temperature,
8LD SOIC pkg
h) MCP6407T-H/SN: Tape and Reel,
High Temperature,
8LD SOIC pkg
i) MCP6409-H/SL: High Temperature,
14LD SOIC pkg
j) MCP6409T-H/SL: Tape and Reel,
High Temperature,
14LD SOIC pkg

© 2009-2011 Microchip Technology Inc. DS22229D-page 41

MCP6401/1R/1U/2/4/6/7/9
NOTES:

DS22229D-page 42 © 2009-2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-61341-616-7

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2009-2011 Microchip Technology Inc. DS22229D-page 43

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
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Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
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Tel: 248-538-2250
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Tel: 86-21-5407-5533 Tel: 886-3-5778-366
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Tel: 317-773-8323 China - Shenyang Taiwan - Kaohsiung
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Fax: 86-24-2334-2393 Fax: 886-7-330-9305
Los Angeles
Mission Viejo, CA China - Shenzhen Taiwan - Taipei
Tel: 949-462-9523 Tel: 86-755-8203-2660 Tel: 886-2-2500-6610
Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-2-2508-0102

Santa Clara China - Wuhan Thailand - Bangkok

Santa Clara, CA Tel: 86-27-5980-5300 Tel: 66-2-694-1351
Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 66-2-694-1350
Fax: 408-961-6445 China - Xian
Toronto Tel: 86-29-8833-7252
Mississauga, Ontario, Fax: 86-29-8833-7256
Canada China - Xiamen
Tel: 905-673-0699 Tel: 86-592-2388138
Fax: 905-673-6509 Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
08/02/11
Fax: 86-756-3210049

DS22229D-page 44 © 2009-2011 Microchip Technology Inc.