MCP6001/1R/1U/2/4

1 MHz, Low-Power Op Amp

Features Description
• Available in SC-70-5 and SOT-23-5 packages The Microchip Technology Inc. MCP6001/2/4 family of
• Gain Bandwidth Product: 1 MHz (typical) operational amplifiers (op amps) is specifically
• Rail-to-Rail Input/Output designed for general-purpose applications. This family
has a 1 MHz Gain Bandwidth Product (GBWP) and 90°
• Supply Voltage: 1.8V to 6.0V
phase margin (typical). It also maintains 45° phase
• Supply Current: IQ = 100 µA (typical) margin (typical) with a 500 pF capacitive load. This
• Phase Margin: 90° (typical) family operates from a single supply voltage as low as
• Temperature Range: 1.8V, while drawing 100 µA (typical) quiescent current.
- Industrial: -40°C to +85°C Additionally, the MCP6001/2/4 supports rail-to-rail input
and output swing, with a Common-mode input voltage
- Extended: -40°C to +125°C
range of VDD + 300 mV to VSS – 300 mV. This family of
• Available in Single, Dual and Quad Packages op amps is designed with Microchip’s advanced CMOS
process.
Applications
The MCP6001/2/4 family is available in the industrial
• Automotive and extended temperature ranges, with a power supply
• Portable Equipment range of 1.8V to 6.0V.
• Photodiode Amplifier
• Analog Filters
Package Types
• Notebooks and PDAs MCP6001 MCP6001R
• Battery-Powered Systems SC70-5, SOT-23-5 SOT-23-5
VOUT 1 5 VDD VOUT 1 5 VSS
Design Aids VSS 2 VDD 2
+ – + –
• SPICE Macro Models VIN+ 3 4 VIN– VIN+ 3 4 VIN–
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator MCP6002 MCP6001U
• Microchip Advanced Part Selector (MAPS) PDIP, SOIC, MSOP SOT-23-5
• Analog Demonstration and Evaluation Boards VOUTA 1 8 VDD VIN+ 1 5 VDD
• Application Notes VINA– 2 –+ 7 VOUTB VSS 2 +
–
VINA+ 3 + - 6 VINB– VIN– 3 4 VOUT
Typical Application VSS 4 5 VINB+

VDD
MCP6002 MCP6004
VIN + 2x3 DFN * PDIP, SOIC, TSSOP
MCP6001 VOUT VOUTA 1 8 VDD VOUTA 1 14 VOUTD
– VINA– 2
V –
7 VOUTB INA 2 – + + – 13 VIND–
EP
VSS VINA+ 3
9 V +
6 VINB– INA 3 12 VIND+

VSS 4 5 V + VDD 4
INB
11 VSS

VINB+ 5 10 VINC+
R1
R2 VINB– 6 – + +– 9 VINC–
R1 VOUTB 7 8 VOUTC
Gain = 1 + ------
R2
VREF
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Non-Inverting Amplifier

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NOTES:

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 MCP6001/1R/1U/2/4
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
CHARACTERISTICS device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings † indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
VDD – VSS ........................................................................7.0V periods may affect device reliability.
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”.
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ................................... –65°C to +150°C
Maximum Junction Temperature (TJ)......................... .+150°C
ESD Protection On All Pins (HBM; MM)   4 kV; 200V

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VL = VDD/2,
RL = 10 kto VL, and VOUT  VDD/2 (refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -4.5 — +4.5 mV VCM = VSS (Note 1)
Input Offset Drift with Temperature VOS/TA — ±2.0 — µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection Ratio PSRR — 86 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current: IB — ±1.0 — pA
Industrial Temperature IB — 19 — pA TA = +85°C
Extended Temperature IB — 1100 — pA TA = +125°C
Input Offset Current IOS — ±1.0 — pA
Common-mode Input Impedance ZCM — 1013||6 — ||pF
Differential Input Impedance ZDIFF — 1013||3 — ||pF
Common-mode
Common-mode Input Range VCMR VSS 0.3 — VDD + 0.3 V
Common-mode Rejection Ratio CMRR 60 76 — dB VCM = -0.3V to 5.3V,
VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 88 112 — dB VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD – 25 mV VDD = 5.5V,
0.5V Input Overdrive
Output Short Circuit Current ISC — ±6 — mA VDD = 1.8V
— ±23 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 6.0 V Note 2
Quiescent Current per Amplifier IQ 50 100 170 µA IO = 0, VDD = 5.5V, VCM = 5V
Note 1: MCP6001/1R/1U/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV
minimum/maximum limits.
2: All parts with date codes November 2007 and later have been screened to ensure operation at
VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V.

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MCP6001/1R/1U/2/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VL = VDD/2, VOUT  VDD/2, RL = 10 k to VL, and CL = 60 pF (refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 1.0 — MHz
Phase Margin PM — 90 — ° G = +1 V/V
Slew Rate SR — 0.6 — V/µs
Noise
Input Noise Voltage Eni — 6.1 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 28 — nV/Hz f = 1 kHz
Input Noise Current Density ini — 0.6 — fA/Hz f = 1 kHz

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA -40 — +85 °C
Extended Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C Note
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 JA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W
Thermal Resistance, 8L-PDIP JA — 85 — °C/W
Thermal Resistance, 8L-SOIC (150 mil) JA — 163 — °C/W
Thermal Resistance, 8L-MSOP JA — 206 — °C/W
Thermal Resistance, 8L-DFN (2x3) JA — 68 — °C/W
Thermal Resistance, 14L-PDIP JA — 70 — °C/W
Thermal Resistance, 14L-SOIC JA — 120 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note: The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.

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 MCP6001/1R/1U/2/4
1.1 Test Circuits
CF
The circuit used for most DC and AC tests is shown in
6.8 pF
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common-mode voltage ((VP + VM)/2), and that RG RF
VOST includes VOS plus the effects (on the input offset 100 k 100 k
error, VOST) of temperature, CMRR, PSRR and AOL. VP VDD/2
VDD
VIN+
EQUATION 1-1:
+ CB1 CB2
G DM = R F  R G MCP600X 100 nF 1 µF
–
V CM =  V P + V DD  2   2
V OST = V IN– – V IN+ VIN–
V OUT =  V DD  2  +  V P – V M  + V OST  1 + G DM  VM VOUT
RG RF RL CL
Where:
100 k 100 k 10 k 60 pF
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common-mode (V) CF
Input Voltage 6.8 pF VL
VOST = Op Amp’s Total Input Offset (mV)
Voltage FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.

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NOTES:

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 MCP6001/1R/1U/2/4
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.

20% 0
64,695 Samples VDD = 1.8V
Percentage of Occurrences

18% VCM = VSS

Input Offset Voltage (µV)

-100
16%
14% -200
12% -300
10%
-400 TA = -40°C
8%
TA = +25°C
6% -500 TA = +85°C
4% TA = +125°C
-600
2%
0% -700

-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
5 -4 -3 -2 -1 0 1 2 3 4 5
Input Offset Voltage (mV) Common Mode Input Voltage (V)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 1.8V.

18% 0
Percentage of Occurrences

2453 Samples VDD = 5.5V

16% TA = -40°C to +125°C
Input Offset Voltage (µV)

-100
14% VCM = VSS
12% -200
10% -300
8%
6% -400
TA = -40°C
4% -500 TA = +25°C
TA = +85°C
2%
-600 TA = +125°C
0%
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -700
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Offset Voltage Drift;
TC1 (µV/°C) Common Mode Input Voltage (V)

FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.

45%
Percentage of Occurrences

2453 Samples 200

40% TA = -40°C to +125°C
150
Input Offset Voltage (µV)

35% VCM = VSS

30% 100
25% 50 VDD = 5.5V
20%
15% 0
VDD = 1.8V
10% -50
5%
-100
0%
-150
-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

VCM = VSS
-200
Input Offset Quadratic Temp. Co.;
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TC2 (µV/°C2) Output Voltage (V)

FIGURE 2-3: Input Offset Quadratic FIGURE 2-6: Input Offset Voltage vs.
Temp. Co. Output Voltage.

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MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.

14% 100
1230 Samples VCM = VSS
Percentage of Occurrences

12% VDD = 5.5V 90

VCM = VDD
80

PSRR, CMRR (dB)

10% TA = +85°C
70
8% PSRR–
60
6% PSRR+
50
CMRR
4%
40
2%
30
0% 20
0 3 6 9 12 15 18 21 24 27 30 10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05
Input Bias Current (pA) Frequency (Hz)

FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-10: PSRR, CMRR vs.
Frequency.

55% 120 0
605 Samples
Percentage of Occurrences

50%
VDD = 5.5V
45% 100 -30

Open-Loop Gain (dB)

VCM = VDD

Open-Loop Phase (°)

40% TA = +125°C 80 -60
35% Phase
30% 60 -90
25%
20% 40 -120
Gain
15%
20 -150
10%
5% 0 -180
0% VCM = VSS
-20 -210
0

150

300

450

600

750

900

1050

1200

1350

1500

0.1 1.E+
1.E- 1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k 1M 10M
1.E+ 1.E+ 1.E+
Input Bias Current (pA) 01 00 01 Frequency
02 03 04 (Hz) 05 06 07

FIGURE 2-8: Input Bias Current at FIGURE 2-11: Open-Loop Gain, Phase vs.
+125°C. Frequency.

100 1,000
VDD = 5.0V
Input Noise Voltage Density

95
PSRR, CMRR (dB)

90
(nV/Hz)

PSRR (VCM = VSS)

85 100

80
CMRR (VCM = -0.3V to +5.3V)
75

70 10
-50 -25 0 25 50 75 100 125 0.1
1.E-01 1
1.E+0 10
1.E+0 100 1.E+0
1.E+0 1k 10k 1.E+0
1.E+0 100k
Ambient Temperature (°C) 0 1Frequency
2 (Hz)3 4 5

FIGURE 2-9: CMRR, PSRR vs. Ambient FIGURE 2-12: Input Noise Voltage Density
Temperature. vs. Frequency.

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 MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.

30 0.08

G = +1 V/V

Output Voltage (20 mV/div)

25
0.06
Short Circuit Current

TA = -40°C
Magnitude (mA)

TA = +25°C
0.04

20 TA = +85°C 0.02

TA = +125°C
15 0.00

10 -0.02

5
-0.04

-0.06

0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.08
0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05

Power Supply Voltage (V) Time (1 µs/div)

FIGURE 2-13: Output Short Circuit Current FIGURE 2-16: Small-Signal, Non-Inverting
vs. Power Supply Voltage. Pulse Response.

1,000 5.0 G = +1 V/V

4.5
Output Voltage Headroom

VDD = 5.0V

4.0

Output Voltage (V)

VDD – VOH
100 3.5
VOL – VSS 3.0
(mV)

2.5
10 2.0
1.5
1.0
1 0.5
10µ
1.E-05 100µ
1.E-04 1m
1.E-03 10m
1.E-02 0.0 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04

Output Current Magnitude (A) Time (10 µs/div)

FIGURE 2-14: Output Voltage Headroom FIGURE 2-17: Large-Signal, Non-Inverting

vs. Output Current Magnitude. Pulse Response.

180 1.0
VCM = VDD - 0.5V
160 0.9 VDD = 5.5V
140 0.8
Quiescent Current
per amplifier (µA)

Slew Rate (V/µs)

Falling Edge
120 0.7
0.6
100
0.5
80 0.4
TA = +125°C VDD = 1.8V
60 0.3
TA = +85°C Rising Edge
40 TA = +25°C 0.2
20 TA = -40°C 0.1
0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Power Supply Voltage (V)

FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Slew Rate vs. Ambient
Power Supply Voltage. Temperature.

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MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.

10 6
VIN VDD = 5.0V
P-P )

G = +2 V/V
5

Input, Output Voltages (V)

VDD = 5.5V
Output Voltage Swing (V

VOUT
4
VDD = 1.8V
3
1
2

0
0.1
1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 -1 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04

Frequency (Hz) Time (10 µs/div)

FIGURE 2-19: Output Voltage Swing vs. FIGURE 2-21: The MCP6001/2/4 Show No
Frequency. Phase Reversal.

1.E-02
10m
Input Current Magnitude (A)

1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09 +125°C
+85°C
100p
1.E-10 +25°C
10p
1.E-11 -40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)

FIGURE 2-20: Measured Input Current vs.

Input Voltage (below VSS).

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 MCP6001/1R/1U/2/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6001 MCP6001R MCP6001U MCP6002 MCP6004
MSOP, PDIP, Symbol Description
SC70-5, DFN
SOT-23-5 SOT-23-5 PDIP, SOIC,
SOT-23-5 2x3
SOIC TSSOP
1 1 4 1 1 1 VOUT, VOUTA Analog Output (op amp A)
4 4 3 2 2 2 VIN–, VINA– Inverting Input (op amp A)
3 3 1 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A)
5 2 5 8 8 4 VDD Positive Power Supply
— — — 5 5 5 VINB+ Non-inverting Input (op amp B)
— — — 6 6 6 VINB– Inverting Input (op amp B)
— — — 7 7 7 VOUTB Analog Output (op amp B)
— — — — — 8 VOUTC Analog Output (op amp C)
— — — — — 9 VINC– Inverting Input (op amp C)
— — — — — 10 VINC+ Non-inverting Input (op amp C)
2 5 2 4 4 11 VSS Negative Power Supply
— — — — — 12 VIND+ Non-inverting Input (op amp D)
— — — — — 13 VIND– Inverting Input (op amp D)
— — — — — 14 VOUTD Analog Output (op amp D)
— — — — 9 — EP Exposed Thermal Pad (EP);
must be connected to VSS.

3.1 Analog Outputs 3.4 Exposed Thermal Pad (EP)

The output pins are low-impedance voltage sources. There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
3.2 Analog Inputs be connected to the same potential on the Printed
Circuit Board (PCB).
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.

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 MCP6001/1R/1U/2/4
4.0 APPLICATION INFORMATION VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
The MCP6001/2/4 family of op amps is manufactured the current through D1 and D2.
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
VDD
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6001/2/4 ideal for battery-powered applications. D1 D2
This device has high phase margin, which makes it
V1
stable for larger capacitive load applications. +
R1 MCP600X
4.1 Rail-to-Rail Inputs V2 –
R2
4.1.1 PHASE REVERSAL
The MCP6001/1R/1U/2/4 op amp is designed to
R3
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-21 shows the input voltage VSS – (minimum expected V1)
R1 >
exceeding the supply voltage without any phase 2 mA
reversal. VSS – (minimum expected V2)
R2 >
2 mA
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS FIGURE 4-2: Protecting the Analog
The ESD protection on the inputs can be depicted as Inputs.
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias It is also possible to connect the diodes to the left of
current (IB). The input ESD diodes clamp the inputs resistors R1 and R2. In this case, current through the
when they try to go more than one diode drop below diodes D1 and D2 needs to be limited by some other
VSS. They also clamp any voltages that go too far mechanism. The resistors then serve as in-rush current
above VDD; their breakdown voltage is high enough to limiters; the DC current into the input pins (VIN+ and
allow normal operation, and low enough to bypass VIN–) should be very small.
quick ESD events within the specified limits. A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-20. Applications that are
VDD Bond high impedance may need to limit the usable voltage
Pad range.

4.1.3 NORMAL OPERATION

The input stage of the MCP6001/1R/1U/2/4 op amps
VIN+ Bond Input Bond V –
IN
Pad Stage Pad use two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other operates at high VCM. WIth this
topology, the device operates with VCM up to 0.3V
VSS Bond above VDD and 0.3V below VSS.
Pad
The transition between the two input stages occurs
FIGURE 4-1: Simplified Analog Input ESD when VCM = VDD – 1.1V. For the best distortion and
Structures. gain linearity, with non-inverting gains, avoid this region
of operation.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see 4.2 Rail-to-Rail Output
Absolute Maximum Ratings † at the beginning of The output voltage range of the MCP6001/2/4 op amps
Section 1.0 “Electrical Characteristics”). Figure 4-2 is VDD – 25 mV (minimum) and VSS + 25 mV
shows the recommended approach to protecting these (maximum) when RL = 10 k is connected to VDD/2
inputs. The internal ESD diodes prevent the input pins and VDD = 5.5V. Refer to Figure 2-14 for more
(VIN+ and VIN–) from going too far below ground, and information.
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above

 2019 Microchip Technology Inc. DS20001733K-page 13

MCP6001/1R/1U/2/4
4.3 Capacitive Loads 4.4 Supply Bypass
Driving large capacitive loads can cause stability With this family of operational amplifiers, the power
problems for voltage feedback op amps. As the load supply pin (VDD for single-supply) should have a local
capacitance increases, the feedback loop’s phase bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
margin decreases and the closed-loop bandwidth is for good high-frequency performance. It also needs a
reduced. This produces gain peaking in the frequency bulk capacitor (i.e., 1 µF or larger) within 100 mm to
response, with overshoot and ringing in the step provide large, slow currents. This bulk capacitor can be
response. While a unity-gain buffer (G = +1) is the most shared with nearby analog parts.
sensitive to capacitive loads, all gains show the same
general behavior. 4.5 Unused Op Amps
When driving large capacitive loads with these op
An unused op amp in a quad package (MCP6004)
amps (e.g., > 100 pF when G = +1), a small series
should be configured as shown in Figure 4-5. These
resistor at the output (RISO in Figure 4-3) improves the
circuits prevent the output from toggling and causing
feedback loop’s phase margin (stability) by making the
crosstalk. Circuits A sets the op amp at its minimum
output load resistive at higher frequencies. The
noise gain. The resistor divider produces any desired
bandwidth will be generally lower than the bandwidth
reference voltage within the output voltage range of the
with no capacitance load.
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
– current.
RISO
MCP600X VOUT
VIN ¼ MCP6004 (A) ¼ MCP6004 (B)
+ CL
VDD VDD

R1 VDD
FIGURE 4-3: Output resistor, RISO +
stabilizes large capacitive loads. +
VREF –
Figure 4-4 gives recommended RISO values for R2 –
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the R2
Signal Gain are equal. For inverting gains, GN is V REF = V DD  ------------------
R1 + R2
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5: Unused Op Amps.
1000
VDD = 5.0V
RL = 100 k
4.6 PCB Surface Leakage
Recommended RISO (Ω)

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects
100 GN = 1
need to be considered. Surface leakage is caused by
GN  2 humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow; which is greater than the
10
10p 100p 1n 10n MCP6001/1R/1U/2/4 family’s bias current at 25°C (typ-
1.E-11 1.E-10 1.E-09 1.E-08
Normalized Load Capacitance; CL/GN (F) ically 1 pA).
The easiest way to reduce surface leakage is to use a
FIGURE 4-4: Recommended RISO values
guard ring around sensitive pins (or traces). The guard
for Capacitive Loads. ring is biased at the same voltage as the sensitive pin.
After selecting RISO for your circuit, double-check the An example of this type of layout is shown in
resulting frequency response peaking and step Figure 4-6.
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6001/1R/1U/2/4 SPICE
macro model are very helpful.

DS20001733K-page 14  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
VIN- VIN+
VSS –
1/2 R2 R1
MCP6002
VIN1 +
–
MCP6001 VOUT
+
– R2
1/2
MCP6002
Guard Ring VIN2
+ R1 = 20 k
FIGURE 4-6: Example Guard Ring Layout R1
R2 = 10 k
for Inverting Gain.
VREF
1. Non-inverting Gain and Unity-Gain Buffer:
R1
a.Connect the non-inverting pin (VIN+) to the V OUT =  V IN2 – V IN1   ------ + V REF
R2
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input FIGURE 4-7: Instrumentation Amplifier
pin (VIN–). This biases the guard ring to the with Unity-Gain Buffer Inputs.
Common-mode input voltage.
4.7.2 ACTIVE LOW-PASS FILTER
2. Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as The MCP6001/2/4 op amp’s low input bias current
photo detectors): makes it possible for the designer to use larger
a.Connect the guard ring to the non-inverting resistors and smaller capacitors for active low-pass
input pin (VIN+). This biases the guard ring filter applications. However, as the resistance
to the same reference voltage as the op increases, the noise generated also increases.
amp (e.g., VDD/2 or ground). Parasitic capacitances and the large value resistors
could also modify the frequency response. These
b.Connect the inverting pin (VIN–) to the input
trade-offs need to be considered when selecting circuit
with a wire that does not touch the PCB
elements.
surface.
Usually, the op amp bandwidth is 100x the filter cutoff
4.7 Application Circuits frequency (or higher) for good performance. It is
possible to have the op amp bandwidth 10X higher
4.7.1 UNITY-GAIN BUFFER than the cutoff frequency, thus having a design that is
more sensitive to component tolerances.
The rail-to-rail input and output capability of the
Figure 4-8 shows a second-order Butterworth filter with
MCP6001/2/4 op amp is ideal for unity-gain buffer
100 kHz cutoff frequency and a gain of +1 V/V; the op
applications. The low quiescent current and wide
amp bandwidth is only 10x higher than the cutoff
bandwidth makes the device suitable for a buffer
frequency. The component values were selected using
configuration in an instrumentation amplifier circuit, as
Microchip’s FilterLab® software.
shown in Figure 4-7.

100 pF

VIN 14.3 k 53.6 k

+
MCP6002
33 pF – VOUT

FIGURE 4-8: Active Second-Order

Low-Pass Filter.

 2019 Microchip Technology Inc. DS20001733K-page 15

MCP6001/1R/1U/2/4
4.7.3 PEAK DETECTOR EQUATION 4-1:
The MCP6001/2/4 op amp has a high input impedance, dV C1
I SC = C 1 -------------
rail-to-rail input/output and low input bias current, which dt
makes this device suitable for peak detector dV C1 I SC
applications. Figure 4-9 shows a peak detector circuit ------------- = --------
dt C1
with clear and sample switches. The peak-detection
cycle uses a clock (CLK), as shown in Figure 4-9. 25mA
= ---------------
0.1F
At the rising edge of CLK, Sample Switch closes to dV C1
begin sampling. The peak voltage stored on C1 is ------------- = 250mV  s
sampled to C2 for a sample time defined by tSAMP. At dt
the end of the sample time (falling edge of Sample
This voltage rate of change is less than the MCP6001/2/4
Signal), Clear Signal goes high and closes the Clear
slew rate of 0.6 V/µs. When the input voltage swings
Switch. When the Clear Switch closes, C1 discharges
below the voltage across C1, D1 becomes
through R1 for a time defined by tCLEAR. At the end of
reverse-biased. This opens the feedback loop and rails
the clear time (falling edge of Clear Signal), op amp A
the amplifier. When the input voltage increases, the
begins to store the peak value of VIN on C1 for a time
amplifier recovers at its slew rate. Based on the rate of
defined by tDETECT.
voltage change shown in the above equation, it takes an
In order to define tSAMP and tCLEAR, it is necessary to extended period of time to charge a 0.1 µF capacitor. The
determine the capacitor charging and discharging capacitors need to be selected so that the circuit is not
period. The capacitor charging time is limited by the limited by the amplifier slew rate. Therefore, the
amplifier source current, while the discharging time () capacitors should be less than 40 µF and a stabilizing
is defined using R1 ( = R1C1). tDETECT is the time that resistor (RISO) needs to be properly selected. (Refer to
the input signal is sampled on C1 and is dependent on Section 4.3 “Capacitive Loads”).
the input voltage change frequency.
The op amp output current limit, and the size of the
storage capacitors (both C1 and C2), could create
slewing limitations as the input voltage (VIN) increases.
Current through a capacitor is dependent on the size of
the capacitor and the rate of voltage change. From this
relationship, the rate of voltage change or the slew rate
can be determined. For example, with an op amp short
circuit current of ISC = 25 mA and a load capacitor of
C1 = 0.1 µF, then:

VIN
+ D1 RISO VC1
1/2
MCP6002 + 1/2 RISO VC2
MCP6002 + VOUT
– C1
Op Amp A R1 MCP6001
–
C2
Op Amp B –
Op Amp C

Sample
Switch
Clear
Switch tSAMP

Sample Signal
tCLEAR

Clear Signal
tDETECT

CLK

FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches.

DS20001733K-page 16  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
5.0 DESIGN AIDS 5.4 Microchip Advanced Part Selector
(MAPS)
Microchip provides the basic design tools needed for
the MCP6001/1R/1U/2/4 family of op amps. MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
5.1 SPICE Macro Model fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
The latest SPICE macro model for the maps, the MAPS is an overall selection tool for
MCP6001/1R/1U/2/4 op amps is available on the Microchip’s product portfolio that includes Analog,
Microchip web site at www.microchip.com. The model Memory, MCUs and DSCs. Using this tool you can
was written and tested in official Orcad (Cadence) define a filter to sort features for a parametric search of
owned PSPICE. For the other simulators, it may devices and export side-by-side technical comparison
require translation. reports. Helpful links are also provided for Data sheets,
The model covers a wide aspect of the op amp's Purchase, and Sampling of Microchip parts.
electrical specifications. Not only does the model cover
voltage, current, and resistance of the op amp, but it 5.5 Analog Demonstration and
also covers the temperature and noise effects on the Evaluation Boards
behavior of the op amp. The model has not been
verified outside of the specification range listed in the Microchip offers a broad spectrum of Analog
op amp data sheet. The model behaviors under these Demonstration and Evaluation Boards that are
conditions can not be guaranteed that it will match the designed to help you achieve faster time to market. For
actual op amp performance. a complete listing of these boards and their
corresponding user’s guides and technical information,
Moreover, the model is intended to be an initial design
visit the Microchip web site at www.micro-
tool. Bench testing is a very important part of any
chip.com/analogtools.
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be Some boards that are especially useful are:
validated by comparing them to the data sheet • MCP6XXX Amplifier Evaluation Board 1
specifications and characteristic curves.
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
5.2 FilterLab® Software
• MCP6XXX Amplifier Evaluation Board 4
Microchip’s FilterLab® software is an innovative • Active Filter Demo Board Kit
software tool that simplifies analog active filter (using • 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
op amps) design. Available at no cost from the
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
Microchip web site at www.microchip.com/filterlab, the
P/N SOIC8EV
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also • 14-Pin SOIC/TSSOP/DIP Evaluation Board,
outputs the filter circuit in SPICE format, which can be P/N SOIC14EV
used with the macro model to simulate actual filter
performance.

5.3 Mindi™ Circuit Designer &

Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.

 2019 Microchip Technology Inc. DS20001733K-page 17

MCP6001/1R/1U/2/4
5.6 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip. com/appnotes and are
recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits,” DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications,” DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications,” DS00723
• AN884: “Driving Capacitive Loads With Op
Amps,” DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview,” DS00990
• AN1177: “Op Amp Precision Design: DC Errors,”
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise,” DS01228
• AN1297: "Microchip 's Op Amp SPICE Macro
Models"
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide,” DS21825

DS20001733K-page 18  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
5-Lead SC-70 (MCP6001) Example: (I-Temp)

XXN (Front) I-Temp E-Temp AA7 (Front)

Device
YWW (Back) Code Code 432 (Back)
MCP6001 AAN CDN
Note: Applies to 5-Lead SC-70.

OR OR

I-Temp E-Temp
Device
XXNN Code Code AA74
MCP6001 AANN CDNN
Note: Applies to 5-Lead SC-70.

5-Lead SOT-23 (MCP6001/1R/1U) Example: (E-Temp)

5 4 I-Temp E-Temp 5 4
Device
Code Code

XXNN MCP6001 AANN CDNN CD25

MCP6001R ADNN CENN
1 2 3 MCP6001U AFNN CFNN 1 2 3
Note: Applies to 5-Lead SOT-23.

8-Lead PDIP (300 mil) Example:

XXXXXXXX MCP6002 MCP6002

XXXXXNNN I/P256 OR I/P^^256
e3

YYWW 0432 0746

8-Lead DFN (2 x 3) Example:

XXX ABY
YWW 944
NN 25

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2019 Microchip Technology Inc. DS20001733K-page 19

MCP6001/1R/1U/2/4
Package Marking Information (Continued)
8-Lead SOIC (150 mil) Example:

XXXXXXXX MCP6002I MCP6002I

XXXXYYWW SN0432 OR SN^^0746
e3

NNN 256 256

8-Lead MSOP Example:

6002I
432256

14-Lead PDIP (300 mil) (MCP6004) Example:

XXXXXXXXXXXXXX MCP6004
XXXXXXXXXXXXXX I/P^^
e3
YYWWNNN 0432256

OR

MCP6004
E/P^^
e3
0746256

14-Lead SOIC (150 mil) (MCP6004) Example:

XXXXXXXXXX MCP6004ISL MCP6004

XXXXXXXXXX OR e3
E/SL^^
YYWWNNN 0432256 0746256

14-Lead TSSOP (MCP6004) Example:

XXXXXX 6004ST 6004STE

YYWW 0432 OR 0432
NNN 256 256

DS20001733K-page 20  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
e
e B

3 1

E1 E
2X
0.15 C
4 N
NOTE 1 5X TIPS
2X 0.30 C
0.15 C
5X b
0.10 C A B

TOP VIEW

A A2 c
C
SEATING
PLANE
A1 L

SIDE VIEW END VIEW

Microchip Technology Drawing C04-061D Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001733K-page 21

MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.65 BSC
Overall Height A 0.80 - 1.10
Standoff A1 0.00 - 0.10
Molded Package Thickness A2 0.80 - 1.00
Overall Length D 2.00 BSC
Exposed Pad Length D2 2.50 2.60 2.70
Overall Width E 2.10 BSC
Exposed Pad Width E1 1.25 BSC
Terminal Width b 0.15 - 0.40
Terminal Length L 0.10 0.20 0.46
Lead Thickness c 0.08 - 0.26

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-061D Sheet 2 of 2

DS20001733K-page 22  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

E
Gx

SILK SCREEN

3 2 1
C G
4 5

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.65 BSC
Contact Pad Spacing C 2.20
Contact Pad Width X 0.45
Contact Pad Length Y 0.95
Distance Between Pads G 1.25
Distance Between Pads Gx 0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2061B

 2019 Microchip Technology Inc. DS20001733K-page 23

MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

0.20 C 2X
D

e1
A D

E/2
E1/2

E1 E
(DATUM D)
(DATUM A-B)

0.15 C D
2X
NOTE 1 1 2

B NX b
0.20 C A-B D

TOP VIEW

A A2
0.20 C

SEATING PLANE
A
SEE SHEET 2 A1 C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2

DS20001733K-page 24  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

T
L
L1

VIEW A-A
SHEET 1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 - 1.30
Standoff A1 - - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 - 0.60
Footprint L1 0.60 REF
Foot Angle I 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001733K-page 25

MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

5 SILK SCREEN

Z C G

1 2

E
GX

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X5) X 0.60
Contact Pad Length (X5) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]

DS20001733K-page 26  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
       !""#$%&
 ' -          $  #     
*...  

D e
b
N N
L

E E2

EXPOSED PAD

NOTE 1
NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW

A3 A1 NOTE 2

/ $0110$%+%,#
! 1 $02 23$ $"4
2  2 5
  6'6(#)
3 7 " 656 686 66
#   " 666 66 66'
) + " 66,%-
3 1 ! 66(#)
3 9  % 66(#)
%   1 ! 6 : ''
%   9  % '6 : ;'
) 9   66 6' 66
) 1 1 66 6 6 6'6
) <<%   = 66 : :
  '
                
           
        
 !     "#$%& '$
(#)* ( ! +        
,%-* ,!          
$ +  !  )6 <)

 2019 Microchip Technology Inc. DS20001733K-page 27

MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001733K-page 28  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
N B

E1

NOTE 1
1 2
TOP VIEW

C A A2

PLANE
L c
A1

e eB
8X b1
8X b
.010 C

SIDE VIEW END VIEW

Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001733K-page 29

MCP6001/1R/1U/2/4

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(NOTE 5)

DATUM A DATUM A

b b
e e
2 2

e e

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.

Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2

DS20001733K-page 30  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A D
NOTE 5
N

E
2
E1
2

E1 E

NOTE 1 1 2

e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C

C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW

h
R0.13
h
R0.13
H 0.23

L
SEE VIEW C
(L1)
VIEW A–A

VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001733K-page 31

MCP6001/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2

DS20001733K-page 32  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

SILK SCREEN

Y1

X1
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev E

 2019 Microchip Technology Inc. DS20001733K-page 33

MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001733K-page 34  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001733K-page 35

MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001733K-page 36  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
()   *+ + " #$% * &
 ' -          $  #     
*...  

NOTE 1
E1

1 2 3

A A2

L c

A1
b1

b e eB

/ 02)7%#
! 1 $02 23$ $"4
2  2 
  66(#)
+#   " : : 6
$    + " ' 6 8'
( #   " 6' : :
# # 9  % 86 6 '
$    9  %  6 '6 56
3 1 ! ;' ;'6 ;;'
+#   1 ' 6 '6
1 +  665 66 6'
/1 9   6 ' 6@6 6;6
11 9   6 65 6
3 ,# > ( : :  6
  '
                
 ># )   
 !  !  %      $       66?  
 !     "#$%& '$
(#)*( ! +        

$ +  !  )6 <66'(

 2019 Microchip Technology Inc. DS20001733K-page 37

MCP6001/1R/1U/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A NOTE 5 D
N

E
2
E2
2

E1 E

2X
0.10 C D
2X N/2 TIPS
NOTE 1 1 2 3 0.20 C
e NX b
B NOTE 5 0.25 C A–B D

TOP VIEW

0.10 C

C A A2
SEATING
PLANE 14X
A1 SIDE VIEW 0.10 C

h h

H R0.13
R0.13

SEE VIEW C
L
VIEW A–A (L1)

VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2

DS20001733K-page 38  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Lead Angle 0° - -
Foot Angle 0° - 8°
Lead Thickness c 0.10 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001733K-page 39

MCP6001/1R/1U/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

14

SILK SCREEN

1 2
X
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X14) X 0.60
Contact Pad Length (X14) Y 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2065-SL Rev D

DS20001733K-page 40  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001733K-page 41

MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001733K-page 42  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001733K-page 43

MCP6001/1R/1U/2/4
NOTES:

DS20001733K-page 44  2019 Microchip Technology Inc.

 MCP6001/1R/1U/2/4
APPENDIX A: REVISION HISTORY Revision G (November 2007)
The following is the list of modifications:
Revision K (November 2019)
1. Updated notes to Section 1.0 “Electrical
The following is the list of modifications: Characteristics”.
1. Updated Section 6.0 “Packaging Informa- 2. Increased Absolute Maximum Voltage range at
tion”. input pins.
3. Increased maximum operating supply voltage
Revision J (November 2009) (VDD).
4. Added test circuits.
The following is the list of modifications:
5. Added Figure 2-3 and Figure 2-20.
1. Added new 2x3 DFN 8-Lead package on 6. Added Section 4.1.1 “Phase Reversal”,
page 1. Section 4.1.2 “Input Voltage and Current
2. Updated the Temperature Specifications table Limits”, Section 4.1.3 “Normal Operation”
with 2x3 DFN thermal resistance information. and Section 4.5 “Unused Op Amps”.
3. Updated Section 1.1 “Test Circuits”. 7. Updated Section 5.0 “Design AIDS”,
4. Updated Figure 2-15. 8. Updated Section 6.0 “Packaging
5. Added the 2x3 DFN column to Table 3-1. Information”
6. Added new Section 3.4 “Exposed Thermal 9. Updated Package Outline Drawings.
Pad (EP)”.
7. Updated Section 5.1 “SPICE Macro Model”. Revision F (March 2005)
8. Updated Section 5.5 “Analog Demonstration
The following is the list of modifications:
and Evaluation Boards”.
9. Updated Section 5.6 “Application Notes”. 1. Updated Section 6.0 “Packaging
Information” to include old and new packaging
10. Updated Section 6.1 “Package Marking
examples.
Information” with the new 2x3 DFN package
marking information.
Revision E (December 2004)
11. Updated the package drawings.
12. Updated the Product Identification System The following is the list of modifications:
section with new 2x3 DFN package information. 1. VOS specification reduced to ±4.5 mV from
±7.0 mV for parts starting with date code
Revision H (May 2008) YYWW = 0449
The following is the list of modifications: 2. Corrected package markings in Section 6.0
“Packaging Information”.
1. Design Aids: Name change for Mindi
3. Added Appendix A: Revision History.
Simulation Tool.
2. Package Types: Correct device labeling error.
Revision D (May 2003)
3. Section 1.0 “Electrical Characteristics”, DC
Electrical Specifications: Changed “Maximum • Undocumented changes.
Output Voltage Swing” condition from 0.9V Input
Overdrive to 0.5V Input Overdrive. Revision C (December 2002)
4. Section 1.0 “Electrical Characteristics”, AC
• Undocumented changes.
Electrical Specifications: Changed Phase
Margin condition from G = +1 to G= +1 V/V.
5. Section 5.0 “Design AIDS”: Name change for
Revision B (October 2002)
Mindi Simulation Tool. • Undocumented changes.

Revision A (June 2002)

• Original data sheet release.

 2019 Microchip Technology Inc. DS20001733K-page 45

 MCP6001/1R/1U/2/4
NOTES:

 2019 Microchip Technology Inc. DS20001733K-page 46

 MCP6001/1R/1U/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX Examples:

a) MCP6001T-I/LT:Tape and Reel,
Device Temperature Package Industrial Temperature,
Range 5LD SC-70 package
b) MCP6001T-I/OT: Tape and Reel,
Industrial Temperature,
Device: MCP6001T: Single Op Amp (Tape and Reel)
5LD SOT-23 package.
(SC-70, SOT-23)
MCP6001RT: Single Op Amp (Tape and Reel) (SOT-23) c) MCP6001RT-I/OT: Tape and Reel,
MCP6001UT: Single Op Amp (Tape and Reel) (SOT-23) Industrial Temperature,
Op Amp
MCP6002: Dual 5LD SOT-23 package.
Op Amp
MCP6002T: Dual (Tape and Reel) d) MCP6001UT-E/OT: Tape and Reel,
(SOIC, MSOP) Extended Temperature,
Op Amp
MCP6004: Quad
MCP6004T: Quad
Op Amp
(Tape and Reel)
5LD SOT-23 package.
(SOIC, MSOP)
a) MCP6002-I/MS:Industrial Temperature, 8LD
MSOP package.
Temperature Range: I = -40°C to +85°C b) MCP6002-I/P:Industrial Temperature, 8LD
E = -40°C to +125°C PDIP package.
c) MCP6002-E/P:Extended Temperature, 8LD
PDIP package.
Package: LT = Plastic Package (SC-70), 5-lead (MCP6001 only)
OT = Plastic Small Outline Transistor (SOT-23), 5-lead d) MCP6002-E/MC:Extended Temperature,
(MCP6001, MCP6001R, MCP6001U) 8LD DFN package.
MS = Plastic MSOP, 8-lead e) MCP6002-I/SN:Industrial Temperature, 8LD
MC = Plastic DFN, 8-lead SOIC package.
P = Plastic DIP (300 mil body), 8-lead, 14-lead
SN = Plastic SOIC, (3.99 mm body), 8-lead f) MCP6002T-I/MS:Tape and Reel,
SL = Plastic SOIC (3.99 body), 14-lead Industrial Temperature,
ST = Plastic TSSOP (4.4mm body), 14-lead 8LD MSOP package.
g) MCP6002T-E/MC:Tape and Reel,
Extended Temperature,
8LD DFN package.

a) MCP6004-I/P:Industrial Temperature, 14LD

PDIP package.
b) MCP6004-I/SL:Industrial Temperature, 14LD
SOIC package.
c) MCP6004-E/SL:Extended Temperature, 14LD
SOIC package.
d) MCP6004-I/ST:Industrial Temperature, 14LD
TSSOP package.
e) MCP6004T-I/SL:Tape and Reel,
Industrial Temperature,
14LD SOIC package.
f) MCP6004T-I/ST:Tape and Reel,
Industrial Temperature,
14LD TSSOP package.

 2019 Microchip Technology Inc. DS20001733K-page 47

MCP6001/1R/1U/2/4
NOTES:

DS20001733K-page 48  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.

© 2019, Microchip Technology Incorporated, All Rights Reserved.

For information regarding Microchip’s Quality Management Systems, ISBN: 978-1-5224-5331-4

please visit www.microchip.com/quality.

 2019 Microchip Technology Inc. DS20001733K-page 49

 Worldwide Sales and Service
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Tel: 905-695-1980
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DS20001733K-page 50  2019 Microchip Technology Inc.

05/14/19
Mouser Electronics

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