MCP6V51

45V, 2 MHz Zero-Drift Op Amp with EMI Filtering

Features General Description
• High DC Precision: The Microchip Technology Inc. MCP6V51 operational
- VOS Drift: 36 nV/°C (max.) amplifier employs dynamic offset correction for very
- VOS: 15 µV (max.) low offset and offset drift. The device has a gain
bandwidth product of 2 MHz (typical). It is unity-gain
- Open-Loop Gain: 140 dB (min.)
stable, has virtually no 1/f noise and excellent Power
- PSRR: 134 dB (min.) Supply Rejection Ratio (PSRR) and Common Mode
- CMRR: 135 dB (min.) Rejection Ratio (CMRR). The product operates with a
• Low Noise: single supply voltage that can range from 4.5V to 45V,
- 10.2 nV/√ Hz at 1 kHz (±2.25V to ±22.5V), while drawing 470 µA (typical) of
quiescent current.
- Eni: 0.21 µVP-P, f = 0.1 Hz to 10 Hz
• Low Power: The MCP6V51 op amp is offered as a single-channel
amplifier and is designed using an advanced CMOS
- IQ: 470 µA/amplifier (typ.)
process.
- Wide Supply Voltage Range: 4.5V to 45V
• Easy to Use: Package Types
- Input Range incl. Negative Rail
- Rail-to-Rail Output
- EMI Filtered Inputs
MCP6V51 MCP6V51
- Gain Bandwidth Product: 2 MHz SOT-23-5 MSOP-8
- Slew Rate 1.2V/µs
VOUT 1 5 VDD NC 1 8 NC
- Unity Gain Stable
VSS 2 VIN– 2 7 VDD
• Small Packages: 5-Lead SOT23, 8-Lead MSOP
VIN+ 3 4 VIN– VIN+ 3 6 VOUT
• Extended Temperature Range: -40°C to +125°C
VSS 4 5 NC

Typical Applications
• Industrial Instrumentation, PLC
• Process Control
• Power Control Loops Typical Application Circuit
• Sensor Conditioning
• Electronic Weight Scales 40VDD
• Medical Instrumentation
• Automotive Monitors Load
• Low-side Current Sensing
U1 40VDD
Design Aids MCP6V51
IL +
• Microchip Advanced Part Selector (MAPS) VOUT
RSHUNT -
• Application Notes
0.05Ω RG
100Ω RF
Related Parts
• MCP6V71/1U/2/4: Zero-Drift, 2 MHz, 1.8V to 5V 20 kΩ
• MCP6V81/1U/2/4: Zero-Drift, 5 MHz, 1.8V to 5V CF 8.2 nF

 2018 Microchip Technology Inc. DS20006136A-page 1

MCP6V51
Figure 1 and Figure 2 show input offset voltage versus As seen in Figure 1 and Figure 2, the MCP6V51 op
ambient temperature for different power supply amps have excellent performance across temperature.
voltages. The input offset voltage temperature drift (TC1) shown
is well within the specified maximum values of
8
22 Samples
31 nV/°C at VDD = 4.5V and 36 nV/°C at VDD = 45V.
6 VDD = 4.5V
This performance supports applications with stringent
Input Offset Voltage (μV)

4 DC precision requirements. In many cases, it will not be

2 necessary to correct for temperature effects (i.e.,
calibrate) in a design. In the other cases, the correction
0
will be small.
-2

-4

-6

-8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

FIGURE 1: Input Offset Voltage vs.

Ambient Temperature with VDD = 4.5V.

8
22 Samples
6 VDD = 45V
Input Offset Voltage (μV)

-2

-4

-6

-8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)

FIGURE 2: Input Offset Voltage vs.

Ambient Temperature with VDD = 45V.

DS20006136A-page 2  2018 Microchip Technology Inc.

 MCP6V51
1.0 ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD - VSS ................................................................................................................................................................49.5V
Current at Input Pins ............................................................................................................................................ ±10 mA
Analog Inputs (VIN+ and VIN-) (Note 1)..................................................................................... VSS - 1.0V to VDD + 1.0V
All Other Inputs and Outputs .................................................................................................... VSS - 0.3V to VDD + 0.3V
Difference Input Voltage .............................................................................................................................................±1V
Output Short Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins ...................................................................................................................... ±50 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM)   2 kV, 750V, 200V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Note 1: See Section 4.2.1, Input Protection.

1.2 Electrical Specifications

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Input Offset
Input Offset Voltage VOS -15 ±2.4 +15 µV TA = +25°C
Input Offset Voltage Drift with TC1 -31 ±5 +31 nV/°C TA = -40 to +125°C,
Temperature (Linear Temp. Co.) VDD = 4.5V (Note 1)
TC1 -36 ±7 +36 nV/°C TA = -40 to +125°C,
VDD = 45V
(Note 1)
Input Offset Voltage Quadratic TC2 — ±42 — nV/ TA = -40 to +125°C
Temp. Co. °C2 VDD = 4.5V
TC2 — ±38 — nV/ TA = -40 to +125°C
°C2 VDD = 45V
Input Offset Voltage Aging ∆VOS — ±2 — µV 408 hours Life Test at
+150°C,
measured at +25°C
Power Supply Rejection Ratio PSRR 134 160 — dB
124 138 — dB TA = -40°C to +125°C
VDD = 45V (Note 1)
Input Bias Current and Impedance
Input Bias Current IB -250 ±60 +250 pA VDD = 45V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.

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MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Input Bias Current across IB — ±80 — pA TA = +85°C
Temperature IB -4 ±1.4 +4 nA TA = +125°C (Note 1)
Input Offset Current IOS -1 ±0.28 +1 nA VDD = 45V
Input Offset Current across IOS — ±0.32 — nA TA = +85°C
Temperature IOS -8 ±0.45 +8 nA TA = +125°C (Note 1)
Common Mode Input Impedance ZCM — 120G||3 — Ω||pF
Differential Input Impedance ZDIFF — 2.5M||5.2 — Ω||pF
Common Mode
Common Mode VCML — — VSS - 0.3 V (Note 2)
Input Voltage Range Low
Common Mode VCMH VDD - 2.1 — — V (Note 2)
Input Voltage Range High
Common Mode Rejection Ratio CMRR 110 125 — dB VDD = 4.5V,
VCM = -0.3V to 2.4V
(Note 2)
106 116 — dB VDD = 4.5V
TA = -40°C to +125°C,
(Note 1)
CMRR 135 150 — dB VDD = 45V,
VCM = -0.3V to 42.9V
(Note 2)
128 140 — dB VDD = 45V
TA = -40°C to +125°C,
(Note 1)
Open-Loop Gain
DC Open-Loop Gain AOL 124 142 — dB VDD = 4.5V,
VOUT = 0.3V to 4.2V
120 139 — dB VDD = 4.5V
TA = -40°C to +125°C,
(Note 1)
AOL 140 164 — dB VDD = 45V,
VOUT = 0.3V to 44.7V
134 160 — dB VDD = 45V
TA = -40°C to +125°C,
(Note 1)
Output
Minimum Output Voltage Swing VOL — VSS + 45 VSS + 60 mV RL = 1 kΩ, VDD = 4.5V
— VSS + 500 VSS + 1000 RL = 1 kΩ, VDD = 45V
— VSS + 6 VSS + 20 RL = 10 kΩ, VDD = 4.5V
— VSS + 50 VSS + 70 RL = 10 kΩ, VDD = 45V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.

DS20006136A-page 4  2018 Microchip Technology Inc.

 MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Maximum Output Voltage Swing VOH VDD - 150 VDD - 100 — mV RL = 1 kΩ, VDD = 4.5V
VDD - 2500 VDD - 1500 — RL = 1 kΩ, VDD = 45V
VDD - 20 VDD - 12 — RL = 10 kΩ, VDD = 4.5V
VDD - 200 VDD - 100 — RL = 10 kΩ, VDD = 45V
Output Short Circuit Current ISC+ — 46 — mA
ISC- — 36 — mA
Closed-loop Output Resistance ROUT — 16 — Ω f = 0.1 MHz, IO = 0,
G=1
Capacitive Load Drive CL — 100 — pF G=1
Power Supply
Supply Voltage VDD 4.5 — 45 V
Quiescent Current per Amplifier IQ 310 460 590 µA VDD = 4.5V, IO = 0
310 470 590 µA VDD = 45V, IO = 0
— 540 670 µA IO = 0,
TA = -40 to +125°C
(Note 1)
(Figure 2-22)
Power-on Reset (POR) Trip VPOR — 2.3 — V
Voltage
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.

AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Amplifier AC Response
Gain Bandwidth Product GBWP — 1.8 — MHz VDD = 4.5V, VIN = 10 mVpp, Gain = 100
— 2 — MHz VDD = 45V, VIN = 10 mVpp, Gain = 100
Slew Rate SR — 1.2 — V/µs (Figure 2-44)
Phase Margin PM — 66 — deg. VDD = 45V
Amplifier Noise Response
Input Noise Voltage Eni — 0.1 — µVP-P f = 0.01 Hz to 1 Hz
Eni — 0.21 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 10.2 — nV/√Hz f = 1 kHz
Input Noise Current Density ini — 4 — fA/√Hz
Amplifier Step Response
Start-Up Time tSTR — 200 — µs G = +1, 1% VOUT settling (Note 1)
Offset Correction Settling Time tSTL — 45 — µs G = +1, VIN step of 2V,
VOS within ±100 µV of its final value
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.
2: tSTL and tODR include some uncertainty due to clock edge timing.

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MCP6V51
AC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Output Overdrive Recovery Time tODR — 65 — µs G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 2)
EMI Protection
EMI Rejection Ratio EMIRR — 80 — dB VIN = 0.1 VPK, f = 400 MHz, VDD = 45V
— 95 — VIN = 0.1 VPK, f = 900 MHz, VDD = 45V
— 108 — VIN = 0.1 VPK, f = 1800 MHz, VDD = 45V
— 109 — VIN = 0.1 VPK, f = 2400 MHz, VDD = 45V
— 109 — VIN = 0.1 VPK, f = 5600 MHz, VDD = 45V
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.
2: tSTL and tODR include some uncertainty due to clock edge timing.

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +4.5V to +45V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C (Note 1)
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8LD-MSOP JA — 206 — °C/W
Thermal Resistance, 5LD-SOT-23 JA — 115 — °C/W
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).

DS20006136A-page 6  2018 Microchip Technology Inc.

 MCP6V51
1.3 Timing Diagrams 1.4 Test Circuits
The Timing Diagrams provide a depiction of the The circuits used for most DC and AC tests are shown
Amplifier Step Response specifications listed under the in Figure 1-4 and Figure 1-5. Lay the bypass
AC Electrical Specifications table. capacitors out as discussed in Section 4.3.10 “Supply
Bypassing and Filtering”. RN is equal to the parallel
combination of RF and RG to minimize bias current
2.3V VDD
VDD 0V effects.

tSTR 1.01(VDD/3) VDD

1 µF
VOUT
0.99(VDD/3) VIN RN
+ RISO VOUT
MCP6V51
FIGURE 1-1: Amplifier Start-Up. -
CL RL
100 nF
VDD/3
VIN VL
RG RF
tSTL VOS + 100 µV FIGURE 1-4: AC and DC Test Circuit for
VOS Most Noninverting Gain Conditions.
VOS – 100 µV
VDD
FIGURE 1-2: Offset Correction Settling 1 µF
Time. VDD/3 RN
+ RISO VOUT
MCP6V51
-
VIN CL RL
100 nF
VIN
tODR
VL
RG RF
VDD
FIGURE 1-5: AC and DC Test Circuit for
tODR Most Inverting Gain Conditions.
VOUT VDD/2 The circuit in Figure 1-6 tests the input’s dynamic
VSS behavior (i.e., tSTR, tSTL and tODR). The potentiometer
balances the resistor network (VOUT should equal VREF
FIGURE 1-3: Output Overdrive Recovery. at DC). The op amp’s Common Mode Input Voltage is
VCM = VIN/3. The error at the input (VERR) appears at
VOUT with a noise gain of approx. 10 V/V.

1.1 kΩ 10 kΩ 500Ω
0.1% 0.1% 25 turn
VREF = VDD/3

VDD
RISO
1 µF 0Ω
VOUT
VIN
100 nF
CL RL
MCP6V51 100 pF open

VL
1.1 kΩ 10 kΩ 249Ω
0.1% 0.1% 1%
FIGURE 1-6: Test Circuit for Dynamic
Input Behavior.

 2018 Microchip Technology Inc. DS20006136A-page 7

MCP6V51
NOTES:

DS20006136A-page 8  2018 Microchip Technology Inc.

 MCP6V51
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.
2.1 DC Input Precision

35%
7611 Samples 8
Percentage of Occurences

Representative Part
30% TA = 25ºC 6

Input Offset Voltage (μV)

VDD = 45V
VDD = 4.5V
25% 4
VDD = 4.5V
20% 2
15% 0
TA = +125°C
10% -2 TA = +85°C
TA = +25°C
5% -4 TA = - 40°C

0% -6
-10 -8 -6 -4 -2 0 2 4 6 8 10 -8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Input Offset Voltage (μV)
Output Voltage (V)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs.
Output Voltage with VDD = 4.5V.

40% 8
22 Samples
Percentage of Occurances

35% TA = -40°C to +125°C Representative Part

6
Input Offset Voltage (μV)

VDD = 45V
30%
VDD = 45V 4
25%
VDD = 4.5V 2
20%
0
TA = +125°C
15% TA = +85°C
-2
TA = +25°C
10% TA = - 40°C
-4
5%
-6
0%
-18 -15 -12 -9 -6 -3 0 3 6 9 12 15 18 -8
-1 4 9 14 19 24 29 34 39 44
Input Offset Voltage Drift; TC1 (nV/°C) Output Voltage (V)

FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs.
Output Voltage with VDD = 45V.

20 8.0
VDD = 4.5V
6.0
Input Offset Voltage (μV)

15 Representative Part
Input Offset Voltage (μV)

10 4.0
TA = -40°C
5 2.0
TA = +25°C
0 0.0
TA = +125°C
-5 -2.0 TA = +85°C
TA = +25°C
-10 TA = +85°C -4.0 TA = - 40°C
TA = +125°C
-15 -6.0

-20 -8.0
0 5 10 15 20 25 30 35 40 45 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
Power Supply Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Power Supply Voltage. Common Mode Voltage with VDD = 4.5V

 2018 Microchip Technology Inc. DS20006136A-page 9

MCP6V51

8.0 60%

Percentage of Occurrences
VDD = 45V
Input Offset Voltage (μV)

6.0 Representative Part 474 Samples

50%
TA = +25ºC VDD = 45V
4.0
40%
2.0
0.0 30%

-2.0 TA = +125°C 20%

TA = +85°C
-4.0 TA = +25°C VDD = 4.5V
TA = - 40°C 10%
-6.0
-8.0 0%

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5
-1 4 9 14 19 24 29 34 39 44
Common Mode Input Voltage (V) 1/AOL (μV/V)

FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: DC Open-Loop Gain.
Common Mode Voltage with VDD = 45V.

90% 160
Percentage of Occurrences

80% 488 Samples PSRR

150

CMRR, PSRR (dB)

70% TA = +25ºC
VDD = 45V
60%
140
50% CMRR @ VDD = 45V
40% @ VDD = 4.5V
130
30%
20%
VDD = 4.5V 120
10%
0% 110
-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

1/CMRR (μV/V) Ambient Temperature (°C)

FIGURE 2-8: CMRR. FIGURE 2-11: CMRR and PSRR vs.

Ambient Temperature.

35% 170
DC Open-Loop Gain (dB)
Percentage of Occurrences

30%
488 Samples
TA = +25ºC 160
VDD= 45V
25%

20% 150

15%
140
VDD= 4.5V
10%

5%
130

0%
120
-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.1

-50 -25 0 25 50 75 100 125

1/PSRR (μV/V) Ambient Temperature (°C)

FIGURE 2-9: PSRR. FIGURE 2-12: DC Open-Loop Gain vs.

Ambient Temperature.

DS20006136A-page 10  2018 Microchip Technology Inc.

 MCP6V51

500 1m
Input Bias, Offset Currents (pA)
VDD = 45V
400

Input Current Magnitude (A)

TA = +85 ºC 100μ
300
Input Offset Current
200 10μ
100 1μ
0
Input Bias Current 100n TA = +125°C
-100 TA = +85°C
-200 10n TA = +25°C
TA = -40°C
-300
1n
-400
-500 100p
0 5 10 15 20 25 30 35 40 45 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Common Mode Voltage (V)
Input Voltage (V)

FIGURE 2-13: Input Bias and Offset FIGURE 2-16: Input Bias Current vs. Input
Currents vs. Common Mode Input Voltage with Voltage (Below VSS).
TA = +85°C.

2000
Input Bias, Offset Currents (pA)

VDD = 45V
1500 TA = +125 ºC

1000 Input Bias Current

500

-500 Input Offset Current

-1000
0 5 10 15 20 25 30 35 40 45
Input Common Mode Voltage (V)

FIGURE 2-14: Input Bias and Offset

Currents vs. Common Mode Input Voltage with
TA = +125°C.

10n
Input Bias, Offset Currents (A)

45V
1n
IOS

100p
4.5V
IB
10p

1p
25

35

45

55

65

75

85

95

105

115

125

Ambient Temperature (°C)

FIGURE 2-15: Input Bias and Offset

Currents vs. Ambient Temperature with
VDD = 45V.

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MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.

2.2 Other DC Voltages and Currents

2.5 200

Output Voltage Headroom (mV)

Input Common Mode Voltage

RL = 10 kȍ
2
Upper (VDD - VCMH) 150
Headroom (V)

1.5

1 100

0.5 VDD - VOH

VDD = 45V
Lower (VCML - VSS) 50
0 VOL - VSS
VDD = 4.5V

-0.5 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

FIGURE 2-17: Input Common Mode FIGURE 2-20: Output Voltage Headroom
Voltage Headroom (Range) vs. Ambient vs Temperature RL = 10 kΩ.
Temperature.

1000 80
Output Short Circuit Current
Output Voltage Headroom

VDD -VOH 60

100 40
(mV)

20 TA = +125°C
(mA)

VDD = 4.5V VOL -VSS TA = +85°C

0 TA = +25°C
TA = -40°C
10
-20

VDD = 45V -40

1 -60
0.1 1 10 0 5 10 15 20 25 30 35 40 45
Output Current Magnitude (mA) Power Supply Voltage (V)

FIGURE 2-18: Output Voltage Headroom FIGURE 2-21: Output Short Circuit Current
vs. Output Current. vs. Power Supply Voltage.
Output Voltage Headroom (mV)

2000 700
RL = 1 kȍ
600
Quiescent Current

1500
(μA/Amplifier)

500

400
1000
VDD - VOH 300 TA = +125°C
VDD = 45V TA = +85°C
200 TA = +25°C
500 TA = -40°C
VOL - VSS
VDD = 4.5V 100
0 0
-50 -25 0 25 50 75 100 125 0 10 20 30 40 50
Ambient Temperature (°C) Power Supply Voltage (V)

FIGURE 2-19: Output Voltage Headroom FIGURE 2-22: Supply Current vs. Power
vs. Ambient Temperature. Supply Voltage.

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 MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.

2.3 Frequency Response

180
VDD = 45V 4.0 80

Gain Bandwidth Product (MHz)

160
3.5 PM 70
140
CMRR, PSRR (dB)

PSRR+ CMRR
120 3.0 60

Phase Margin
100 2.5 VDD = 4.5V VDD = 45V 50
80
PSRR- 2.0 40
60 GBWP
1.5 30
40
1.0 20
20
0 0.5 10
1 10 100 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Frequency (Hz)

FIGURE 2-23: CMRR and PSRR vs. FIGURE 2-26: Gain Bandwidth Product
Frequency. and Phase Margin vs. Ambient Temperature.

5 90
140 -30
VDD = 45V

Gain Bandwidth Product (MHz)

120 -60
Phase
4 80
Open-Loop Phase (°)
Open-Loop Gain (dB)

Phase Margin (º)

100 -90
80 -120 3 PM 70
60 -150
Gain 2 60
40 -180
GBWP = 1.8 MHz
GBWP
20 VDD = 4.5V -210 1 50
RL= 10 kΩ
0 CL = 100 pF -240
'RP3ROHP+]
-20 -270 0 40
1 10 100 1,000
100 10k 100,000
1k 10,000 1M10,000,000
10M
100k1,000,000 0 5 10 15 20 25 30 35 40 45
Frequency (Hz)
Common Mode Input Voltage (V)

FIGURE 2-24: Open-Loop Gain vs. FIGURE 2-27: Gain Bandwidth Product
Frequency with VDD = 4.5V. and Phase Margin vs. Common Mode Input
Voltage.

1000
140 -30 VDD = 4.5V
100
120 -60
Closed Loop Output

Phase
Open-Loop Phase (°)
Open-Loop Gain (dB)

Impedance (:)

100 -90 10

80 -120 1

60 -150 0.1 GN:

Gain 101 V/V
40 -180 11 V/V
GBWP = 2 MHz 0.01
VDD = 45V 1 V/V
20 -210
RL= 10 kΩ 0.001
CL = 100 pF
0 'RP3ROHP+]
-240
0.0001
-20 -270 1 10 100 1k 10k 100k 1M 10M 100M
1 10 100 1,000
100 10k 100,000
1k 10,000 1M10,000,000
10M
100k1,000,000
Frequency (Hz) Frequency (Hz)

FIGURE 2-25: Open-Loop Gain vs. FIGURE 2-28: Closed-Loop Output

Frequency with VDD = 45V. Impedance vs. Frequency with VDD = 4.5V.

 2018 Microchip Technology Inc. DS20006136A-page 13

MCP6V51

1000
VDD = 45V
100
Closed Loop Output
Impedance (:)

10

1 GN:
101 V/V
0.1 11 V/V
1 V/V
0.01

0.001

0.0001
1 10 100 1k 10k 100k 1M 10M 100M

Frequency (Hz)

FIGURE 2-29: Closed-Loop Output

Impedance vs. Frequency with VDD = 45V.

100
Output Voltage Swing (VP-P)

VDD = 45V

10

VDD = 4.5V

0
100 1k 10k 100k 1M 10M
Frequency (Hz)

FIGURE 2-30: Maximum Output Voltage

Swing vs. Frequency.

120
110
100
90
EMIRR (dB)

80
VDD = 45V
70
60
50
40
VDD = 4.5V
30
20 VINPK = 100 mV

10
10
10M 100
100M 1000
1G 10000
10G
Frequency (Hz)

FIGURE 2-31: EMIRR vs. Frequency.

DS20006136A-page 14  2018 Microchip Technology Inc.

 MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.

2.4 Input Noise

1000 1000

Integrated Input Noise Voltage;

VDD = 45V, green
Input Noise Voltage Density;

VDD = 4.5V, blue

100 100
eni (nV/¥Hz)

Eni (μVP-P)
eni

10 10

Eni (0 Hz to f)
1 1
1
1.E+0 10
1.E+1 100
1.E+2 1k
1.E+3 10k
1.E+4 100k
1.E+5
Frequency (Hz)

FIGURE 2-32: Input Noise Voltage Density

and Integrated Input Noise Voltage vs.
Frequency.

VDD = 4.5V
Input Noise Voltage; eni(t)

NPBW = 10 Hz
(0.1 μV/div)

NPBW = 1 Hz

0 10 20 30 40 50 60
Time (s)

FIGURE 2-33: Input Noise vs. Time with

1 Hz and 10 Hz Filters and VDD = 4.5V.

VDD = 45V
Input Noise Voltage; eni(t)

NPBW = 10 Hz
(0.1 μV/div)

NPBW = 1 Hz

0 10 20 30 40 50 60
Time (s)

FIGURE 2-34: Input Noise vs. Time with

1 Hz and 10 Hz Filters and VDD = 45V.

 2018 Microchip Technology Inc. DS20006136A-page 15

MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.

2.5 Time Response

20 100
VDD = +/-15V

Output Voltage (20 mV/div)

G = +1 V/V
Input Offset Voltage (μV)

PCB Temperature (ºC)

15 60
TPCB

10 20
VIN
VDD = 45V
VDD = 4.5V
VOUT
5 -20
VOS
0 -60
Temperature increased by
using heat gun for 3 seconds
-5 -100
0 20 40 60 80 100 120 140 160 180 200 0 1 2 3 4 5 6 7 8 9 10
Time (s) Time (μs)

FIGURE 2-35: Input Offset Voltage vs. FIGURE 2-38: Noninverting Small Signal
Time with Temperature Change. Step Response.

2000 48 15
VDD = +/-15 V
1750 42 G = +1 V/V
Power Supply Voltage (V)

VDD 10
Input Offset Voltage (mV)

1500 36
VDD Bypass = 1PF
Output Voltage (V)

1250 VDD = 45V 30 5

G = +1 V/V VIN VOUT
1000 24
0
750 18
500 12 -5

250 6 -10
VOS
0 0
-15
-250 -6 0 10 20 30 40 50 60 70 80 90 100
0 2 4 6 8 10 12 14 16 18 20
Time (ms) Time (μs)

FIGURE 2-36: Input Offset Voltage vs. FIGURE 2-39: Noninverting Large Signal
Time at Power-Up. Step Response.

30 30
VDD = +/-22.5V VDD = +/-22.5 V
G = +1 V/V G = +1 V/V
20 9,1 933 20
Input, Output Voltages (V)

Output Voltage (V)

10 10 VIN
VOUT
0 0

-10 -10
VOUT
-20
-20
VIN -30
-30
0 20 40 60 80 100 120 140 160 180 200
Time (100 μs/div)
Time (μs)

FIGURE 2-37: The MCP6V51 Shows No FIGURE 2-40: Noninverting 40 VPP Step
Input Phase Reversal with Overdrive. Response.

DS20006136A-page 16  2018 Microchip Technology Inc.

 MCP6V51

2.0
VIN
Output Voltage (20mV/div) VOUT 1.8
Falling Edge, VDD = 45V

Slew Rate (V/μs)

1.6 Falling Edge, VDD = 4.5V

1.4
Rising Edge, VDD = 45V

1.2
Rising Edge, VDD = 4.5V
VDD = +/-15V
1.0
G = -1 V/V
0.8
0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125
Time (μs) Ambient Temperature (°C)

FIGURE 2-41: Inverting Small Signal Step FIGURE 2-44: Slew Rate vs. Ambient
Response. Temperature.

15 30
VDD = +/-15 V
G = -1 V/V
GVIN VOUT
10 20
Output Voltage (V)

Output Voltage (V)

5 10
VIN
0 VDD = 45 V
0 G = -10V/V
VOUT 0.5V Overdrive
-5
-10
-10 GVIN VOUT
-20
-15
0 10 20 30 40 50 60 70 80 90 100 -30

Time (μs) Time (100 us/div)

FIGURE 2-42: Inverting Large Signal Step FIGURE 2-45: Output Overdrive Recovery
Response. vs. Time with G = -10 V/V.

30 1m
VDD = +/-22.5 V 0.5V Input Overdrive
Overdrive Recovery Time (s)

VIN G = -1 V/V
20
VDD = 45V
Output Voltage (V)

10 100μ

0
tODR, high tODR, low VDD = 4.5V
-10 10μ
VOUT
-20

-30 1μ
0 20 40 60 80 100 120 140 160 180 200 1 10 100 1000
Time (μs) Inverting Gain Magnitude (V/V)

FIGURE 2-43: Inverting 40 VPP Step FIGURE 2-46: Output Overdrive Recovery
Response. Time vs. Inverting Gain.

 2018 Microchip Technology Inc. DS20006136A-page 17

MCP6V51
NOTES:

DS20006136A-page 18  2018 Microchip Technology Inc.

 MCP6V51
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6V51
Symbol Description
SOT23-5 MSOP-8
1 6 VOUT Output
4 2 VIN- Inverting Input
3 3 VIN+ Noninverting Input
2 4 VSS Negative Power Supply
5 7 VDD Positive Power Supply
— 1, 5, 8 NC Do not connect (no internal connection)

3.1 Analog Output

The analog output pins (VOUT) are low-impedance
voltage sources.

3.2 Analog Inputs

The noninverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 4.5V to 45V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.

 2018 Microchip Technology Inc. DS20006136A-page 19

MCP6V51
NOTES:

DS20006136A-page 20  2018 Microchip Technology Inc.

 MCP6V51
4.0 APPLICATIONS The Output Buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The MCP6V51 is designed for precision applications
The Oscillator runs at fOSC1 = 200 kHz. Its output is
with requirements for small packages and low power.
divided by two, to produce the chopping clock rate of
Its wide supply voltage range and low quiescent current
fCHOP = 100 kHz.
make the MCP6V51 devices ideal for industrial
applications. The internal Power-on Reset (POR) starts the part in a
known good state, protecting against power supply
4.1 Overview of Zero-Drift Operation brown-outs.
The Digital Control block controls switching and POR
Figure 4-1 shows a simplified diagram of the
events.
MCP6V51 zero-drift op amp. This diagram will be used
to explain how slow voltage errors are reduced in this 4.1.2 CHOPPING ACTION
architecture (much better VOS, VOS/TA (TC1),
CMRR, PSRR, AOL and 1/f noise). Figure 4-2 shows the amplifier connections for the first
phase of the chopping clock and Figure 4-3 shows the
connections for the second phase. Its slow voltage
VREF errors alternate in polarity, making the average error
-
small.
VOUT Output
Buffer
VIN+
VIN+ +
+
+ -
- VIN- Main +
VIN- Main + Amp. - NC
Amp. - NC +
+ -
-
Low-Pass
Low-Pass Filter
Filter

+ Aux. +
Chopper Chopper - Amp. -
+ Aux. +
Input Output
- Amp. -
Switches Switches

FIGURE 4-2: First Chopping Clock Phase;

Equivalent Amplifier Diagram.
Oscillator Digital Control POR
VIN+
FIGURE 4-1: Simplified Zero-Drift Op +
Amp Functional Diagram. -
Main +
VIN-
+ Amp. - NC
4.1.1 BUILDING BLOCKS
-
The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input Low-Pass
pair (+ and - pins at the top left) is used for the higher Filter
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the
low-frequency portion of the input signal and corrects
+ Aux. +
the op amp’s input offset voltage. Both inputs are - Amp. -
added together internally.
The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher FIGURE 4-3: Second Chopping Clock
frequencies, while white noise is modulated to low Phase; Equivalent Amplifier Diagram.
frequency.
The Low-Pass Filter reduces high-frequency content,
including harmonics of the chopping clock.

 2018 Microchip Technology Inc. DS20006136A-page 21

MCP6V51
4.2 Other Functional Blocks In addition, the input is protected by a pair of back-to-
back diodes across the amplifier’s inputs, which will
4.2.1 INPUT PROTECTION limit the voltage that can develop across the inputs to
about +/-1V.
The MCP6V51 can be operated on a single supply
voltage ranging from 4.5V to 45V, or in a split-supply In some applications, it may be necessary to prevent
application (+/-2.25V to +/- 22.5V). The input common- excessive voltages from reaching the op amp inputs;
mode range extends below the negative rail, Figure 4-5 shows one approach of protecting these
VCML = VSS - 0.3V at 25°C, while maintaining high inputs. D1 and D2 may be small-signal silicon diodes,
CMRR (135 dB min. at 45VDD). The upper range of the Schottky diodes for lower clamping voltages or
input common-mode is limited to VCMH = VDD - 2.1V. diode-connected FETs for low leakage.
To ensure proper operation, these VCM limits, along
with any potential overvoltage/current conditions as
VDD
described in the following paragraphs, should be taken
into consideration.
U1
D1
4.2.1.1 Phase Reversal MCP6V51
V1 +
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply D2 VOUT
voltages. Figure 2-37 shows an input voltage V2 -
exceeding both supplies with no phase inversion.

4.2.1.2 Input Voltage Limits FIGURE 4-5: Protecting the Analog Inputs
In order to prevent damage and/or improper operation against High Voltages.
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum 4.2.1.3 Input Current Limits
Ratings †). This requirement is independent of the In order to prevent damage and/or improper operation
current limits discussed later on. of these amplifiers, the circuit must limit the currents
The ESD protection on the inputs can be depicted as into the input pins (see Section 1.1, Absolute
shown in Figure 4-4. This structure was chosen to Maximum Ratings †). This requirement is
protect the input transistors against many (but not all) independent of the voltage limits discussed previously.
overvoltage conditions and to minimize input bias Figure 4-6 shows one approach to protecting these
current (IB). inputs. The R1 and R2 resistors limit the possible
The input ESD diodes clamp the inputs when they try current in or out of the input pins (and into D1 and D2).
to go more than one diode drop below VSS. They also Once the diode is forward biased, any current will flow
clamp any voltages well above VDD; their breakdown into the VDD supply line.
voltage is high enough to allow normal operation but
not low enough to protect against slow overvoltage VDD
(beyond VDD) events. Very fast ESD events (that meet
the specification) are limited so that damage can
U1
largely be prevented. D1
MCP6V51
V1 +
R1 D2 VOUT
VDD Bond -
Pad V2
R2

VIN+
Bond Input Bond
VIN- V SS – min  V1 V2 
Pad Stage Pad min(R1 R 2   --------------------------------------------
10 mA

max  V 1 V 2  – V DD
min(R 1 R 2   ------------------------------------------------
VSS Bond 10 mA
Pad

FIGURE 4-4: Simplified Analog Input ESD FIGURE 4-6: Protecting the Analog Inputs
Structures. Against High Currents.

DS20006136A-page 22  2018 Microchip Technology Inc.

 MCP6V51
It is also possible to connect the diodes to the left of the To derive the Power dissipation of the device, add the
R1 and R2 resistors. In this case, the currents through terms for the devices’ quiescent power and the load
the D1 and D2 diodes need to be limited by some other power as shown in Equation 4-2:
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and EQUATION 4-2:
VIN-) should be very small.
A significant amount of current can flow out of the
PD =  V DD – VSS   I Q + I OUT   V DD – VOUT 
inputs (through the ESD diodes) when the Common
Mode Voltage (VCM) is below ground (VSS); see
Figure 2-16. This assumes that the device is sourcing the load
current, i.e. current flowing from the VDD supply into the
4.2.2 INTEGRATED EMI FILTER load. Use the term (IOUT × (VOUT - VSS)) when the
The MCP6V51 has an integrated low-pass filter in its device is sinking current. Note that this simple example
inputs for the dedicated purpose of reducing any assumes a constant (DC) signal current flow.
electromagnetic or RF interference (EMI, RFI). The on- The thermal shutdown circuitry activates as soon as
chip filter is designed as a 2nd-order RC low-pass, the junction temperature reaches approximately
which sets a bandwidth limit of approximately +175°C causing the amplifier’s output stage to be tri-
115 MHz and attenuates the high-frequency stated (high-impedance) effectively disabling any
interference. Performance results of the MCP6V51’s output current flow. The amplifier will remain in this
EMI rejection ratio (EMIRR) under various conditions disabled state until the junction temperature has cooled
can be seen in Figure 2-31 and Figure 2-33. down to approximately +160°C. At this point the
thermal shutdown circuitry will enable the output stage
4.2.3 RAIL-TO-RAIL OUTPUT of the MCP6V51 amplifier and the device will resume
The Output Voltage Range of the MCP6V51 zero-drift normal operation.
op amps is typically VDD - 100 mV, and VSS + 50 mV If a fault condition persists, for example the amplifier’s
when RL = 10 kΩ is connected to VDD/2 and output (VOUT) is shorted causing excessive output
VDD = 45V. Refer to Figure 2-18, Figure 2-19 and current, the thermal shutdown circuity may be triggered
Figure 2-20 for more information. again and the previously described cycle repeats. This
may continue until the fault condition is removed.
4.2.4 THERMAL SHUTDOWN
It should be noted that the thermal shutdown feature of
Under certain operating conditions, the MCP6V51 the MCP6V51 does not guarantee that the device will
amplifier can be subjected to a rise of its die remain undamaged when operated under stress
temperature above the specified maximum junction conditions during which the device is placed into the
temperature of 150°C. To control possible overheating shutdown mode.
and damage, the MCP6V51 amplifier has internal
thermal shutdown circuitry. Especially when operating
with the maximum supply voltage of 45V, observe that
4.3 Application Tips
the ambient temperature and/or the amplifier’s output
4.3.1 INPUT OFFSET VOLTAGE OVER
current are such that the junction temperature remains
below the specified limit. To estimate the junction
TEMPERATURE
temperature (TJ) consider these factors: the total power Table DC Electrical Specifications gives both the
dissipation of the device (PD) and the ambient linear and quadratic temperature coefficients (TC1 and
temperature at the device package (TA), and use TC2) of input offset voltage. The input offset voltage, at
Equation 4-1 below. any temperature in the specified range, can be
calculated as follows:
EQUATION 4-1:
EQUATION 4-3:
T J = P D   JA + T A VOS  T A  = V OS + TC 1  T + TC2  T
2

Where:
Where:
JA = the thermal resistance between the die
T = TA – 25°C
and the ambient environment, as
shown in Temperature VOS(TA) = Input offset voltage at TA
Specifications VOS = Input offset voltage at +25°C
TC1 = Linear temperature coefficient
TC2 = Quadratic temperature coefficient

 2018 Microchip Technology Inc. DS20006136A-page 23

MCP6V51
4.3.2 DC GAIN PLOTS reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
Figure 2-8, Figure 2-9 and Figure 2-10 are
response. These zero-drift op amps have a different
histograms of the reciprocals (in units of µV/V) of
output impedance compared to standard linear op
CMRR, PSRR and AOL, respectively. They represent
amps, due to their unique topology.
the change in Input Offset Voltage (VOS) with a change
in Common Mode Input Voltage (VCM), Power Supply When driving a capacitive load with these op amps, a
Voltage (VDD) and Output Voltage (VOUT). series resistor at the output (RISO in Figure 4-8)
improves the feedback loop’s phase margin (stability)
The 1/AOL histogram is centered near 0 µV/V because
by making the output load resistive at higher
the measurements are dominated by the op amp’s
frequencies. The bandwidth will be generally lower
input noise. The negative values shown represent
than the bandwidth with no capacitive load.
noise and tester limitations, not unstable behavior.
Production tests make multiple VOS measurements,
Figure 4-7 gives recommended RISO values for
which validates an op amp's stability; an unstable part
different capacitive loads and gains. The x-axis is the
would show greater VOS variability or the output would
load capacitance (CL). The y-axis is the resistance
stick at one of the supply rails.
(RISO).
4.3.3 OFFSET AT POWER-UP GN is the circuit’s noise gain. For non-inverting gains,
GN and the Signal Gain are equal. For inverting gains,
When these parts power up, the input offset (VOS)
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain may cause the
output to reach one of the two rails. In this case, the 1000
VDD = 45 V
time to a valid output is delayed by an output overdrive
Recommended R ISO (:)
RL = 10 kȍ
time (tODR), in addition to the start-up time (tSTR).
100
To avoid this extended start-up time, reducing the gain
is one method. Adding a capacitor across the feedback
resistor (RF) is another method.
10
GN:
4.3.4 SOURCE RESISTANCES 1 V/V
10 V/V
The input bias currents have two significant 100 V/V
1
components: switching glitches that dominate at room 10p 100p 1n 10n 100n 1μ
temperature and below, and input ESD diode leakage Normalized Load Capacitance; CL/—GN (F)
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and FIGURE 4-7: Recommended RISO Values
equal. This minimizes the output offset voltage caused for Capacitive Loads.
by the input bias currents. After selecting RISO for your circuit, double check the
The inputs should see a resistance on the order of 10Ω resulting frequency response peaking and step
to 1 kΩ at high frequencies (i.e., above 1 MHz). This response overshoot. Modify the RISO value until the
helps minimize the impact of switching glitches, which response is reasonable. Bench evaluation is helpful.
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.

4.3.5 SOURCE CAPACITANCE

The capacitances seen by the two inputs should be
small. Large input capacitances and source
resistances, together with high gain, can lead to
instability.

4.3.6 CAPACITIVE LOADS

Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is

DS20006136A-page 24  2018 Microchip Technology Inc.

 MCP6V51
4.3.7 STABILIZING OUTPUT LOADS CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
This family of zero-drift op amps has an output
impedance (Figure 2-28 and Figure 2-29) that has a The largest value of RF that should be used depends
double zero when the gain is low. This can cause a on the noise gain (see GN in Section 4.3.6
large phase shift in feedback networks that have low- “Capacitive Loads”), CG and the open-loop gain’s
impedance near the part’s cross-over frequency. This phase shift. An approximate limit for RF is shown in
phase shift can cause stability problems. Equation 4-4.
Figure 4-8 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load. EQUATION 4-4:
This load needs to be large enough to maintain 3.5 pF
stability; it is recommended to design for a total load of R F  10 k   ---------------  G N2
CG
10 kΩ, or higher.

Some applications may modify these values to reduce

RG RF RISO either output loading or gain peaking (step-response
VOUT overshoot).
- At high gains, RN needs to be small, in order to prevent
RL CL
+ positive feedback and oscillations. Large CN values
can also help.
U1
MCP6V51

FIGURE 4-8: Output Resistor, RISO,

Stabilizes Capacitive Loads

4.3.8 GAIN PEAKING

Figure 4-9 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The CN and CG capacitances
represent the total capacitance at the input pins; they
include the op amp’s Common Mode Input
Capacitance (CCM), board parasitic capacitance and
any capacitor placed in parallel. The CFP capacitance
represents the parasitic capacitance coupling between
the output and the non-inverting input pins.

CN
RN CFP
VP
U1 +
VOUT
MCP6V51 -
VM
RG RF
CG

FIGURE 4-9: Amplifier with Parasitic

Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/
V), which causes an increase in gain at high
frequencies. CG also reduces the phase margin of the
feedback loop, which becomes less stable. This effect
can be reduced by either reducing CG or RF||RG.

 2018 Microchip Technology Inc. DS20006136A-page 25

MCP6V51
4.3.9 REDUCING UNDESIRED NOISE Typical thermojunctions have temperature-to-voltage
AND SIGNALS conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
Reduce undesired noise and signals with:
Microchip’s AN1258 Application Note – “Op Amp
• Low bandwidth signal filters:
Precision Design: PCB Layout Techniques” (DS01258)
- Minimize random analog noise contains in-depth information on PCB layout
- Reduce interfering signals techniques that minimize thermojunction effects. It also
• Good PCB layout techniques: discusses other effects, such as crosstalk,
- Minimize crosstalk impedances, mechanical stresses and humidity.
- Minimize parasitic capacitances and
4.3.11.2 Crosstalk
inductances that interact with fast switching
edges DC crosstalk causes offsets that appear as a larger
• Good power supply design: input offset voltage. Common causes include:
- Isolation from other parts • Common mode noise (remote sensors)
- Filtering of interference on supply line(s) • Ground loops (current return paths)
• Power supply coupling
4.3.10 SUPPLY BYPASSING AND
Interference from the mains (usually 50 Hz or 60 Hz)
FILTERING and other AC sources can also affect the DC
With this operational amplifier, the power supply pins performance. Nonlinear distortion can convert these
(only VDD for single supply) should have a low-ESR signals to multiple tones, including a DC shift in voltage.
ceramic bypass capacitor (i.e., 0.01 µF to 0.1 µF) When the signal is sampled by an ADC, these AC
within 2 mm of the pins for good high-frequency signals can also be aliased to DC, causing an apparent
decoupling. shift in offset.
It is recommended to place a bulk capacitor (i.e., 1 µF To reduce interference:
or larger) within 100 mm of the device to provide large, - Keep traces and wires as short as possible
slow currents. This bulk capacitor can be shared with
- Use shielding
other low-noise analog parts.
- Use ground plane (at least a star ground)
In some cases, high-frequency power supply noise
- Place the input signal source near the DUT
(e.g., switched-mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift; - Use good PCB layout techniques
this noise needs to be filtered. Adding a small resistor - Use a separate power supply filter (bypass
or ferrite bead into the supply connection can be capacitors) for these zero-drift op amps
helpful.
4.3.11.3 Miscellaneous Effects
4.3.11 PCB DESIGN FOR DC PRECISION Keep the resistances seen by the input pins as small
In order to achieve DC precision on the order of ±1 µV, and as near to equal as possible, to minimize bias
many physical errors need to be minimized. The design current-related offsets.
of the Printed Circuit Board (PCB), the wiring and the Make the (trace) capacitances seen by the input pins
thermal environment have a strong impact on the small and equal. This is helpful in minimizing switching
precision achieved. A poor PCB design can easily be glitch-induced offset voltages.
more than 100 times worse than the MCP6V51 op
amps’ specifications. Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
4.3.11.1 PCB Layout conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
Any time two dissimilar metals are joined together, a and insulation in full contact.
temperature-dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This Mechanical stresses can make some capacitor types
effect is used in thermocouples to measure (such as some ceramics) output small voltages. Use
temperature. The following are examples of more appropriate capacitor types in the signal path and
thermojunctions on a PCB: minimize mechanical stresses and vibration.
• Components (resistors, op amps, …) soldered to Humidity can cause electrochemical potential voltages
a copper pad to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias

DS20006136A-page 26  2018 Microchip Technology Inc.

 MCP6V51
4.4 Typical Applications
VDD 0.01C 1 kΩ +5V
4.4.1 LOW-SIDE CURRENT SENSE
R R 100R +
The common-mode input range of the MCP6V51 0.2R - ADC
typically extend 0.3V below ground (VSS), which makes
this amplifier a good choice for Low-side current sense
R R - U1
application especially where operation on higher 0.2R
supply voltages is required. One such example is + MCP6V51
shown in Figure 4-10. Here, the load current (IL)
ranges from 0A to 1.5A, which results in an voltage FIGURE 4-11: Simple Design.
drop across the shunt resistor of 0 to 75 mV. The gain Figure 4-13 shows a higher performance circuit for a
on the MCP6V51 is set to 201 V/V, which gives an Wheatstone bridge signal conditioning design. This
output voltage range of about 0V to +15V. example offers a symmetric, high impedance load to
the bridge with superior CMRR performance. It
maintains this high CMRR by driving the signal
40VDD differentially into the ADC.

Load MCP6V51
U1 40VDD
MCP6V51 200 
IL +
VOUT VDD
RSHUNT - 1 µF
0.05Ω RG
R R
100Ω RF 10 nF 20 k
200 3 k VDD
20 kΩ
R R
CF 8.2 nF 1 µF ADC

200 3 k
FIGURE 4-10: Low-Side Current Sense for 10 nF
20 k
1.5A Max Load Current.
This circuit example can be adapted to a wide range of 1 µF
similar applications:
- for VDD voltages from 4.5V up to 45V
200 
- adjusting the shunt resistor and/or gain for
higher or lower load currents.
MCP6V51
Because the MCP6V51 has a very low offset drift and
virtually no 1/f noise, very small shunt resistor values FIGURE 4-12: Higher Performance Design.
can be selected, which helps in mediating the heating
and size problems that may arise in such applications.

4.4.2 WHEATSTONE BRIDGE

Many sensors are configured as Wheatstone bridges.
Strain gages and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single-ended
and there is a minimum of filtering; the CMRR is good
enough for moderate common mode noise.

 2018 Microchip Technology Inc. DS20006136A-page 27

MCP6V51
4.4.3 RTD SENSOR
The ratiometric circuit in Figure 4-13 conditions a
two-wire RTD for applications with a limited
temperature range. U1 acts as a difference amplifier,
with a low-frequency pole. The sensor’s wiring
resistance (RW) is corrected in firmware. Failure (open)
of the RTD is detected by an out-of-range voltage.

VDD

RT RN
34.8 kΩ 10.0 kΩ 10 nF

RW RF
2 MΩ
U1 +
RRTD
100Ω MCP6V51 -
1 kΩ
RG RF
RW
10.0 kΩ 2 MΩ
100 nF
RB 10 nF +5V
1.0 µF
4.99 kΩ
+
- ADC

FIGURE 4-13: RTD Sensor.

DS20006136A-page 28  2018 Microchip Technology Inc.

 MCP6V51
5.0 DESIGN AIDS 5.3 Application Notes
Microchip provides the basic design aids needed for The following Microchip Application Notes are
the MCP6V51 op amp. available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
5.1 Microchip Advanced Part Selector reference resources.
(MAPS) • ADN003 Application Note – “Select the Right
Operational Amplifier for your Filtering Circuits”
MAPS is a software tool that helps efficiently identify (DS21821)
Microchip devices that fit a particular design
• AN722 Application Note – “Operational Amplifier
requirement. Available at no cost from the Microchip
Topologies and DC Specifications” (DS00722)
web site at www.microchip.com/maps, MAPS is an
overall selection tool for Microchip’s product portfolio • AN723 Application Note – “Operational Amplifier
that includes Analog, Memory, MCUs and DSCs. Using AC Specifications and Applications” (DS00723)
this tool, a customer can define a filter to sort features • AN884 Application Note – “Driving Capacitive
for a parametric search of devices and export Loads With Op Amps” (DS00884)
side-by-side technical comparison reports. Helpful links • AN990 Application Note – “Analog Sensor
are also provided for data sheets, purchase and Conditioning Circuits - An Overview” (DS00990)
sampling of Microchip parts. • AN1177 Application Note – “Op Amp Precision
Design: DC Errors” (DS01177)
5.2 Analog Demonstration and • AN1228 Application Note – “Op Amp Precision
Evaluation Boards Design: Random Noise” (DS01228)
• AN1258 Application Note – “Op Amp Precision
Microchip offers a broad spectrum of Analog
Design: PCB Layout Techniques” (DS01258)
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analog tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 1
(P/N DS51667)
• MCP6XXX Amplifier Evaluation Board 2
(P/N DS51668)
• MCP6XXX Amplifier Evaluation Board 3
(P/N DS51673)
• MCP6XXX Amplifier Evaluation Board 4
(P/N DS51681)
• Active Filter Demo Board Kit (P/N DS51614)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board
(P/N SOIC14EV)

 2018 Microchip Technology Inc. DS20006136A-page 29

MCP6V51
NOTES:

DS20006136A-page 30  2018 Microchip Technology Inc.

 MCP6V51
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

5-Lead SOT-23 Example

AADQY
32256

8-Lead MSOP Example

6V51
832256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2018 Microchip Technology Inc. DS20006136A-page 31

MCP6V51

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

0.20 C 2X
D

e1
A D

E/2
E1/2

E1 E
(DATUM D)
(DATUM A-B)

0.15 C D
2X
NOTE 1 1 2

B NX b
0.20 C A-B D

TOP VIEW

A A2
0.20 C

SEATING PLANE
A
SEE SHEET 2 A1 C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2

DS20006136A-page 32  2018 Microchip Technology Inc.

 MCP6V51

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

T
L
L1

VIEW A-A
SHEET 1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 - 1.30
Standoff A1 - - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 - 0.60
Footprint L1 0.60 REF
Foot Angle I 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

 2018 Microchip Technology Inc. DS20006136A-page 33

MCP6V51

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

5 SILK SCREEN

Z C G

1 2

E
GX

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X5) X 0.60
Contact Pad Length (X5) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]

DS20006136A-page 34  2018 Microchip Technology Inc.

 MCP6V51

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2018 Microchip Technology Inc. DS20006136A-page 35

MCP6V51

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20006136A-page 36  2018 Microchip Technology Inc.

 MCP6V51

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2018 Microchip Technology Inc. DS20006136A-page 37

MCP6V51
NOTES:

DS20006136A-page 38  2018 Microchip Technology Inc.

 MCP6V51
APPENDIX A: REVISION HISTORY

Revision A (December 2018)

• Initial release of this document

 2018 Microchip Technology Inc. DS20006136A-page 39

 MCP6V51
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. [X](1) X /XX

Examples:
Device Tape and Reel Temperature Package a) MCP6V51T-E/OT: 5-Lead SOT-23 package,
Option Range Tape and Reel
b) MCP6V51-E/MS: 8-Lead MSOP package
c) MCP6V51T-E/MS: 8-Lead MSOP package,
Device: MCP6V51: 45V, 2 MHz Zero-Drift Op Amp with EMI Filtering Tape and Reel

Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This
Temperature E = -40C to +125C (Extended) identifier is used for ordering purposes and is
Range: not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Package: OT = 5-Lead Plastic Small Outline Transistor (SOT-23)
MS = 8-Lead Plastic Micro Small Outline Package
(MSOP)

 2018 Microchip Technology Inc. DS20006136A-page 40

MCP6V51
NOTES:

DS20006136A-page 41  2018 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in
headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries.
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
CERTIFIED BY DNV ISBN: 978-1-5224-3968-4

== ISO/TS 16949 ==

 2018 Microchip Technology Inc. DS20006136A-page 42

 Worldwide Sales and Service
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DS20006136A-page 43  2018 Microchip Technology Inc.

08/15/18