BQ25960

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SLUSE08 – FEBRUARY 2021
SLUSE08 – FEBRUARY 2021

BQ25960 I2C Controlled, Single Cell 8-A Switched Cap Parallel Battery Charger with
Integrated Bypass Mode and Dual-Input Selector

1 Features 2 Applications
• 98.1% peak efficiency switched cap parallel • Smartphone
charger supporting 8-A fast charge • Tablet
• Patent pending dual phase switched cap
architecture optimized for highest efficiency
3 Description
– Input voltage is 2x battery voltage The BQ25960 is a 98.1% peak efficiency, 8-A battery
– Output current is 2x of input current charging solution using switch capacitor architecture
– Reduces power loss across input cable for 1-cell Li-ion battery. The switched cap architecture
allows the cable current to be half the charging
• Integrated 5-A Bypass Mode fast charge
current, reducing the cable power loss, and limiting
– 21-mΩ Rdson charging path resistance to temperature rise. The dual-phase architecture
support 5-A input and 5-A output charging increases charging efficiency and reduces the input
current and output cap requirements. When used with a main
• Dual-input power mux controller for source charger such as BQ2561x or BQ2589x, the system
selection during fast charging and USB On-The- enables full charging cycle from trickle charge to
Go (OTG)/ reverse TX Mode termination with low power loss at Constant Current
• Support wide range of input voltage (CC) and Constant Voltage (CV) Mode.
– Up to 12.75-V operational input voltage The BQ25960 supports 5-A Bypass Mode charge
– Maximum 40-V input voltage with optional (previously called battery switch charge) through
external ACFET and 20-V without external internal MOSFETs. The Rdson in Bypass Mode
ACFET charging path is 21 mΩ for high-current operation.
• Parallel charging with synchronized dual BQ25960 The integrated Bypass Mode allows backward
operations for up to 13-A charging current compatibility of 5-V fast charging adapter to charge 1-
• Integrated programmable protection features for cell battery.
safe operation The device supports dual input configuration through
– Input overvoltage protection (BUSOVP) and integrated mux control and driver for external N-FETs.
battery overvoltage protection (BATOVP) It also allows single input with no external N-FET or
– Input overcurrent protection (BUSOCP) and single N-FET.
battery overcurrent protection (BATOCP)
Device Information
– Output overvoltage protection (VOUTOVP)
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
– Input undercurrent protection (BUSUCP) and
BQ25960 DSBGA (36) 2.55 mm x 2.55 mm
input reverse-current protection (BUSRCP) to
detect adapter unplug and prevent boost-back (1) For all available packages, see the orderable addendum at
– Battery and connector temperature monitoring the end of the data sheet.
(TSBAT_FLT and TSBUS_FLT) Phone

– Junction overtemperature protection BQ25960

(Parallel charger)

(TDIE_FLT) SC Phase
#1
VOUT

• Programmable settings for system optimization Adapter

SC Phase
#2

– Interrupts and interrupt masks

SW
Type C Connector

AC/DC VBUS
– ADC readings and configuration
SYSTEM
Type C Connector

VBUS
Converter
Main charger SYS

– Alarm functions for host control D+/D-

D+/D- BAT
Host + PD Controller

• Integrated 16-bit ADC for voltage, current, and CC1/ CC2

PD Controller
Battery

temperature monitoring I2C

AP

Simplified Schematic

An©IMPORTANT
Copyright NOTICEIncorporated
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Table of Contents
1 Features............................................................................1 9.4 Programming............................................................ 29
2 Applications..................................................................... 1 9.5 Register Maps...........................................................32
3 Description.......................................................................1 10 Application and Implementation................................ 61
4 Revision History.............................................................. 2 10.1 Application Information........................................... 61
5 Description (continued).................................................. 3 10.2 Typical Application.................................................. 61
6 Device Comparison Table...............................................4 11 Power Supply Recommendations..............................67
7 Pin Configuration and Functions...................................5 12 Layout...........................................................................68
8 Specifications.................................................................. 7 12.1 Layout Guidelines................................................... 68
8.1 Absolute Maximum Ratings ....................................... 7 12.2 Layout Example...................................................... 68
8.2 ESD Ratings .............................................................. 7 13 Device and Documentation Support..........................69
8.3 Recommended Operating Conditions ........................7 13.1 Device Support....................................................... 69
8.4 Thermal Information ...................................................8 13.2 Documentation Support.......................................... 69
8.5 Electrical Characteristics ............................................8 13.3 Receiving Notification of Documentation Updates..69
8.6 Timing Requirements ............................................... 12 13.4 Support Resources................................................. 69
8.7 Typical Characteristics.............................................. 13 13.5 Trademarks............................................................. 69
9 Detailed Description......................................................15 13.6 Electrostatic Discharge Caution..............................69
9.1 Overview................................................................... 15 13.7 Glossary..................................................................69
9.2 Functional Block Diagram......................................... 16 14 Mechanical, Packaging, and Orderable
9.3 Feature Description...................................................17 Information.................................................................... 70

4 Revision History
DATE REVISION NOTES
February 2021 * Initial release.

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5 Description (continued)
The device integrates all the necessary protection features to support safe charging, including input overvoltage
and overcurrent protection, output overvoltage and overcurrent protection, input undercurrent and reverse-
current protection, temperature sensing for the battery and cable, and junction overtemperature protection in
both Switched Cap and Bypass Mode.
The device includes a 16-bit analog-to-digital converter (ADC) to provide VAC voltage, bus voltage, bus current,
output voltage, battery voltage, battery current, input connector temperature, battery temperature, junction
temperature, and other calculated measurements needed to manage the charging of the battery from the
adapter, or wireless input, or power bank.

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6 Device Comparison Table

Table 6-1. Device Comparison
FUNCTION BQ25960 BQ25970 BQ25968 BQ25980
Package YBG-36 YFF-56 YFF-56 YFF-80
Die size 6.5 mm2 9.5 mm2 9.5 mm2 13.2 mm2
Battery 1 cell 1 cell 1 cell 2 cell
Input MUX control Dual input power MUX Single OVPFET Single OVPFET Dual input power MUX
control control
Bypass Mode Yes No No Yes
Recommended 8-A 8A 8A 6A 8A
charging current

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7 Pin Configuration and Functions

1 2 3 4 5 6

GND CFL1 VOUT CFH1 PMID VBUS

A

B GND CFL1 VOUT CFH1 PMID VBUS

GND CFL2 VOUT CFH2 PMID VBUS

C

/INT SRN_
CDRVH CFL2 VOUT CFH2
D SYNCIN

CDRVL_ TSBAT_ SCL BATN_

VAC2 VAC1
E ADDRMS SYNCOUT SRP

REGN ACDRV2 ACDRV1 TSBUS SDA BATP

F

Figure 7-1. YBG Package - BQ25960 36-Pin DSBGA Top View

Table 7-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
Input FETs Driver Pin 1 - The charge pump output to drive the port #1 input N-channel
MOSFET (ACFET1) and the reverse blocking N-channel MOSFET (RBFET1). ACDRV1
F3 ACDRV1 P voltage becomes 5 V above the common drain connection of the ACFET1 and RBFET1, when
the turn-on condition is met. If ACFET1 and RBFET1 are not used, connect ACDRV1 to
ground.
Input FETs Driver Pin 2 -The charge pump output to drive the port #2 input N-channel
MOSFET (ACFET2) and the reverse blocking N-channel MOSFET (RBFET2). ACDRV2
F2 ACDRV2 P voltage becomes 5 V above the common drain connection of the ACFET2 and RBFET2, when
the turn-on condition is met. If ACFET2 and RBFET2 are not used, connect ACDRV2 to
ground.
Negative input for battery voltage sensing and positive input for battery current
sensing- Connect to negative terminal of battery pack. It is also used for battery current
E6 BATN_SRP AI sensing. Place RSNS (2 mΩ or 5 mΩ) between BATN_SRP and SRN_SYNCIN. Short
BATN_SRP to SRN_SYNCIN together and place 100-Ω series resistance between pin and
negative terminal if RSNS is not being used.
Positive input for battery voltage sensing - Connect to positive terminal of battery pack.
F6 BATP AI
Place 100-Ω series resistance between pin and positive terminal.
Charge pump for gate drive - Connect a 0.22-µF cap between CDRVH and
D1 CDRVH AIO
CDRVL_ADDRMS.
Charge pump for gate drive - Connect a 0.22-µF cap between CDRVH and
E1 CDRVL_ADDRMS AIO CDRVL_ADDRMS. During Power ON Reset (POR), this pin is used to assign the address of
the device and the mode of the device as Standalone, Primary, or Secondary.
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
A4, B4 CFH1 P
and CFL1.
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
C4, D4 CFH2 P
and CFL2.
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
A2, B2 CFL1 P
and CFH1.

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Table 7-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NO. NAME
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
C2, D2 CFL2 P
and CFH2.
Open drain, active low interrupt output - Pull up to voltage with 10-kΩ resistor. Normally
D5 INT DO
high, the device asserts low to report status and faults. INT is pulsed low for tINT.
A1, B1,
GND P Ground return
C1
A5, B5,
PMID P Input to the switched cap power stage -Connect 10-µF cap to PMID.
C5
Charger internal LDO output - Connect a 4.7-µF cap between this pin and GND. When in
F1 REGN AO Primary/Secondary Mode, connect through 1-kΩ resistor to the TSBAT_SYNCOUT and
SRN_SYNCIN pins. Do not use REGN for any other function.
E5 SCL DI I2C interface clock - Pull up to 3.3 V with 10-kΩ resistor.
F5 SDA DIO I2C interface data - Pull up to 3.3 V with 10-kΩ resistor.
Negative input for battery current sensing - Place RSNS (2 mΩ or 5 mΩ) between
SRN_SYNCIN and SRP. Short to SRP and SRN_SYNCIN together if not used. If configured
D6 SRN_SYNCIN AI
as a secondary for dual charger configuration, this pin functions as SYNCIN, and connect to
TSBAT_SYNCOUT of Primary, and connect a 1-kΩ pullup resistor to REGN.
Battery temperature voltage input and Primary Mode SYNCOUT - Requires external
resistor divider, NTC, and voltage reference. See the TSBAT section for choosing the resister
E4 TSBAT_SYNCOUT AI
divider values. If the device is in Primary Mode, connect this pin to SRN_SYNCIN of the
Secondary device.
BUS temperature voltage input - Requires external resistor divider, NTC, and voltage
F4 TSBUS AI
reference. See the TSBUS section for choosing the resister divider values.
A6, B6,
VBUS P Device power input - Connect 1-µF capacitor from VBUS to GND.
C6
A3, B3,
VOUT P Device power output - Connect 22-µF capacitor from VOUT to GND.
C3, D3
E3 VAC1 AI VAC1 input detection - Connected to VBUS if ACFET1 and RBFET1 are not used.
E2 VAC2 AI VAC2 input detection - Connected to VBUS if ACFET2 and RBFET2 are not used.

(1) Type: P = Power , AIO = Analog Input/Output , AI = Analog Input, DO = Digital Output, AO = Analog Output, DIO = Digital Input/Output

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VAC1, VAC2 (converter not switching) –2 40 V
VBUS (converter not switching) –2 20 V
PMID (converter not switching) –0.3 20 V
ACDRV1, ACDRV2 –0.3 30 V
CFL1, CFL2 –0.3 7 V
Voltage CFH1 to VOUT, CFH2 to VOUT –0.3 7 V
VOUT –0.3 7 V
BATP, BATN_SRP –0.3 6 V
INT, SDA, SCL, CDRVL_ADDRMS, SRN_SYNCIN,
–0.3 6 V
TSBAT_SYNCOUT, TSBUS
CDRVH –0.3 20 V
Output Sink Current INT 6 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all V
±250
pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VAC1, VAC2 Input voltage at VAC1 and VAC2 12 V
VBUS Input voltage at VBUS 12 V
PMID Input voltage at PMID 12 V
PMID-CFH1, PMID-CFH2 Voltage across QCH1, QCH2 6 V
CFH1-VOUT, CFH2-VOUT Voltage across QDH1, QDH2 6 V
VOUT-CFL1, VOUT-CFL2 Voltage across QCL1, QCL2 6 V
CFL1, CFL2 Voltage across QDL1, QDL2 6 V
ICHG Charging current 8 A
TA Ambient temperature –40 85 °C
TJ Junction temperature –40 120 °C
CCFLY Effective CFLY capacitance 6.6 20 µF
CVBUS Effective VBUS capacitance 0.2 1 µF
CPMID Effective PMID capacitance 2 10 µF

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8.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
COUT Effective VOUT capacitance 2 10 µF
CREGN Effective REGN capacitance 1 4.7 µF
CDRV Effective DRV capacitance 44 220 nF

8.4 Thermal Information

BQ25960
THERMAL METRIC(1) YBG (DSBGA) UNIT
36 PINS
RθJA Junction-to-ambient thermal resistance (JEDEC(1)) 54.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.2 °C/W
RθJB Junction-to-board thermal resistance 12 °C/W
ΨJT Junction-to-top characterization parameter 0.1 °C/W
ΨJB Junction-to-board characterization parameter 11.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

8.5 Electrical Characteristics

VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
ADC disabled, charge disabled,
VBUS, VAC1, and VAC2 not present, 12 20 µA
VBAT=4V
IQ_BAT Quiescent battery current
ADC enabled (slowest mode), charge
disabled, VBUS, VAC1, and VAC2 480 750 µA
not present, VBAT=4V
ADC disabled, charge disabled,
ACDRV disabled, EN_HIZ=1, VAC1 90 µA
IQ_VAC Quiescent VAC current or VAC2 =8V
ADC enabled, charge disabled,
660 µA
ACDRV enabled, VAC1 or VAC2= 8V
INTERNAL THRESHOLD
VAC rising threshold for active
VVACUVLOZ VAC1 or VAC2 rising 3.24 3.4 3.6 V
I2C, no VOUT, no VBUS
VAC falling threshold for I2C stop
VVACUVLO VAC1 or VAC2 falling 3.05 3.2 3.4 V
working
VAC rising threshold to turn on
VAC1 or VAC2 rising 3.3 3.4 3.5 V
ACFET-RBFET
VVACPRESENT
VAC falling threshold to turn off
VAC1 or VAC2 falling 3.1 3.2 3.3 V
ACFET-RBFET
VBUS rising threshold for active
VVBUSUVLOZ VBUS rising 3.24 3.4 3.6 V
I2C, no VOUT, no VAC
VBUS falling threshold for I2C
VVBUSUVLO VBUS falling 2.65 2.8 2.95 V
stop working
VBUS rising threshold to allow
VBUS rising 3.3 3.4 3.5 V
VVBUSPRESENT user set CHG_EN =1
VBUS falling VBUS falling 3.1 3.2 3.3 V

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8.5 Electrical Characteristics (continued)

VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT rising threshold for active
VVOUTUVLOZ VOUT rising 2.48 2.6 2.72 V
I2C, no VAC, no VBUS
VOUT falling threshold for I2C
VVOUTUVLO VOUT falling 2.25 2.4 2.55 V
stop working
VOUT rising to threshold allow
VOUT rising 3.0 3.1 3.2 V
VVOUTPRESENT user set CHG_EN =1
VOUT falling VOUT falling 2.9 3.0 3.1 V
RESISTANCE
RON_BLK VBUS to PMID resistance VBUS=8V 6.1 10.5 mΩ
RON_CH1 PMID to CFH1 resistance PMID=8V 19.3 26.8 mΩ
RON_DH1 CFH1 to VOUT resistance CFLY=4V 11.4 16.8 mΩ
RON_CL1 VOUT to CFL1 resistance VOUT=4V 11.8 18 mΩ
RON_DL1 CFL1 to GND resistance CFLY=4V 12 18.3 mΩ
RON_CH2 PMID to CFH2 resistance PMID=8V 19.3 26.8 mΩ
RON_DH2 CFH2 to VOUT resistance CFLY=4V 11.4 16.8 mΩ
RON_CL2 VOUT to CFL2 resistance VOUT=4V 11.8 18 mΩ
RON_DL2 CFL2 to GND resistance CFLY=4V 12 18.3 mΩ
RVBUS_PD VBUS pull down resistance 5 kΩ
VAC pull down resistance for
RVAC_PD VAC=10V 125 Ω
both VAC1 and VAC2
PROTECTION AND ALARM THRESHOLD AND ACCURACY
VBATOVP_RANGE Battery over-voltage range 3.491 4.759 V
VBATOVP_STEP Typical battery over-voltage step 9.985 mV
IBATP BATP leakage current 1.2 µA
IBATN BATN leakage current 1 nA
VBATOVP_ACC Battery over-voltage accuracy VBATOVP = 4.390V 4.346 4.390 4.434 V
VOUTOVP_ACC VOUT over-voltage accuracy VOUTOVP= 5V 4.9 5 5.1 V
IBATOCP_RANGE Battery over-current range 2.05 8.7125 A
IBATOCP_STEP Typical battery over-current step 102.5 mA
IBATOCP=6.15A, RSNS=2mΩ
IBATOCP_ACC Battery over-current accuracy 5.842 6.15 6.458 A
TJ = –20°C - 85°C
Switched Cap Mode 7 12.75 V
VBUSOVP_RANGE VBUS over-voltage range
Bypass Mode 3.5 6.5
Switched Cap Mode 50 mV
VBUSOVP_STEP Typical VBUS over-voltage step
Bypass Mode 25 mV
VBUSOVP = 4.45V 4.39 4.45 4.488 V
VBUSOVP_ACC VBUS over-voltage accuracy
VBUSOVP = 9V 8.91 9 9.09 V
VBUS ERRHI rising threshold for
VBUS_ERRHI_RISING_SC switched cap mode stop VOUT=4V 9.6 V
switching
VBUS ERRHI falling threshold
VBUS_ERRHI_FALLING_SC for switched cap mode start VOUT=4V 9.4 V
switching
VBUS ERRHI rising threshold for
VBUS_ERRHI_RISING_BYPASS VOUT=4V 4.8 V
bypass mode stop switching
VBUS ERRHI falling threshold
VBUS_ERRHI_FALLING_BYPASS VOUT=4V 4.68 V
for bypass mode start switching
VVACOVP_RANGE VAC over-voltage range 6.5 18 V

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8.5 Electrical Characteristics (continued)

VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VACOVP=6.5V 6.3 6.5 6.6 V
VVACOVP_ACC VAC over-voltage accuracy VACOVP=10.5V 10.2 10.5 10.7 V
VACOVP=12V 11.7 12 12.2 V
VVACOVP_HYS VACOVP hysteresis 3 %
Switched Cap Mode 1.0175 4.579 A
IBUSOCP_RANGE Input over-current range
Bypass Mode 1.0475 6.809 A
Switched Cap Mode 254 mA
IBUSOCP_STEP Typical input over current step
Bypass Mode 262 mA
IBUSOCP=3.05A, switched cap
mode 2.897 3.05 3.206 A
IBUSOCP_ACC Input over current accuracy TJ = –20°C - 85°C
IBUSOCP=3.14A, bypass mode
2.983 3.14 3.297 A
TJ = –20°C - 85°C
IBUSUCP_ACC Input under-current accuracy BUSUCP=250mA, TJ = –20°C - 85°C 100 250 450 mA
IBUSRCP_ACC Input reverse-current accuracy BUSRCP=300mA, TJ = -20°C - 85°C 150 300 450 mA
TSBUS_FLT_RANGE TSBUS fault % of VREGN range 0 50 %
TSBUS fault % of VREGN step
TSBUS_FLT_STEP 0.1953 %
size
TSBUSFLT_ACC TSBUS fault accuracy TSBUS_FLT=20.12% 18.5 20.12 21.5 %
TSBAT_FLT_RANGE TSBAT fault % of VREGN range 0 50 %
TSBAT fault % of VREGN step
TSBAT_FLT_STEP 0.1953 %
size
TSBAT_FLT_ACC TSBAT voltage accuracy TSBAT_FLT=20.12% 18.5 20.12 21.5 %
TDIE_FLT_RANGE TDIE over-temperature range 80 140 °C
TDIE_FLT_STEP TDIE over-temperature step 20 °C
TDIE over-temperature alarm
TDIE_ALM_RANGE 25 150 °C
range
TDIE over-temperature alarm
TDIE_ALM_STEP 0.5 °C
step
ADC MEASUREMENT PERFORMANCE
ADC_SAMPLE[1:0] = 00 24 ms

Conversion-time, Each ADC_SAMPLE[1:0] = 01 12 ms

tADC_CONV
Measurement ADC_SAMPLE[1:0] = 10 6 ms
ADC_SAMPLE[1:0] = 11 3 ms
ADC_SAMPLE[1:0] = 00 14 15 bit
ADC_SAMPLE[1:0] = 01 13 14 bit
ADCRES Effective Resolution
ADC_SAMPLE[1:0] = 10 12 13 bit
ADC_SAMPLE[1:0] = 11 10 11 bit
ADC MEASUREMENT RANGES AND ACCURACY
IBUSADC_RANGE ADC BUS current range 0 7 A
ADC BUS current LSB Switched Cap Mode 0.9972 mA
IBUSADC_LSB
ADC BUS current LSB Bypass Mode 1.0279 mA
ADC BUS current offset Switched Cap Mode 66 mA
IBUSADC_OFFSET
ADC BUS current offset Bypass Mode 64 mA

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8.5 Electrical Characteristics (continued)

VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IBUS=2A, ADC_SAMPLE[1:0]=00,
1.9 2 2.1 A
TJ = –20°C - 85°C
IBUSADC_ACC ADC BUS current accuracy
IBUS=3A, ADC_SAMPLE[1:0]=00,
2.85 3 3.15 A
TJ = –20°C - 85°C
VBUSADC_RANGE ADC BUS voltage range 0 16.39 V
VBUSADC_LSB ADC BUS voltage LSB 1.002 mV
VBUS=4V, ADC_SAMPLE[1:0]=00 3.96 4 4.04 V
VBUSADC_ACC ADC BUS voltage accuracy
VBUS=8V, ADC_SAMPLE[1:0]=00 7.92 8 8.08 V
VAC1ADC_RANGE ADC VAC1 voltage range 0 14 V
VAC1ADC_STEP ADC VAC1 voltage LSB 1.0008 mV
VAC1ADC_OFFSET ADC VAC1 voltage offset 3 mV
VAC1=4V, ADC_SAMPLE[1:0]=00 3.96 4 4.04 V
VAC1ADC_ACC ADC VAC1 voltage accuracy
VAC1=8V, ADC_SAMPLE[1:0]=00 7.92 8 8.08 V
VAC2ADC_RANGE ADC VAC2 voltage range 0 14 V
VAC2ADC_LSB ADC VAC2 voltage LSB 1.0006 mV
VAC2ADC_OFFSET ADC VAC2 voltage offset 5 mV
VAC2ADC_ACC ADC VAC2 voltage accuracy VAC2=4V, ADC_SAMPLE[1:0]=00 3.96 4 4.04 V
VAC2ADC_ACC ADC VAC2 voltage accuracy VAC2=8V, ADC_SAMPLE[1:0]=00 7.92 8 8.08 V
VBATADC_RANGE ADC BAT voltage range 0 6 V
VBATADC_LSB ADC BAT voltage LSB 1.017 mV
VBATADC_OFFSET ADC BAT voltage offset 1 mV
VBAT=4V, ADC_SAMPLE[1:0]=00 3.96 4 4.04 V
VBATADC_ACC ADC BAT voltage accuracy
VBAT=4.4V, ADC_SAMPLE[1:0]=00 4.356 4.4 4.444 V
VOUTADC_RANGE ADC VOUT voltage range 0 6 V
VOUTADC_LSB ADC VOUT voltage LSB 1.0037 mV
VOUTADC_OFFSET ADC VOUT voltage offset 2 mV
VOUT=4V, ADC_SAMPLE[1:0]=00 3.98 4 4.02 V
VOUTADC_ACC ADC VOUT voltage accuracy
VOUT=4.4V, ADC_SAMPLE[1:0]=00 4.378 4.4 4.422 V
IBATADC_RANGE ADC battery current range -12 12 A
IBATADC_LSB ADC battery current LSB 0.999 mA
IBATADC_OFFSET ADC battery current offset -150 mA
IBAT=4A, ADC_SAMPLE[1:0]=00, TJ
3.92 4.00 4.08 A
ADC battery current accuracy = –20°C - 85°C
IBATADC_ACC_2mOhm
through 2mOhm sense resistor IBAT=6A, ADC_SAMPLE[1:0]=00, TJ
5.88 6.00 6.12 A
= –20°C - 85°C
TSBUSADC_RANGE ADC TSBUS % of VREGN range 0 50 %
ADC TSBUS % of VREGN range
TSBUSADC_STEP 0.0986 %
LSB
ADC TSBUS % of VREGN range
TSBUSADC_OFFSET 0.1 %
offset
TSBUS=20% of VREGN,
TSBUSADC_ACC ADC TSBUS accuracy 19 20 21 %
ADC_SAMPLE[1:0]=00
TSBATADC_RANGE ADC TSBAT % of VREGN range 0 50 %
ADC TSBAT % of VREGN range
TSBATADC_STEP 0.0976 %
LSB
ADC TSBAT % of VREGN range
TSBATADC_OFFSET 0.065 %
offset

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8.5 Electrical Characteristics (continued)

VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSBAT=20% of VREGN,
TSBATADC_ACC ADC TSBAT accuracy 19 20 21 %
ADC_SAMPLE[10]=00
TDIE_ADC_RANGE ADC TDIE range -40 150 °C
TDIE_ADC_STEP ADC TDIE step 0.5079 °C
TDIE_ADC_OFFSET ADC TDIE offset -3.5 °C
REGN LDO
VREGN REGN LDO output voltage VBUS=8V, IREGN=20mA 5.0 V
IREGN REGN LDO current limit VBUS=8V, VREGN=4.5V 40 mA
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA
VIH Pull up rail 1.8V 1.3 V
and SCL
VIL Input low threshold level Pull up rail 1.8V 0.4 V
VOL Output low threshold level Sink current = 5mA 0.4 V
IBIAS High-level leakage current Pull up rail 1.8V 1 µA
LOGIC OUTPUT PIN (INT, TSBAT_SYNCOUT)
Output low threshold level, INT
VOL Sink current = 5mA 0.4 V
pin
High-level leakage current, INT
IOUT Pull up rail 1.8V 1 µA
pin
LOGIC INPUT PIN (SRN_SYNCIN)
Input high threshold level,
VIH_SRN_SYNCIN 1.3 V
SRN_SYNCIN
Input low threshold level,
VIL_SRN_SYNCIN 0.4 V
SRN_SYNCIN
IIN_SRN_SYNCIN High level leakage current Pull-up rail 1.8V 1 µA

8.6 Timing Requirements

MIN NOM MAX UNIT
TIMINGS
tVACOVP VAC OVP response time 100 ns
tBATOCP IBAT OCP response time 640 µs
tINT Duration that INT is pulled low when an event occurs 256 µs
tALM_DEBOUNCE Time between consecutive faults for ALM indication 120 ms
I2C INTERFACE
fSCL SCL clock frequency 1000 kHz

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8.7 Typical Characteristics

Typical characteristics are taken with the BMS041 for switching test and GRM188R61C226M is used as CFLY.

97.75 2.4
2.2
97.25
2
96.75
1.8
96.25 1.6

Power loss (W)

Efficiency (%)

1.4
95.75
1.2
95.25
1
94.75 0.8
0.6
94.25
0.4
93.75
0.2
93.25 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Charge current (A) Charge current (A)

VBAT = 4.0 V, FSW = 500 kHz VBAT = 4.0 V, FSW = 500 kHz

Figure 8-1. Battery Charge Efficiency vs. Charge Current, 1 x Figure 8-2. Battery Charge Power Loss vs. Charge Current, 1 x
22-µF CFLY per Phase Switching Frequency 22-µF CFLY per Phase Switching Frequency
1.8
98
1.6
97.6
1.4
97.2
1.2
Power loss (W)
Efficiency (%)

96.8
1
96.4
0.8
96
0.6
95.6
0.4
95.2 0.2
94.8 0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5
Charge current (A) Charge current (A)
VBAT = 4.0 V, FSW = 500 kHz VBAT = 4.0 V, FSW = 500 kHz

Figure 8-3. Battery Charge Efficiency vs. Charge Current, 2 x Figure 8-4. Battery Charge Power Loss vs. Charge Current, 2 x
22-µF CFLY per Phase 22-µF CFLY per Phase

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8.7 Typical Characteristics (continued)

Typical characteristics are taken with the BMS041 for switching test and GRM188R61C226M is used as CFLY.
98.2
1.6
98
97.8 1.4
97.6
97.4 1.2

Power loss (W)

97.2
Efficiency (%)

1
97
96.8 0.8
96.6
96.4 0.6
96.2
0.4
96
95.8 0.2
95.6
95.4 0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5
Charge current (A) Charge current (A)

VBAT = 4.0 V, FSW = 500 kHz VBAT = 4.0 V, FSW = 500 kHz

Figure 8-5. Battery Charge Efficiency vs. Charge Current, 3 x Figure 8-6. Battery Charge Power Loss vs. Charge Current, 3 x
22-µF CFLY per Phase 22-µF CFLY per Phase

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9 Detailed Description
9.1 Overview
The BQ25960 is a 98.1% peak efficiency, 8-A battery charging solution using a switched cap architecture for 1-
cell Li-ion battery. This architecture allows the cable current to be half the charging current, reducing the cable
power loss, and limiting temperature rise. The dual-phase architecture increases charging efficiency and reduces
the input and output cap requirements. When used with a main charger such as BQ2561x or BQ2589x, the
system the system enables full charging cycle from trickle charge to termination with low power loss at Constant
Current (CC) and Constant Voltage (CV) mode.
The device also operates in bypass mode charging the battery directly from VBUS through QB, QCH1 and
QDH1 in parallel with QCH2 and QDH2. The impedance in bypass mode is limited to 21 mΩ for 5-A charging
current.
The device supports dual input power path management which manages the power flowing from two different
input sources. The inputs selection is controlled by host through I2C with default source #1 as the primary input
and the source #2 as the secondary source.
The device integrates all the necessary protection features to ensure safe charging, including input overvoltage
and overcurrent protection, output overvoltage and overcurrent protection, temperature sensing for the battery
and cable, and monitoring the die temperature.
The device includes a 16-bit ADC to provide bus voltage, bus current, output voltage, battery voltage, battery
current, input connector temperature, battery temperature, junction temperature, and other calculated
measurements needed to manage the charging of the battery from the smart wall adapter or wireless input or
power bank.

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9.2 Functional Block Diagram

VVBUSUVLOZ
+ UVLO
BQ25960
Block Diagram
+
VVBUSOVP REGN REGN
VBUSOVP EN_HIZ LDO REGN

CDRVH
QB CDRVL_ADDRMS
IBUS
VBUS PMID

ACDRV1
QCH1 QCH2
ACDRV2
Switched CFH2
VAC1 Cap
INPUT Control CFH1
VAC2 SELECTOR
QDH1 QDH2

VOUT
Digital Core,
SDA I2C Control
and System
QCL1 QCL2
Feedback to HOST
SCL SYNCOUT
CFL2
SYNCIN CFL1
INT
QDL1 QDL2

TSBUS TSBUS_FLT
+ GND
VBUS_ADC VBAT_ADC

TSBAT_SYNCOUT + VAC1_ADC IBAT_ADC BATP

TSBAT_FLT VAC2_ADC TSBUS_ADC
ADC
IBUS_ADC TSBAT_ADC
TDIE_ADC
SYNCOUT VOUT_ADC BATN_SRP
+
VBUS + +
VBATOVP
VBUSOVP
SRN_SYNCIN
+
IBUS + +
Protection IBATOCP
IBUSOCP

IBUSUCP + + VOUT

IBUS VOUTOVP SYNCIN

IBUS + + IC_TJ
IBUSRCP TDIE_FTL

VAC1 + + VAC2
VAC1OVP VAC2OVP

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9.3 Feature Description

9.3.1 Charging System
BQ25960 is a single-cell high efficiency switched cap charger, used in parallel with a switching mode charger. A
host must set up the protections and alarms on BQ25960 prior to enabling the BQ25960. The host must monitor
the alarms generated by BQ25960 and communicate with the smart adapter to control the current delivered to
the charger.
Phone

BQ25960
(Parallel charger)

VOUT
SC Phase
#1

SC Phase
Adapter #2

SW
Type C Connector

AC/DC VBUS SYSTEM

Type C Connector

VBUS
Converter
Main charger SYS

D+/D-
D+/D- BAT
Host + PD Controller
CC1/ CC2
PD Controller

Battery
I2C

AP

Figure 9-1. BQ25960 System Diagram

9.3.2 Battery Charging Profile

The system will have a specific battery charging profile that is unique due to the switched cap architecture. The
charging will be controlled by the main charger such as the BQ2561x or BQ2589x until ystem voltage reaches
minimum system regulation voltage VSYSMIN. Once the battery voltage reaches VSYSMIN (3.5 V), the adapter can
negotiate for a higher bus voltage, enable BQ25960 charging, and regulate the current on VBUS to charge the
battery. In the CC phase, the protection in BQ25960 will not regulate the battery voltage, but will provide
feedback to the system to increase and decrease current as needed, as well as disable the blocking and
switching FETs if the voltage is exceeded. Once the CV point is reached, the BQ25960 will provide feedback to
the adapter to reduce the current, effectively tapering the current until a point where the main charger takes over
again. The BQ25960 can operate as long as input current is above the BUSUCP threshold.

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8A
Note: Current and Voltage steps are exaggerated for
example only ± actual current steps are much
7A smaller

BATOVP
6A BATOVP_ALM
Battery Current
Charge Current (A)

5A Battery Voltage
Cable Current

Battery Voltage (V)

4A
3.5V

3A 3.5

2A

3.0
1A 3.0V
Pre-Charge

Pre-Charge CC CC CV CV
Main charger Main charger BQ25960 BQ25960 Main charger
T1 T2 T3 T4 T5

Figure 9-2. BQ25960 System Charging Profile

9.3.3 Device Power Up

The device is powered from the higher of VAC1 or VAC2 (with VAC1 being primary input), VBUS or VOUT
(battery). The voltage must be greater than the VVACUVLOZ, VVBUSUVLOZ or VVOUTUVLOZ threshold to be a valid
supply. When VAC1 or VAC2 rises above VVACUVLOZ or VBUS rises above VVBUSUVLOZ or VOUT rises above
VVOUTUVLOZ, I2C interface is ready for communication and all the registers are reset to default value. The host
needs to wait VBUSPRESENT_STAT and VOUTPRESENT_STAT go high before setting CHG_EN =1 and start
charging.
9.3.4 Device HIZ State
The device enters HIZ mode when EN_HIZ bit is set to '1'. When device is in HIZ mode, the converter stops
switching, ADC stops converting, ACDRV is turned off and REGN LDO is forced off even when the adapter is
present and no fault condition is present. The device exits HIZ Mode when EN_HIZ is set to '0' by host or device
POR.
The faults conditions force the converter stop switching and clear CHG_EN bit, but keep REGN on and EN_HIZ
bit = 0. More details can be found in the Device Protection section.
9.3.5 Dual Input Bi-Directional Power Path Management
The device has two ACDRV pins to drive two sets of N-channel ACFET-RBFET, which select and manage the
input power from two different input sources. In the POR sequence, the device detects if the ACFET-RBFET is
populated based on if ACDRV pin is shorted to ground or not, and then updates the status register
ACRB1_CONFIG_STAT or ACRB2_CONFIG_STAT to indicate the presence of ACFET-RBFET. If the external
ACFET-RBFET is not populated in the schematic, then tie VAC to VBUS and connect ACDRV to GND. The
device supports:
1. single input without external FET
2. single input with one single ACFET
3. dual input with one set of ACFET-RBFET
4. dual input with two sets of ACFET-RBFET
The power-up sequences for different applications are described in detail below.

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9.3.5.1 ACDRV Turn-On Condition

The ACDRV controls input power MUX for both BQ25960 and main charger. In order to turn the ACDRV, all of
the following conditions must be valid:
1. The corresponding AC-RB FET is populated: VAC is not short to VBUS and ACDRV is not short to ground
2. VAC is above VVACpresent threshold
3. VAC is below VVACOVP threshold
4. DIS_ACDRV_BOTH is not set to '1'
5. EN_HIZ is not set to '1'
6. VBUS is below VVBUSpresent threshold
9.3.5.2 Single Input from VAC to VBUS without ACFET-RBFET
In this scenario, VAC1 and VAC2 are both shorted to VBUS, ACDRV1 and ACDRV2 are pulled down to ground.
The table below summarizes the VAC1/VAC2, ACDRV1/ACDRV2 connection, register control, and status
functions.
Table 9-1. Single Input without External FET Summary
INPUT CONFIGURATION SINGLE INPUT
External FET connection No external FET
Input pin connection VAC1 and VAC2 short to VBUS
ACDRV pin connection ACDRV1 and ACDRV2 short to ground
ACDRV1_STAT 0
ACDRV2_STAT 0
DIS_ACDRV_BOTH 1
ACRB1_CONFIG_STAT 0
ACRB2_CONFIG_STAT 0
EN_HIZ No impact on ACDRV

ACDRV2 VAC2

Adapter VBUS PMID

QB
VAC1

ACDRV1
BQ25960

Figure 9-3. Single input without ACFET-RBFET

9.3.5.3 Single Input with ACFET1

In this scenario, ACFET1 without RBFET1 is populated, but ACFET2-RBFET2 is not. VAC2 is short to VBUS
and ACDRV2 is pulled down to ground. The table below summarizes the VAC1/ VAC2, ACDRV1/ACDRV2
connection, register control, and status functions. Use VAC1 for single input configuration.
Table 9-2. Single Input with Single ACFET1
INPUT CONFIGURATION SINGLE INPUT
External FET connection ACFET1, no ACFET2-RBFET2
Input pin connection VAC1 connected to input source
VAC2 short to VBUS
ACDRV pin connection ACDRV1 active
ACDRV2 tie to ground

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Table 9-2. Single Input with Single ACFET1 (continued)

INPUT CONFIGURATION SINGLE INPUT
ACDRV1_STAT 1: ACDRV1 is ON
0: ACDRV1 is OFF
ACDRV2_STAT 0
DIS_ACDRV_BOTH 0: Allow ACDRV1 to turn on if the conditions of ACDRV turn on are met.
1: Force ACDRV1 OFF
ACRB1_CONFIG_STAT 1
ACRB2_CONFIG_STAT 0
EN_HIZ 0: Allow ACDRV1 to turn on if the conditions of ACDRV turn on are met.
1: Force ACDRV1 OFF

ACDRV2 VAC2
ACFET1
Adapter PMID
VBUS

QB
ACDRV1

VAC1
BQ25960

Figure 9-4. Single Input with ACFET1

9.3.5.4 Dual Input with ACFET1-RBFET1

In this scenario, ACFET1-RBFET1 is populated, but ACFET2-RBFET2 is not. VAC2 is short to VBUS and
ACDRV2 is pulled down to ground. The table below summarizes the connection, register control and status
functions. Use VAC1 for adapter input and VBUS for wireless input.
Table 9-3. Dual Input with ACFET1-RBFET1
INPUT CONFIGURATION DUAL INPUT
External FET connection ACFET1-RBFET1, no ACFET2-RBFET2
Input pin connection VAC1 connected to input source 1
VAC2 short to VBUS
ACDRV pin connection ACDRV1 active
ACDRV2 short to ground
ACDRV1_STAT 0: ACDRV1 OFF
1: ACDRV1 ON
ACDRV2_STAT 0
DIS_ACDRV_BOTH 0: Allow ACDRV1 to turn on if other conditions of ACDRV turn on are met
1: Force ACDRV1 OFF
ACRB1_CONFIG_STAT 1
ACRB2_CONFIG_STAT 0
EN_HIZ 0: Allow ACDRV1 to turn on if other conditions of ACDRV turn on are met
1: Force ACDRV1 OFF

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ACDRV2 VAC2
Wireless VBUS
PMID

QB
Adapter ACDRV1

VAC1 BQ25960
ACFET1 RBFET1

Figure 9-5. Dual Input with ACFET-RBFET1

9.3.5.5 Dual Input with ACFET1-RBFET1 and ACFET2-RBFET2

In this scenario, both ACFET1-RBFET1 and ACFET2-RBFET2 are populated and the device supports dual
input. The table below summarizes the connection, register control and status functions. Connect input with high
OVP threshold to VAC1.
Table 9-4. Dual Input with Both ACFET1-RBFET1 and ACFET2-RBFET2 Summary
INPUT CONFIGURATION DUAL INPUT
External FET connection ACFET1-RBFET1, ACFET1-RBFET2
Input pin connection VAC1 connected to input source 1
VAC2 connected to input source 2
No input source allowed to connect to VBUS
ACDRV pin connection ACDRV1 and ACDRV2 active
ACDRV1_STAT 0: ACDRV1 OFF
1: ACDRV1 ON
Once device is in dual input configuration with ACFET1-RBFET1 and ACFET2-RBFET2, the
host can use this bit to swap the input between VAC1 and VAC2 if both VAC1 and VAC2 are
valid.
ACDRV2_STAT 0: ACDRV2 OFF
1: ACDRV2 ON
Once device is in dual input configuration with ACFET1-RBFET1 and ACFET2-RBFET2, the
host can use this bit to swap the input between VAC1 and VAC2 if both VAC1 and VAC2 are
valid.
DIS_ACDRV_BOTH 0: Allow ACDRV to turn on. By default, ACDRV1 is turned on if the conditions of ACDRV turn
on are met, ACDRV1_STAT=1 and ACDRV2_STAT =0. In On-The-GO (OTG) or Reverse TX
Mode, refer to OTG and Reverse TX Mode Operation session for turn on precedence.
1: Force both ACDRV to turn off, both ACDRV1_STAT and ACDRV2_STAT become 0.
ACRB1_CONFIG_STAT 1
ACRB2_CONFIG_STAT 1
EN_HIZ 0: Allow ACDRV to turn on for the port w/ VAC present if the conditions of ACDRV turn on
are met.
ACDRV1 is turned on since VAC1 is the primary input source when both VAC1 and VAC2
present and the turn on conditions are met.
1: Turns off both ACDRV

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ACDRV2 VAC2
ACFET2 RBFET2
Wireless VBUS PMID

QB

Adapter ACDRV1

VAC1
ACFET1 RBFET1

BQ25960

Figure 9-6. Two Inputs with ACFET-RBFET1 and ACFET-RBFET2

9.3.5.6 OTG and Reverse TX Mode Operation

When the main charger is in OTG or reverse TX Mode, the input power MUX (ACFET-RBFET) also controls
which port is desired for OTG output.
To enter OTG or reverse TX Mode, the host should follow the steps below:
1. Host writes EN_OTG =1
2. BQ25960 sets DIS_ACDRV_BOTH =1
3. Host writes DIS_ACDRV_BOTH=0, and then writes ACDRV1_STAT=1 or ACDRV2_STAT=1 depending on
which port is desired for OTG or reverse TX output
4. Host enables OTG Mode on main charger
5. If VBUSOVP or VACOVP fault occurs, ACDRV will be disabled but EN_OTG is still '1'. Host needs to write
ACDRV1_STAT high or ACDRV2_STAT high when the fault is cleared. Set VAC1OVP and VAC2OVP to the
same threshold in the OTG Mode
6. EN_OTG is cleared when watchdog timer expires
To exit OTG or Reverse TX Mode, the host should follow the steps below:
1. Turn off main OTG or reverse TX source
2. Turn on VBUS pulldown resistor (RVBUS_PD) by setting BUS_PD_EN=1 or VAC pulldown resistor RVAC_PD by
setting VAC1_PD_EN=1 or VAC2_PD_EN=1, depending on which port is to be discharged
3. Wait for VBUS and VAC to be discharged
4. Turn off ACDRV by setting ACDRV1_STAT=0 or ACDRV2_STAT=0
5. Exit OTG Mode by setting EN_OTG=0
9.3.6 Bypass Mode Operation
When host determines the adapter support bypass mode charging, the device can enable Bypass mode by
setting EN_BYPASS=1. Blocking FET (QB) and four high side switching FET (QCH1 and QDH1/ QCH2 and
QDH2) are turned on to charge from adapter to battery. During Bypass Mode, when fault occurs, CHG_EN is
cleared but EN_BYPASS stays ‘1’.

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ACDRV2 VAC2
Adapter VBUS
BQ25960

Wireless
SDA
ACDRV1
QB Digital
VAC1
Core SCL Host
PMID /INT

QCH1 QCH2
CFH1 CFH2

CFLY1 QDH1 QDH2 CFLY2

VOUT

QCL1 QCL2
CFL1 CFL2

QDL1 QDL2
GND

Battery
Figure 9-7. BQ25960 Bypass Mode

To change from Bypass Mode to Switched Cap Mode or from Switched Cap to Bypass Mode, the host would first
set CHG_EN=0 to stop the converter and then set EN_BYPASS to desired value. The host sets desired
protection threshold based on the selected operation modes and then host enables charge by setting
CHG_EN=1.
9.3.7 Charging Start-Up
The host can start Switched Cap or Bypass Mode charging follow the steps below:
1. Both VBUS and VOUT need to be present. Host can check the status through VBUSPRESENT_STAT
(REG15[2]) and VOUTPRSENT_STAT (REG15[5]). Both of them need to be '1'.
2. Host sets all the protections to the desired thresholds. Refer to the Device Modes and Protection Status
section for proper setting.
3. Host sets either Switched Cap Mode or Bypass Mode through EN_BYPASS bit (REG0F[3]) based on adapter
type.
4. Host sets the desired switching frequency in Switched Cap Mode through FSW_SET [2:0] bits (REG10[7:5]).
5. Host sets BUS under current protection (BUSUCP) to 250 mA though BUSUCP bit (REG05[6])=1
6. Host sets charger configuration bits: CHG_CONFIG_1 (REG05[3])=1.
7. Host can enable charge by setting CHG_EN=1.
8. Once charge has been enabled, the CONV_ACTIVE_STAT bit is set to '1' to indicate either switched cap or
bypass is active, and current starts to flow to the battery.
9. When watchdog timer expires, CHG_EN is reset to '0' and charging stops. Host needs to read or write any
register bit before watchdog expires, or disable watchdog timer (set REG10[2]=1) to prevent watchdog timer
from expiring.
9.3.8 Adapter Removal
If adapter is removed during soft start timer, CHG_EN will be cleared after soft-start timer expires. The user can
program the soft-start timer in SS_TIMEOUT register. If adapter is removed after soft-start timer expires,
converter stops switching and CHG_EN is cleared after the deglitch time programmed in

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IBUSUCP_FALL_DG_SEL register. The device prevents boost back when the adapter is removed during and
after the soft-start timer. To accelerate VBUS or VAC discharge after adapter removal, the user to turn on the
VBUS pulldown resistor (RVBUS_PD) and VAC pulldown current resistor (RVAC_PD) by setting BUS_PD_EN or
VAC1_PD_EN or VAC2_PD_EN to '1'.
9.3.9 Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
The integrated 16-bit ADC of the device allows the user to get critical system information for optimizing the
behavior of the charger control. The control of the ADC is done through the ADC control register. The ADC_EN
bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous
conversion or one-shot behavior. The ADC_AVG bit enables or disables (default) averaging. ADC_AVG_INIT
starts average using the existing (default) or using a new ADC value.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if the VVAC>VVACPRESENT,
VVBUS>VVBUSPRESENT or VVOUT>VVOUTPRESENT is valid. If ADC_EN is set to ‘1’ before VAC, VBUS or VOUT
reach their respective PRESENT threshold, then the ADC conversion will be postponed until one of the power
supplies reaches the threshold.
The ADC_SAMPLE bits control the sample speed of the ADC, with conversion times of tADC_CONV. The
integrated ADC has two rate conversion options: a 1-shot mode and a continuous conversion mode set by the
ADC_RATE bit. By default, all ADC parameters will be converted in 1-shot or continuous conversion mode
unless disabled in the ADC CONTROL 1 and ADC_CONTROL 2 register. If an ADC parameter is disabled by
setting the corresponding bit in the ADC CONTROL 1 and ADC_CONTROL 2 register, then the value in that
register will be from the last valid ADC conversion or the default POR value (all zeros if no conversions have
taken place). If an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish
the conversion of that parameter, but will not convert the parameter starting the next conversion cycle. Even
though no conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is
active and ready to begin conversion as soon as one of the bits in the ADC CONTROL 1 and ADC_CONTROL 2
register is set to ‘0’.
The ADC_DONE_* bits signal when a conversion is complete in 1-shot mode only. During continuous conversion
mode, the ADC_DONE_* bits have no meaning and will be ‘0’.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set
ADC_EN = ‘0’ to disable the ADC. ADC readings are only valid for DC states and not for transients. When host
writes ADC_EN=0, the ADC stops immediately. If the host wants to exit ADC more gracefully, it is possible to do
either of the following:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Write all the DIS bits low, and the ADC will stop at the end of the current measurement.
When external sense resistor (RSNS) is placed and IBATADC is used, it is recommended to use 375-kHz
switching frequency.
9.3.10 Device Modes and Protection Status
Table 9-5 shows the features and modes of the device depending on the conditions of the device.
Table 9-5. Device Modes and Protection Status
STATE
BATTERY ONLY VAC1/
VAC2/ VBUS NOT INPUT PRESENT INPUT PRESENT INPUT PRESENT
FUNCTIONS AVAILABLE
PRESENT
DURING SOFTSTART AFTER SOFTSTART
CHARGE DISABLED
TIMER TIMER
I2C allowed X X X X
ADC X X X X
ACDRV gate drive X X X

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Table 9-5. Device Modes and Protection Status (continued)

STATE
BATTERY ONLY VAC1/
VAC2/ VBUS NOT INPUT PRESENT INPUT PRESENT INPUT PRESENT
FUNCTIONS AVAILABLE
PRESENT
DURING SOFTSTART AFTER SOFTSTART
CHARGE DISABLED
TIMER TIMER
VACOVP X X X
TDIE_ALM X X X
TDIE_TFL X X X
BUSOVP_ALM X X
BUSOCP_ALM X X
BATOVP_ALM X X
BATOCP_ALM X X
BATUCP_ALM X X
VOUTOVP X X X
TSBUS_FLT X X X
TSBAT_ FLT X X X
BUSOVP X X X
BATOVP X X X
BATOCP X X
BUSOCP X X
BUSUCP X
BUSRCP X X

Tripping any of these protections causes QB to be off and converter stops switching. Masking the fault or alarm
does NOT disable the protection, but only keeps an INT from being triggered by the event. Disabling the fault or
alarm protection other than BUSUCP holds that STAT and FLAG bits in reset, and also prevents an interrupt
from occurring. Disable BUSUCP protection still sets STAT and FLAT bits and sends interrupt to alert host but
keeps converter running when triggered.
When any OVP, OCP, RCP or overtemperature fault event is triggered, the CHG_EN bit is set to ‘0’ to disable
charging, and the charging start-up sequence must be followed to begin charging again.
9.3.10.1 Input Overvoltage, Overcurrent, Undercurrent, Reverse-Current and Short-Circuit Protection
Input overvoltage protection with external single or back-to-back N-channel FET(s): The device integrates
the functionality of an input overvoltage protector. With external single or back-to-back N-channel FET(s), the
device blocks high input voltage exceeding VACOVP threshold (VAC1OVP or VAC2OVP). This eliminates the
need for a separate OVP device to protect the overall system. The integrated VACOVP feature has a response
time of tVACOVP (the actual time to turn off external FET(s) will be longer and depends upon the FET(s) gate
capacitance). The VAC1OVP and VAC2OVP setting is adjustable in the VAC control register. The part allows the
user to have different VAC1OVP and VAC2OVP settings. Always put the high VACOVP threshold input to VAC1.
When VAC1OVP or VAC2OVP is tripped, corresponding ACDRV is turned off and VAC1OVP_STAT or
VAC2OVP_STAT and VAC1OVP_FLAG or VAC2OVP_FLAG is set to ‘1’, and INT is asserted low to alert the
host (unless masked by VAC1OVP_MASK or VAC2OVP_MASK). When VAC2OVP is triggered, the device
sends multiple interrupts when the fault persists. Use VAC1 as input unless both VAC1 and VAC2 are needed.
Input overvoltage protection (BUSOVP): The BUSOVP threshold is adjustable in the BUSOVP register. When
BUSOVP is tripped, switched cap or bypass mode is disabled and CHG_EN is set to ‘0’. BUSOVP_STAT and
BUSOVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSOVP_MASK). The
start-up sequence must be followed to resume charging.

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Input overcurrent protection (BUSOCP): Input overcurrent protection monitors the current flow into VBUS.
The overcurrent protection threshold is adjustable in the BUSOCP register. When BUSOCP is tripped, Switched
Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSOCP_STAT and BUSOCP_FLAG is set to ‘1’,
and INT is asserted low to alert the host (unless masked by BUSOCP_MASK). The start-up sequence must be
followed to resume charging.
Input undercurrent protection (BUSUCP): BUS undercurrent protection (UCP) is implemented to detect
adapter unplug. Set BUSUCP =1 (REG05[6]) before enable charge. When BUSUCP is enabled
(BUSUCP_DIS=0), if the current is below BUSUCP after soft start timer (programmable in SS_TIMEOUT[2:0])
expires, Switched Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSUCP_STAT and
BUSUCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSUCP_MASK). The
start-up sequence must be followed to resume charging. The deglitch time for BUSUCP is programmable in
IBUSUCP_FALL_DG_SET[1:0] register. Please note that BUSUCP deglitch time needs to be set shorter than
soft start timer in order for BUSUCP to be effective.
When BUSUCP is disabled (BUSUCP_DIS=1), if the current is below BUSUCP after soft-start timer expires,
CHG_EN is not set to ‘0’, BUSUCP_STAT and BUSUCP_FLAG is set to ‘1’, and INT is asserted low to alert the
host (unless masked by BUSUCP_MASK). The host can determine if charge needs to be stopped in this case.
Input reverse-current protection (BUSRCP): The device monitors the current flow from VBUS to VBAT to
ensure there is no reverse current (current flow from VBAT to VBUS). In an event that a reverse current flow is
detected when BUSRCP_DIS is set to ‘0’, the Switched Cap or Bypass is disabled and CHG_EN is set to ‘0’.
The start-up sequence must be followed to resume charging. To disable BUSRCP, set REG05[1:0] to '00' and
then set BUSRCP_DIS=1.
RCP is always active when converter is switching and BUSRCP_DIS is set to '0'. When RCP is tripped,
BUSRCP_STAT and BUSRCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by
BUSRCP_MASK).
Input overvoltage and overcurrent protection alarm (BUSOVP_ALM and BUSOCP_ALM): In addition to
input overvoltage and overcurrent, the device also integrates alarm function BUSOVP_ALM and BUSOCP_ALM.
When alarm is triggered, the corresponding STAT and FLAG bit is set to ‘1’ and INT is asserted low to alert the
host (unless it is masked by the MASK bit). However, CHG_EN is not cleared and host can reduce input voltage
or input current to prevent VBUS reaching VBUSOVP threshold or IBUS reaching IBUSOCP threshold.
VBUS_ERRHI: the device monitors VBUS to VOUT voltage ratio. If VBUS/VOUT is greater than
VBUS_ERRHI_RISING threshold, the converter does not switch but CHG_EN is kept at '1'. The converter
automatically starts switching when the VBUS/VOUT drops below VBUS_ERRHI_FALLING threshold.
9.3.10.2 Battery Overvoltage and Overcurrent Protection
BATOVP and BATOVP_ALM: The device integrates both overcurrent and overvoltage protection for the battery.
The device monitors the battery voltage on BATP and BATN_SRP. In order to reduce the possibility of battery
terminal shorts during manufacturing, 100-Ω series resistors on BATP is required. If external sense resistor is not
used, place 100-Ω series resistors on BATN as well. The device is intended to be operated within the window
formed by the BATOVP and BATOVP_ALM. When the BATOVP_ALM is reached, an interrupt is sent to the host
to reduce the charge current and thereby not reaching the BATOVP threshold. If BATOVP is reached, the
switched cap or bypass is disabled and CHG_EN is set to ‘0’, and the start-up sequence must be followed to
resume charging. At the same time, BATOVP_STAT and BATOVP_FLAG are set to ‘1’, and INT is asserted low
to alert the host (unless masked by BATOVP_MASK). BATOVP and BATOVP_ALM is disabled when
BATOVP_DIS and BATOVP_ALM_DIS is set to ‘1’.
BATOCP and BATOCP_ALM: The device monitors current through the battery by monitoring the voltage across
the external series battery sense resistor. The differential voltage of this sense resistor is measured on
BATN_SRP and SRN_SYNCIN. The device is intended to be operated within the window formed by the
BATOCP and BATOCP_ALM. When the BATOCP_ALM is reached, an interrupt is sent to the host to reduce the
charge current from reaching the BATOCP threshold. If BATOCP is reached, the Switched Cap or Bypass is
disabled after a deglitch time of tBATOCP and CHG_EN is set to ‘0’, and the start-up sequence must be followed
to resume charging. At the same time, BATOCP_STAT and BATOCP_FLAG are set to ‘1’, and INT is asserted

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low to alert the host (unless masked by BATOCP_MASK). BATOCP and BATOCP_ALM is disabled when
BATOCP_DIS and BATOCP_ALM_DIS is set to ‘1’.
VOUTOVP: The device also monitors output voltage between VOUT and ground in case of battery removal to
protect the system. If VOUTOVP is reached and VOUTOVP_DIS=0, the Switched Cap or Bypass is disabled and
CHG_EN is set to ‘0’, and the start-up sequence must be followed to resume charging. At the same time,
VOUTOVP_STAT and VOUTOVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked
by VOUTOVP_MASK). If VOUTOVP_DIS =1, the protection is disabled.

9.3.10.3 IC Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring

The device has three temperature sensing mechanisms to protect the device and system during charging:
1. TSBUS for monitoring the cable connector temperature
2. TSBAT for monitoring the battery temperature
3. TDIE for monitoring the internal junction temperature of the device
The TSBUS and TSBAT both rely on a resistor divider that has an external pullup voltage to REGN. Place a
negative coefficient thermistor (NTC) in parallel to the low-side resistor. A fault on the TSBUS and TSBAT pin is
triggered on the falling edge of the voltage threshold, signifying a “hot” temperature. The threshold is adjusted
using the TSBUS_FLT and TSBAT_FLT registers.
The typical TS resistor network on TSBAT_SYNCOUT is illustrated in Figure 9-8. The resistor network on
TSBUS is the same.

REGN
RHI

TSBAT_SYNCOUT
RLO

RNTC

BQ25960

Figure 9-8. TSBAT_SYNCOUT Resistor Network

The RLO and RHI resistors should be chosen depending on the NTC used. If a 10-kΩ NTC is used, use 10-kΩ
resistors for RLO and RHI. If a 100-kΩ NTC is used, use 100-kΩ resistors for RLO and RHI. The ratio of VTS/
REGN can be from 0% to 50%, and the voltage at the TS pin is determined by the following equation.

1
1 1
( + )
65$75 KN 65$#6 (8) = 406% 4.1 × 84')0
1
4*+ + 1 1
( + )
406% 4.1 (1)

The percentage of the TS pin voltage is determined by the following equation.

1
1 1
( + )
65$75 KN 65$#6 (%) = 406% 4.1
1
4*+ + 1 1
( + )
406% 4.1 (2)

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Additionally, the device measures internal junction temperature, with adjustable threshold TDIE_FLT in
TDIE_FLT register.
If the TSBUS_FLT, TSBAT_FLT, and TDIE_FLT thresholds are reached, the Switched Cap or Bypass Mode is
disabled and CHG_EN is set to ‘0’, and the start-up sequence must be followed to resume charging. The
corresponding STAT and FLAG bit is set to ‘1’ unless it is masked by the MASK bit. If TSBUS, TSBAT, or TDIE
protections are not used, the functions can be disabled in the register by setting the TSBUS_FLT_DIS,
TSBAT_FLT_DIS, or TDIE_FLT_DIS bit to ‘1’.
TSBUS_TSBAT_ALM_STAT and FLAG is set to ‘1’ unless it is masked by corresponding mask bit when one of
the following conditions is met: 1) TSBUS is within 5% of TSBUS_FLT threshold or 2) TSBAT is within of
TSBAT_FLT. If the TSBUS_FLT or TSBAT_FLT is disabled, it will not trigger a TSBUS_TSBAT_ALM interrupt.
Using the TDIE_ALM register, an alarm can be set to notify the host when the device die temperature exceeds a
threshold. The TDIE_ALM_STAT and TDIE_ALM_FLAG bit is set to ‘1’ unless it is masked by TDIE_ALM_MASK
bit. The device will not automatically stop switching when reaching the alarm threshold and the host may decide
on the steps to take to lower the temperature, such as reducing the charge current.
9.3.11 INT Pin, STAT, FLAG, and MASK Registers
The INT pin is an open drain pin that needs to be pulled up to a voltage with a pullup resistor. INT is normally
high and will assert low for tINT when the device needs to alert the host of a fault or status change.
The fields in the STAT registers show the current status of the device, and are updated as the status changes.
The fields in the FLAG registers indicate that the event has occurred, and the field is cleared when read. If the
event persists after the FLAG register has been read and cleared, another INT signal is not sent to prevent host
keep receiving interrupts. The fields in the MASK registers allow the user to disable the interrupt on the INT pin,
but the STAT and FLAG registers are still updated even though INT is not pulled low.
9.3.12 Dual Charger Operation Using Primary and Secondary Modes
For higher power systems, it is possible to use two devices in dual charger configuration. This allows each
device to operate at lower charging current with higher efficiency compared with single device operating at the
same total charging current. The CDRVL_ADDRMS pin is used to configure the functionality of the device as
Standalone, Primary or Secondary during POR. Refer to Section 9.3.13 for proper setting. When configured as a
primary, the TSBAT_SYNCOUT pin functions as SYNCOUT, and the SRN_SYNCIN pin functions as SRN. When
configured as a Secondary, the TSBAT_SYNCOUT pin functions as TSBAT, and the SRN_SYNCIN pin functions
as SYNCIN. ACDRV1 and ACDRV2 are controlled by the primary, and ACDRV1 and ACDRV2 on the secondary
should be grounded. Pull the SYNCIN/SYNCOUT pins to REGN on the primary BQ25960 through a 1-kΩ
resistor. The maximum switching frequency in primary and secondary mode is 500 kHz.
The dual charger can operate in Primary and Secondary Mode in Bypass Mode as well. In both Bypass and
Switched Cap Mode, the current distribution between the two devices depends on loop impedance and the
chargers do not balance it. In order balance the current, the board layout needs to be as symmetrical as
possible.

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System
VBUS SYS

Main Charger

GND
BAT

RX
ACDRV2 VAC2 ACDRV2 VAC2 VAC1
BQ25960_Primary BQ25960_Secondary ACDRV1
Adapter VBUS

Host
VBUS
ACDRV1 SDA/ SDA/
Digital Core Digital Core
QB SCL SCL QB
VAC1

PMID PMID

CFH1 CFH1
VOUT VOUT
SC Phase SC Phase
CFLY1 CFLY1
CFL1 #1 #1 CFL1

PMID PMID
CFH2 BATP CFH2
BATP
SC Phase SC Phase
CFLY2 CFLY2
CFL2 #2

Battery
#2 CFL2
BATN_SRP BATN_SRP
CDRVH
CDRVH
Protection 16 bit ADC 16 bit ADC Protection
CDRVL_
CDRVL_
ADDRMS
SRN_SYNCIN ADDRMS
REGN TSBAT_SYNCOUT SRN_SYNCIN

1NŸ

Figure 9-9. Parallel Operation of BQ25960

9.3.13 CDRVH and CDRVL_ADDRMS Functions

The device requires a cap between the CDRVH and CDRVL_ADDRMS pin to operate correctly. The
CDRVL_ADDRMS pin also allows setting the default I2C address and device operation mode. Pull to GND with a
resistor for the desired setting shown in Table 9-6. The surface mount resistor with ±1% tolerance is
recommended. After POR, the host can read back the device's configuration from MS register (REG12[1:0]).
Table 9-6. I2C Address and Mode Selection
RADDRMS (kΩ) I2C ADDRESS CONFIGURATION
>75.0 0x65 Standalone
6.19 0x67 Standalone
8.06 0x66 Dual charger (Secondary)
10.5 0x66 Dual charger (Primary)
14.0 0x66 Standalone
18.2 0x67 Dual charger (Secondary)
27.4 0x65 Dual charger (Primary)

9.4 Programming
The device uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial
interface developed by NXP (formerly Philips Semiconductor, see I2C BUS Specification, Version 5, October
2012). The BUS consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the BUS is
idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C BUS through
open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal processor,
controls the BUS. The master is responsible for generating the SCL signal and device addresses. The master

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also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives
and/or transmits data on the BUS under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C BUS™
Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery
management solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from the battery in active battery mode. The
battery voltage must stay above VBATUVLO when no VIN is present to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is determined
by the ADDR pin on the device.
9.4.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in the figure below. All I2C-compatible devices
should recognize a start condition.

DATA

CLK
S P
START Condition STOP Condition

Figure 9-10. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 9-11). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see Figure 9-12) by pulling the SDA line low during the entire
high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link
with a slave has been established.

DATA

CLK

Data Line Change

Stable; of Data
Data Valid Allowed

Figure 9-11. Bit Transfer on the Serial Interface

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Data Output
by Transmitter

Not Acknowledge

Data Output
by Receiver
Acknowledge

SCL From 1 2 8 9
Master

Clock Pulse for

START Acknowledgement
Condition

Figure 9-12. Acknowledge on the I2C BUS

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 9-13). This releases the BUS and stops the
communication link with the addressed slave. All I2C compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the BUS is released, and wait for a start condition
followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP
condition to prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register
addresses not listed in this section will result in 0xFFh being read out.
Recognize START or Recognize STOP or
REPEATED START REPEATED START
Condition Condition
Generate ACKNOWLEDGE
Signal

SDA
MSB Acknowledgement Sr
Signal From Slave
Address

R/W

SCL
S Sr
or ACK ACK or
Sr P

Figure 9-13. BUS Protocol

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9.5 Register Maps

9.5.1 I2C Registers
Table 9-7 lists the I2C registers. All register offset addresses not listed in Table 9-7 should be considered as
reserved locations and the register contents should not be modified. All register bits marked 'RESERVED' in
Field column should not be modified.
Table 9-7. I2C Registers
Offset Acronym Register Name Section
0h REG00_BATOVP BATOVP Go
1h REG01_BATOVP_ALM BATOVP_ALM Go
2h REG02_BATOCP BATOCP Go
3h REG03_BATOCP_ALM BATOCP_ALM Go
4h REG04_BATUCP_ALM BATUCP_ALM Go
5h REG05_CHARGER_CONTROL 1 CHARGER_CONTROL 1 Go
6h REG06_BUSOVP BUSOVP Go
7h REG07_BUSOVP_ALM BUSOVP_ALM Go
8h REG08_BUSOCP BUSOCP Go
9h REG09_BUSOCP_ALM BUSOCP_ALM Go
Ah REG0A_TEMP_CONTROL TEMP CONTROL Go
Bh REG0B_TDIE_ALM TDIE_ALM Go
Ch REG0C_TSBUS_FLT TSBUS_FLT Go
Dh REG0D_TSBAT_FLT TSBAT_FLT Go
Eh REG0E_VAC_CONTROL VAC CONTROL Go
Fh REG0F_CHARGER_CONTROL 2 CHARGER CONTROL 2 Go
10h REG10_CHARGER_CONTROL 3 CHARGER CONTROL 3 Go
11h REG11_CHARGER_CONTROL 4 CHARGER CONTROL 4 Go
12h REG12_CHARGER_CONTROL 5 CHARGER CONTROL 5 Go
13h REG13_STAT 1 STAT 1 Go
14h REG14_STAT 2 STAT 2 Go
15h REG15_STAT 3 STAT 3 Go
16h REG16_STAT 4 STAT 4 Go
17h REG17_STAT 5 STAT 5 Go
18h REG18_FLAG 1 FLAG 1 Go
19h REG19_FLAG 2 FLAG 2 Go
1Ah REG1A_FLAG 3 FLAG 3 Go
1Bh REG1B_FLAG 4 FLAG 4 Go
1Ch REG1C_FLAG 5 FLAG 5 Go
1Dh REG1D_MASK 1 MASK 1 Go
1Eh REG1E_MASK 2 MASK 2 Go
1Fh REG1F_MASK 3 MASK 3 Go
20h REG20_MASK 4 MASK 4 Go
21h REG21_MASK 5 MASK 5 Go
22h REG22_DEVICE_INFO DEVICE INFO Go
23h REG23_ADC_CONTROL 1 ADC_CONTROL 1 Go
24h REG24_ADC_CONTROL 2 ADC_CONTROL 2 Go
25h REG25_IBUS_ADC IBUS_ADC Go
27h REG27_VBUS_ADC VBUS_ADC Go
29h REG29_VAC1_ADC VAC1_ADC Go

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Table 9-7. I2C Registers (continued)

Offset Acronym Register Name Section
2Bh REG2B_VAC2_ADC VAC2_ADC Go
2Dh REG2D_VOUT_ADC VOUT_ADC Go
2Fh REG2F_VBAT_ADC VBAT_ADC Go
31h REG31_IBAT_ADC IBAT_ADC Go
33h REG33_TSBUS_ADC TSBUS_ADC Go
35h REG35_TSBAT_ADC TSBAT_ADC Go
37h REG37_TDIE_ADC TDIE_ADC Go

Complex bit access types are encoded to fit into small table cells. Table 9-8 shows the codes that are used for
access types in this section.
Table 9-8. I2C Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

9.5.1.1 REG00_BATOVP Register (Offset = 0h) [reset = 5Ah]

REG00_BATOVP is shown in Table 9-9
Return to the Summary Table.
BATOVP
Table 9-9. REG00_BATOVP Register Field Descriptions
Bit Field Type Reset Note Description
7 BATOVP_DIS R/W 0h Reset by: Disable BATOVP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0 BATOVP_6:0 R/W 5Ah Reset by: Battery Overvoltage Setting. When the battery voltage reaches
REG_RST the programmed threshold, QB and switching FETs are turned
off and CHG_EN is set to '0'. The host controller should
monitor the bus voltage to ensure that the adapter keeps the
voltage under the BATOVP threshold for proper operation.
Type : R/W
POR: 4390 mV (5Ah)
Range : 3491 mV - 4759 mV
Fixed Offset : 3491 mV
Bit Step Size : 9.985 mV

9.5.1.2 REG01_BATOVP_ALM Register (Offset = 1h) [reset = 46h]

REG01_BATOVP_ALM is shown in Table 9-10.
Return to the Summary Table.
BATOVP_ALM

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Table 9-10. REG01_BATOVP_ALM Register Field Descriptions

Bit Field Type Reset Note Description
7 BATOVP_ALM_DIS R/W 0h Reset by: Disable BATOVP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0 BATOVP_ALM_6:0 R/W 46h Reset by: When battery voltage goes above the programmed threshold,
REG_RST an INT is sent.
The BATOVP_ALM should be set lower than BATOVP and the
host controller should monitor the battery voltage to ensure
that the adapter keeps the voltage under BATOVP threshold
for proper operation.
Type : R/W
POR: 4200 mV (46h)
Range : 3500 mV - 4770 mV
Fixed Offset : 3500 mV
Bit Step Size : 10 mV

9.5.1.3 REG02_BATOCP Register (Offset = 2h) [reset = 47h]

REG02_BATOCP is shown in Table 9-11.
Return to the Summary Table.
BATOCP
Table 9-11. REG02_BATOCP Register Field Descriptions
Bit Field Type Reset Note Description
7 BATOCP_DIS R/W 0h Reset by: Disable BATOCP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0 BATOCP_6:0 R/W 47h Reset by: Battery Overcurrent Protection Setting. When battery current
REG_RST reaches the programmed threshold, the QB and switching
FETs are disabled and CHG_EN is set to '0'. The host
controller should monitor the battery current to ensure that the
adapter keeps the current under the threshold for proper
operation.
Type : R/W
POR: 7277.5 mA (47h)
Range : 2050 mA - 8712.5 mA
Fixed Offset : 0 mA
Bit Step Size : 102.5 mA

9.5.1.4 REG03_BATOCP_ALM Register (Offset = 3h) [reset = 46h]

REG03_BATOCP_ALM is shown in Table 9-12.
Return to the Summary Table.
BATOCP_ALM
Table 9-12. REG03_BATOCP_ALM Register Field Descriptions
Bit Field Type Reset Note Description
7 BATOCP_ALM_DIS R/W 0h Reset by: Disable BATOCP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable

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Table 9-12. REG03_BATOCP_ALM Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6-0 BATOCP_ALM_6:0 R/W 46h Reset by: Battery Overcurrent Alarm Setting. When battery current
REG_RST reaches the programmed threshold, an INT is sent.
The BATOCP_ALM should be set lower than BATOCP and the
host controller should monitor the battery current to ensure
that the adapter keeps the current under BATOCP threshold
for proper operation.
Type : R/W
POR: 7000 mA (46h)
Range : 0 mA - 12700 mA
Fixed Offset : 0 mA
Bit Step Size : 100 mA

9.5.1.5 REG04_BATUCP_ALM (Offset = 4h) [reset = 28h]

REG04_BATUCP_ALM is shown in Table 9-13.
Return to the Summary Table.
BATUCP_ALM
Table 9-13. REG04_BATUCP_ALM Register Field Descriptions
Bit Field Type Reset Note Description
7 BATUCP_ALM_DIS R/W 0h Reset by: Disable BATUCP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0 BATUCP_ALM_6:0 R/W 28h Reset by: Battery Undercurrent Alarm setting. When battery current falls
REG_RST below the programmed threshold, an INT is sent. The host
controller should monitor the battery current to determine
when to disable the device and hand over charging to the
main charger.
Type : R/W
POR: 2000 mA (28h)
Range : 0 mA - 4500 mA
Fixed Offset : 0 mA
Bit Step Size : 50 mA

9.5.1.6 REG05_CHARGER_CONTROL 1 Register (Offset = 5h) [reset = 2h]

REG05_CHARGER_CONTRL 1 is shown in Table 9-14.
Return to the Summary Table.
CHARGER_CONTROL 1
Table 9-14. REG05_CHARGER_CONTROL 1 Register Field Descriptions
Bit Field Type Reset Note Description
7 BUSUCP_DIS R/W 0h Reset by: Disable BUSUCP
REG_RST Type : R/W
POR: 0b
0h = Enable, BUSUCP turns off QB and switching FETs,
BUSUCP_STAT and FLAG is set to '1', and INT is sent to host.
1h = Disable, BUSUCP does not turn off QB or switching FETs,
but BUSUCP_STAT and FLAG is set to '1', and INT is sent to
host.

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Table 9-14. REG05_CHARGER_CONTROL 1 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6 BUSUCP R/W 0h Reset by: BUSUCP Setting. If input current is below BUSUCP threshold
REG_RST after soft start timer expires, the QB and switching FETs are
turned off and CHG_EN is set to '0' and INT is sent if
BUSUCP_DIS=0. If BUSUCP_DIS=1, INT is sent to host but
converter keeps running. Change this bit to '1' before
CHG_EN is set to '1' in order for BUSUCP to be effective.
Type : R/W
POR: 0b
0h = RESERVED
1h = 250 mA
5 BUSRCP_DIS R/W 0h Reset by: Disable BUSRCP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
4 BUSRCP R/W 0h Reset by: BUSRCP Setting, if IBUS is below BUSRCP threshold, the QB
REG_RST and switching FETs are turned off and CHG_EN is set to '0'
and INT is sent. Keep this bit set to '0' in order for BUSRCP to
be effective.
Type : R/W
POR: 0b
0h = 300 mA
1h = RESERVED
3 CHG_CONFIG_1 R/W 0h Reset by: Charger Configuration 1. Set this bit to '1' before CHG_EN is
REG_RST set to '1'.
Type : R/W
POR: 0h
2 VBUS_ERRHI_DIS R/W 0h Reset by: Disable VBUS_ERRHI
REG_RST Type : R/W
POR: 0b
0h = Enable, converter does not switching, but QB is turned on
when device is in VBUS_ERRHI
1h = Disable, both converter and QB is turned on when device
is in VBUS_ERRHI
1-0 RESERVED R/W 2h Reset by: RESERVED
REG_RST Type : R/W
POR: 10b

9.5.1.7 REG06_BUSOVP Register (Offset = 6h) [reset = 26h]

REG06_BUSOVP is shown in Table 9-15.
Return to the Summary Table.
BUSOVP
Table 9-15. REG06_BUSOVP Register Field Descriptions
Bit Field Type Reset Note Description
7 BUS_PD_EN R/W 0h Reset by: VBUS Pulldown Resistor Control
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable

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Table 9-15. REG06_BUSOVP Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6-0 BUSOVP_6:0 R/W 26h Reset by: Bus Overvoltage Setting. When the bus voltage reaches the
REG_RST programmed threshold, QB and switching FETs are turned off
and CHG_EN is set to '0'. The host controller should monitor
the bus voltage to ensure that the adapter keeps the voltage
under the BUSOVP threshold for proper operation.
Switched cap mode:
Type : R/W
POR: 8900 mV (26h)
Range : 7000 mV - 12750 mV
Fixed Offset : 7000 mV
Bit Step Size : 50 mV
Bypass Mode:
Type : R/W
POR: 4450 mV (26h)
Range : 3500 mV - 6500 mV
Fixed Offset : 3500 mV
Bit Step Size : 25 mV

9.5.1.8 REG07_BUSOVP_ALM Register (Offset = 7h) [reset = 22h]

REG07_BUSOVP_ALM is shown in Table 9-16.
Return to the Summary Table.
BUSOVP_ALM
Table 9-16. REG07_BUSOVP_ALM Register Field Descriptions
Bit Field Type Reset Note Description
7 BUSOVP_ALM_DIS R/W 0h Reset by: Disable BUSOVP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0 BUSOVP_ALM_6:0 R/W 22h Reset by: Bus Overvoltage Alarm Setting. When the bus voltage reaches
REG_RST the programmed threshold, an INT is sent. The host controller
should monitor the bus voltage to ensure that the adapter
keeps the voltage under the BUSOVP threshold for proper
operation.
Switched Cap Mode:
Type : R/W
POR: 8700 mV (22h)
Range : 7000 mV - 13350 mV
Fixed Offset : 7000 mV
Bit Step Size : 50 mV
Bypass Mode:
Type : R/W
POR: 4350 mV (22h)
Range : 3500 mV - 6675 mV
Fixed Offset : 3500 mV
Bit Step Size : 25 mV

9.5.1.9 REG08_BUSOCP Register (Offset = 8h) [reset = Bh]

REG08_BUSOCP is shown in Table 9-17.
Return to the Summary Table.
BUSOCP

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Table 9-17. REG08_BUSOCP Register Field Descriptions

Bit Field Type Reset Note Description
7-5 RESERVED R 0h RESERVED
4-0 BUSOCP_4:0 R/W Bh Reset by: BUS Overcurrent Protection Setting. When the bus current
REG_RST reaches the programmed threshold, the output is disabled.
The host controller should monitor the bus current to ensure
that the adapter keeps the current under this threshold for
proper operation.
Type : R/W
Switched Cap Mode:
POR: 3816 mA (Bh)
Range: 1017.5 mA - 4579 mA
Fixed Offset : 1017.5 mA
Bit Step Size : 254 mA
Bypass Mode:
POR: 3928 mA (Bh)
Range: 1047.5 mA - 6809 mA
Fixed Offset : 1047.5 mA
Bit Step Size : 262 mA

9.5.1.10 REG09_BUSOCP_ALM Register (Offset = 9h) [reset = Ch]

REG09_BUSOCP_ALM is shown in Table 9-18.
Return to the Summary Table.
BUSOCP_ALM
Table 9-18. REG09_BUSOCP_ALM Register Field Descriptions
Bit Field Type Reset Note Description
7 BUSOCP_ALM_DIS R/W 0h Reset by: Disable BUSOCP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-5 RESERVED R 0h RESERVED
4-0 BUSOCP_ALM_4:0 R/W Ah Reset by: Bus Overvoltage Alarm Setting. When the bus current reaches
REG_RST the programmed threshold, an INT is sent. The host controller
should monitor the bus current to ensure that the adapter
keeps the current under the BUSOCP threshold for proper
operation.
Type : R/W
POR: 3500 mA (Ah)
Range : 1000 mA - 8750 mA
Fixed Offset : 1000 mA
Bit Step Size : 250 mA

9.5.1.11 REG0A_TEMP_CONTROL Register (Offset = Ah) [reset = 60h]

REG0A_TEMP_CONTROL is shown in Table 9-19.
Return to the Summary Table.
TEMP_CONTROL
Table 9-19. REG0A_TEMP_CONTROL Register Field Descriptions
Bit Field Type Reset Note Description
7 TDIE_FLT_DIS R/W 0h Reset by: Disable TDIE Overtemperature Protection
REG_RST Type : R/W
POR: 0b
0h = TDIE_FLT enable
1h = TDIE_FLT disable

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Table 9-19. REG0A_TEMP_CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6-5 TDIE_FLT_1:0 R/W 3h Reset by: TDIE Overtemperature Setting. When the junction temperature
REG_RST reaches the programmed threshold, the QB and switching
FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 11b
0h = 80C
1h = 100C
2h = 120C
3h = 140C
4 TDIE_ALM_DIS R/W 0h Reset by: Disable TDIE Overtemperature Alarm
REG_RST Type : R/W
POR: 0b
0h = TDIE_ALM enable
1h = TDIE_ALM disable
3 TSBUS_FLT_DIS R/W 0h Reset by: Disable TSBUS_FLT
REG_RST Type : R/W
POR: 0b
0h = TSBUS_FLT enable
1h = TSBUS_FLT disable
2 TSBAT_FLT_DIS R/W 0h Reset by: Disable TSBAT_FLT
REG_RST Type : R/W
POR: 0b
0h = TSBAT_FLT enable
1h = TSBAT_FLT disable
1-0 RESERVED R 0h RESERVED
Type : R
POR: 00b

9.5.1.12 REG0B_TDIE_ALM Register (Offset = Bh) [reset = C8h]

REG0B_TDIE_ALM is shown in Table 9-20.
Return to the Summary Table.
TDIE_ALM
Table 9-20. REG0B_TDIE_ALM Register Field Descriptions
Bit Field Type Reset Note Description
7-0 TDIE_ALM_7:0 R/W C8h Reset by: Die Overtemperature Alarm Setting. When the junction
REG_RST temperature reaches the programmed threshold, an INT is
sent.
Type : R/W
POR: 125°C (C8h)
Range : 25°C - 150°C
Fixed Offset : 25°C
Bit Step Size : 0.5°C

9.5.1.13 REG0C_TSBUS_FLT Register (Offset = Ch) [reset = 15h]

REG0C_TSBUS_FLT is shown in Table 9-21.
Return to the Summary Table.
TSBUS_FLT

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Table 9-21. REG0C_TSBUS_FLT Register Field Descriptions

Bit Field Type Reset Note Description
7-0 TSBUS_FLT_7:0 R/W 15h Reset by: TSBUS Percentage Fault Threshold. When the TSBUS/REGN
REG_RST ratio drops below the programmed threshold, the QB and
switching FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 4.10151% (15h)
Range : 0% - 49.8041%
Fixed Offset : 0%
Bit Step Size : 0.19531%

9.5.1.14 REG0D_TSBAT_FLT Register (Offset = Dh) [reset = 15h]

REG0D_TSBAT_FLG is shown in Table 9-22.
Return to the Summary Table.
TSBAT_FLG
Table 9-22. REG0D_TSBAT_FLT Register Field Descriptions
Bit Field Type Reset Note Description
7-0 TSBAT_FLT_7:0 R/W 15h Reset by: TSBAT Percentage Fault Threshold. When the TSBAT/REGN
REG_RST ratio drops below the programmed threshold, the QB and
switching FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 4.10151% (15h)
Range : 0% - 49.8041%
Fixed Offset : 0%
Bit Step Size : 0.19531%

9.5.1.15 REG0E_VAC_CONTROL Register (Offset = Eh) [reset = 0h]

REG0E_VAC_CONTROL is shown in Table 9-23.
Return to the Summary Table.
VAC_CONTROL
Table 9-23. REG0E_VAC_CONTROL Register Field Descriptions
Bit Field Type Reset Note Description
7-5 VAC1OVP_2:0 R/W 0h Reset by: VAC1OVP Setting. When VAC1 voltage reaches the
REG_RST programmed threshold, ACDRV1 is turned off.
Type : R/W
POR: 000b
0h = 6.5 V
1h = 10.5 V
2h = 12 V
3h = 14 V
4h = 16 V
5h = 18 V
4-2 VAC2OVP_2:0 R/W 0h Reset by: VAC2OVP Setting. When VAC2 voltage reaches the
REG_RST programmed threshold, ACDRV2 is turned off.
Type : R/W
POR: 000b
0h = 6.5 V
1h = 10.5 V
2h = 12 V
3h = 14 V
4h = 16 V
5h = 18 V

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Table 9-23. REG0E_VAC_CONTROL Register Field Descriptions (continued)

Bit Field Type Reset Note Description
1 VAC1_PD_EN R/W 0h Reset by: Enable VAC1 Pulldown Resistor
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable
0 VAC2_PD_EN R/W 0h Reset by: Enable VAC2 Pulldown Resistor
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable

9.5.1.16 REG0F_CHARGER_CONTROL 2 Register (Offset = Fh) [reset = 0h]

REG0F_CHARGER_CONTROL 2 is shown in Table 9-24.
Return to the Summary Table.
CHARGER CONTROL 2
Table 9-24. REG0F_CHARGER_CONTROL 2 Register Field Descriptions
Bit Field Type Reset Note Description
7 REG_RST R/W 0h Reset by: Register Reset. Reset registers to default values and reset
REG_RST timer. This bit automatically goes back to '0' after reset.
Type : R/W
POR: 0b
0h = Not reset register
1h = Reset register
6 EN_HIZ R/W 0h Reset by: Enable HIZ Mode. When device is in HIZ mode, converter
REG_RST stops switching, ADC stops converting, ACDRV is turned off
and the REGN LDO is forced off.
Type : R/W
POR: 0b
0h = Disable HIZ mode
1h = Enable HIZ mode
5 EN_OTG R/W 0h Reset by: Power Path Control During the OTG and Reverse TX Mode
WATCHDOG Type : R/W
REG_RST POR: 0b
0h = Don't allow host to control ACDRV(s)
1h = Allow host to control ACDRV(s)
4 CHG_EN R/W 0h Reset by: Charge Enable
WATCHDOG Type : R/W
REG_RST POR: 0b
0h = Disable charge
1h = Enable charge
3 EN_BYPASS R/W 0h Reset by: Enable Bypass Mode
WATCHDOG Type : R/W
REG_RST POR: 0b
0h = Disable Bypass Mode
1h = Enable Bypass Mode
2 DIS_ACDRV_BOTH R/W 0h Disable Both ACDRV. When this bit is set, the device forces
both ACDRV off. It is not reset by the REG_RST or the
WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV1 and ACDRV2 can be turned on
1h = ACDRV1 and ACDRV2 are forced off

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Table 9-24. REG0F_CHARGER_CONTROL 2 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
1 ACDRV1_STAT R/W 0h External ACFET1-RBFET1 Gate Driver Status. For dual input
with two sets ACFET-RBFET, this bit can be used to swap
input. It is not reset by the REG_RST or the WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV1 is OFF
1h = ACDRV1 is ON
0 ACDRV2_STAT R/W 0h External ACFET2-RBFET2 Gate Driver Status. For dual input
with two sets ACFET-RBFET, this bit can be used to swap
input. It is not reset by the REG_RST or the WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV2 is OFF
1h = ACDRV2 is ON

9.5.1.17 REG10_CHARGER_CONTROL 3 Register (Offset = 10h) [reset = 83h]

REG10_CHARGER_CONTROL 3 is shown in Table 9-25.
Return to the Summary Table.
CHARGER CONTROL 3
Table 9-25. REG10_CHARGER_CONTROL 3 Register Field Descriptions
Bit Field Type Reset Note Description
7-5 FSW_SET_2:0 R/W 4h Set Switching Frequency in Switched Cap Mode. It is not reset
by the REG_RST or the WATCHDOG.
Type : R/W
POR: 100b
0h = 187.5 kHz
1h = 250 kHz
2h = 300 kHz
3h = 375 kHz
4h = 500 kHz
5h = 750 kHz
The maximum switching frequency is 500 kHz in dual charger
configuration.
4-3 WATCHDOG_1:0 R/W 0h Reset by: Watchdog Timer
REG_RST Type : R/W
POR: 00b
0h = 0.5 s
1h = 1 s
2h = 5 s
3h = 30 s
2 WATCHDOG_DIS R/W 0h Reset by: Watchdog Timer Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
1-0 RESERVED R 3h RESERVED

9.5.1.18 REG11_CHARGER_CONTROL 4 Register (Offset = 11h) [reset = 71h]

REG11_CHARGER_CONTROL 4 is shown in Table 9-26.
Return to the Summary Table.
CHARGER CONTROL 4

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Table 9-26. REG11_CHARGER_CONTROL 4 Register Field Descriptions

Bit Field Type Reset Note Description
7 RSNS R/W 0h Reset by: Battery Current Sense Resistor Value
REG_RST Type : R/W
POR: 0b
0h = 2 mΩ
1h = 5 mΩ
6-4 SS_TIMEOUT_2:0 R/W 7h Soft Start Timeout to Check if Input Current is Above
BUSUCP Threshold. It is not reset by the REG_RST or
the WATCHDOG.
Type : R/W
POR: 111b
0h = 6.25 ms
1h = 12.5 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 400 ms
6h = 1.5 s
7h = 10 s
3-2 IBUSUCP_FALL_DG_SEL_1:0 R/W 0h Reset by: BUSUCP Deglitch Timer
REG_RST Type : R/W
POR: 00b
0h = 0.01 ms
1h = 5 ms
2h = 50 ms
3h = 150 ms
1-0 RESERVED R/W 1h Reset by: RESERVED
REG_RST Type : R/W
POR: 1b

9.5.1.19 REG12_CHARGER_CONTROL 5 Register (Offset = 12h) [reset = 60h]

REG12_CHARGER_CONTROL 5 is shown in Table 9-27.
Return to the Summary Table.
CHARGER CONTROL 5
Table 9-27. REG12_CHARGER_CONTROL 5 Register Field Descriptions
Bit Field Type Reset Note Description
7 VOUTOVP_DIS R/W 0h Reset by: Disable VOUTOVP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-5 VOUTOVP_1:0 R/W 3h Reset by: VOUTOVP Protection. When output voltage is above the
REG_RST programmed threshold, QB and switching FETs are turned off
and CHG_EN is set to '0'.
Type : R/W
POR: 11b
0h = 4.7 V
1h = 4.8 V
2h = 4.9 V
3h = 5.0 V
4-3 FREQ_SHIFT_1:0 R/W 0h Reset by: Adjust Switching Frequency
REG_RST Type : R/W
POR: 00b
0h = Nominal switching frequency set in REG10[7:5]
1h = Set switching frequency 10% higher than normal
2h = Set switching frequency 10% lower than normal

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Table 9-27. REG12_CHARGER_CONTROL 5 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
2 RESERVED R/W 0h Reset by: RESERVED
REG_RST Type : R/W
POR: 0b
1-0 MS_1:0 R 0h Primary, Secondary, Standalone Operation
Type : R
POR: 00b
0h = Standalone
1h = Secondary
2h = Primary

9.5.1.20 REG13_STAT 1 Register (Offset = 13h) [reset = 0h]

REG13_STAT 1 is shown in Table 9-28.
Return to the Summary Table.
STAT 1
Table 9-28. REG13_STAT 1 Register Field Descriptions
Bit Field Type Reset Description
7 BATOVP_STAT R 0h BATOVP Status
Type : R
POR: 0b
0h = Not in BATOVP
1h = In BATOVP
6 BATOVP_ALM_STAT R 0h BATOVP_ALM Status
Type : R
POR: 0b
0h = Not in BATOVP_ALM
1h = In BATOVP_ALM
5 VOUTOVP_STAT R 0h VOUTOVP Status
Type : R
POR: 0b
0h = Not in VOUTOVP
1h = in VOUTOVP
4 BATOCP_STAT R 0h BATOCP Status
Type : R
POR: 0b
0h = Not in BATOCP
1h = In BATOCP
3 BATOCP_ALM_STAT R 0h BATOCP_ALM Status
Type : R
POR: 0b
0h = Not in BATOCP_ALM
1h = In BATOCP_ALM
2 R 0h BATUCP_ALM Status
BATUCP_ALM_STAT Type : R
POR: 0b
0h = Not in BATUCP_ALM
1h = In BATUCP_ALM
1 BUSOVP_STAT R 0h VBUSOVP Status
Type : R
POR: 0b
0h = Not in VBUS OVP
1h = In VBUS OVP

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Table 9-28. REG13_STAT 1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 BUSOVP_ALM_STAT R 0h BUSOVP_ALM Status
Type : R
POR: 0b
0h = Not in BUSOVP_ALM
1h = In BUSOVP_ALM

9.5.1.21 REG14_STAT 2 Register (Offset = 14h) [reset = 0h]

REG14_STAT 2 is shown in Table 9-29.
Return to the Summary Table.
STAT 2
Table 9-29. REG14_STAT 2 Register Field Descriptions
Bit Field Type Reset Description
7 BUSOCP_STAT R 0h BUSOCP Status
Type : R
POR: 0b
0h = Not in BUSOCP
1h = In BUSOCP
6 BUSOCP_ALM_STAT R 0h BUSOCP_ALM Status
Type : R
POR: 0b
0h = Not in BUSOCP_ALM
1h = In BUSOCP_ALM
5 BUSUCP_STAT R 0h BUSUCP Status
Type : R
POR: 0b
0h = Not in BUSUCP
1h = In BUSUCP
4 BUSRCP_STAT R 0h BUSRCP Status
Type : R
POR: 0b
0h = Not in BUSRCP
1h = In BUSRCP
3 RESERVED R 0h RESERVED
2 CFLY_SHORT_STAT R 0h CFLY Short Detection Status
Type : R
POR: 0b
0h = CFLY not shorted
1h = CFLY shorted
1-0 RESERVED R 0h RESERVED

9.5.1.22 REG15_STAT 3 Register (Offset = 15h) [reset = 0h]

REG15_STAT 3 is shown in Table 9-30.
Return to the Summary Table.
STAT 3
Table 9-30. REG15_STAT 3 Register Field Descriptions
Bit Field Type Reset Description
7 VAC1OVP_STAT R 0h VAC1 OVP Status
Type : R
POR: 0b
0h = Not in VAC1 OVP
1h = In VAC1 OVP

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Table 9-30. REG15_STAT 3 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 VAC2OVP_STAT R 0h VAC2 OVP Status
Type : R
POR: 0b
0h = Not in VAC2 OVP
1h = In VAC2 OVP
5 VOUTPRESENT_STAT R 0h VOUT Present Status
Type : R
POR: 0b
0h = VOUT not present
1h = VOUT present
4 VAC1PRESENT_STAT R 0h VAC1 Present Status
Type : R
POR: 0b
0h = VAC1 not present
1h = VAC1 present
3 VAC2PRESENT_STAT R 0h VAC2 Present Status
Type : R
POR: 0b
0h = VAC2 not present
1h = VAC2 present
2 VBUSPRESENT_STAT R 0h VBUS Present Status
Type : R
POR: 0b
0h = VBUS not present
1h = VBUS present
1 ACRB1_CONFIG_STAT R 0h ACFET1-RBFET1 Status
Type : R
POR: 0b
0h = ACFET1-RBFET1 is not placed
1h = ACFET1-RBFET1 is placed
0 ACRB2_CONFIG_STAT R 0h ACFET2-RBFET2 Status
Type : R
POR: 0b
0h = ACFET2-RBFET2 is not placed
1h = ACFET2-RBFET2 is placed

9.5.1.23 REG16_STAT 4 Register (Offset = 16h) [reset = 0h]

REG16_STAT 4 is shown in Table 9-31.
Return to the Summary Table.
STAT 4
Table 9-31. REG16_STAT 4 Register Field Descriptions
Bit Field Type Reset Description
7 ADC_DONE_STAT R 0h ADC Conversion Status (in One-Shot Mode only)
Note: Always reads 0 in continuous mode
Type : R
POR: 0b
0h = Conversion not complete
1h = Conversion complete
6 SS_TIMEOUT_STAT R 0h Soft-Start Timeout Status
Type : R
POR: 0b
0h = Device not in soft timeout
1h = Device in soft timeout

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Table 9-31. REG16_STAT 4 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TSBUS_TSBAT_ALM_STAT R 0h TSBUS and TSBAT ALM Status
Type : R
POR: 0b
0h = TSBUS or TSBAT threshold is NOT within 5% of the
TSBUS_FLT or TSBAT_FLT set threshold
1h = TSBUS or TSBAT threshold is within 5% of the
TSBUS_FLT or TSBAT_FLT set threshold
4 TSBUS_FLT_STAT R 0h TSBUS_FLT Status
Type : R
POR: 0b
0h = Not in TSBUS_FLT
1h = In TSBUS_FLT
3 TSBAT_FLT_STAT R 0h TSBAT_FLT Status
Type : R
POR: 0b
0h = Not in TSBAT_FLT
1h = In TSBAT_FLT
2 TDIE_FLT_STAT R 0h TDIE Fault Status
Type : R
POR: 0b
0h = Not in TDIE fault
1h = In TDIE fault
1 TDIE_ALM_STAT R 0h TDIE_ALM Status
Type : R
POR: 0b
0h = Not in TDIE_ALM
1h = In TDIE_ALM
0 WD_STAT R 0h I2C Watch Dog Status
Type : R
POR: 0b
0h = Normal
1h = WD timer expired

9.5.1.24 REG17_STAT 5 Register (Offset = 17h) [reset = 0h]

REG17_STAT 5 is shown in Table 9-32.
Return to the Summary Table.
STAT 5
Table 9-32. REG17_STAT 5 Register Field Descriptions
Bit Field Type Reset Description
7 REGN_GOOD_STAT R 0h REGN_GOOD Status
Type : R
POR: 0b
0h = REGN not good
1h = REGN good
6 CONV_ACTIVE_STAT R 0h Converter Active Status
Type : R
POR: 0b
0h = Converter not running
1h = Converter running
5 RESERVED R 0h RESERVED
4 VBUS_ERRHI_STAT R 0h VBUS_ERRHI Status
Type : R
POR: 0b
0h = Not in VBUS_ERRHI status
1h = In VBUS_ERRHI status

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Table 9-32. REG17_STAT 5 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-0 RESERVED R 0h RESERVED

9.5.1.25 REG18_FLAG 1 Register (Offset = 18h) [reset = 0h]

REG18_FLAG 1 is shown in Table 9-33.
Return to the Summary Table.
FLAG 1
Table 9-33. REG18_FLAG 1 Register Field Descriptions
Bit Field Type Reset Description
7 BATOVP_FLAG R 0h BATOVP Flag
Type : R
POR: 0b
0h = Normal
1h = BATOVP status changed
6 BATOVP_ALM_FLAG R 0h BATOVP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATOVP_ALM status changed
5 VOUTOVP_FLAG R 0h VOUTOVP Flag
Type : R
POR: 0b
0h = Normal
1h = VOUTOVP status changed
4 BATOCP_FLAG R 0h BATOCP Flag
Type : R
POR: 0b
0h = Normal
1h = BATOCP status changed
3 BATOCP_ALM_FLAG R 0h BATOCP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATOCP_ALM status changed
2 BATUCP_ALM_FLAG R 0h BATUCP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATUCP_ALM status changed
1 BUSOVP_FLAG R 0h BUSOVP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOVP status changed
0 BUSOVP_ALM_FLAG R 0h BUSOVP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOVP_ALM status changed

9.5.1.26 REG19_FLAG 2 Register (Offset = 19h) [reset = 0h]

REG19_FLAG 2 is shown in Table 9-34.
Return to the Summary Table.

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FLAG 2
Table 9-34. REG19_FLAG 2 Register Field Descriptions
Bit Field Type Reset Description
7 BUSOCP_FLAG R 0h BUSOCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOCP status changed
6 BUSOCP_ALM_FLAG R 0h BUSOCP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOCP_ALM status changed
5 BUSUCP_FLAG R 0h BUSUCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSUCP status changed
4 BUSRCP_FLAG R 0h BUSRCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSRCP status changed
3 RESERVED R 0h RESERVED
2 CFLY_SHORT_FLAG R 0h CFLY Short Flag
Type : R
POR: 0b
0h = Normal
1h = CFLY_SHORT status changed
1-0 RESERVED R 0h RESERVED

9.5.1.27 REG1A_FLAG 3 Register (Offset = 1Ah) [reset = 0h]

REG1A_FLAG 3 is shown in Table 9-35.
Return to the Summary Table.
FLAG 3
Table 9-35. REG1A_FLAG 3 Register Field Descriptions
Bit Field Type Reset Description
7 VAC1OVP_FLAG R 0h VAC1OVP Flag
Type : R
POR: 0b
0h = Normal
1h = VAC1 OVP status changed
6 VAC2OVP_FLAG R 0h VAC2OVP Flag
Type : R
POR: 0b
0h = Normal
1h = VAC2 OVP status changed
5 VOUTPRESENT_FLAG R 0h VOUT Present Flag
Type : R
POR: 0b
0h = Normal
1h = VOUT present status changed
4 VAC1PRESENT_FLAG R 0h VAC1 Present Flag
Type : R
POR: 0b
0h = Normal
1h = VAC1 present status changed

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Table 9-35. REG1A_FLAG 3 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 VAC2PRESENT_FLAG R 0h VAC2 Present Flag
Type : R
POR: 0b
0h = Normal
1h = VAC2 present status changed
2 VBUSPRESENT_FLAG R 0h VBUS Present Flag
Type : R
POR: 0b
0h = Normal
1h = VBUS present status changed
1 ACRB1_CONFIG_FLAG R 0h ACFET1-RBFET1_CONFIG Flag
Type : R
POR: 0b
0h = Normal
1h = ACFET1-RBFET1_CONFIG status changed
0 ACRB2_CONFIG_FLAG R 0h ACFET2-RBFET2_CONFIG Flag
Type : R
POR: 0b
0h = Normal
1h = ACFET2-RBFET2_CONFIG status changed

9.5.1.28 REG1B_FLAG 4 Register (Offset = 1Bh) [reset = 0h]

REG1B_FLAG 4 is shown in Table 9-36.
Return to the Summary Table.
FLAG 4
Table 9-36. REG1B_FLAG 4 Register Field Descriptions
Bit Field Type Reset Description
7 ADC_DONE_FLAG R 0h ADC Conversion Flag (in One-Shot Mode only)
Type : R
POR: 0b
0h = Normal
1h = ADC conversion done status changed
6 SS_TIMEOUT_FLAG R 0h Soft-Start Timeout Flag
Type : R
POR: 0b
0h = Normal
1h = Soft start timeout status changed
5 TSBUS_TSBAT_ALM_FLAG R 0h TSBUS_TSBAT_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = Converter active status changed
4 TSBUS_FLT_FLAG R 0h TSBUS_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TSBUS_FLT status changed
3 TSBAT_FLT_FLAG R 0h TSBAT_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TSBAT_FLT status changed

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Table 9-36. REG1B_FLAG 4 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 TDIE_FLT_FLAG R 0h TDIE_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TDIE_FLT status changed
1 TDIE_ALM_FLAG R 0h TDIE_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = TDIE_ALM status changed
0 WD_FLAG R 0h I2C Watch Dog Timer Flag
Type : R
POR: 0b
0h = Normal
1h = WD timer status changed

9.5.1.29 REG1C_FLAG 5 Register (Offset = 1Ch) [reset = 0h]

REG1C_FLAG 5 is shown in Table 9-37.
Return to the Summary Table.
FLAG 5
Table 9-37. REG1C_FLAG 5 Register Field Descriptions
Bit Field Type Reset Description
7 REGN_GOOD_FLAG R 0h REGN_GOOD Flag
Type : R
POR: 0b
0h = Normal
1h = REGN_GOOD status changed
6 CONV_ACTIVE_FLAG R 0h Converter Active Flag
Type : R
POR: 0b
0h = Normal
1h = Converter active status changed
5 RESERVED R 0h RESERVED
4 VBUS_ERRHI_FLAG R 0h VBUS_ERRHI Flag
Type : R
POR: 0b
0h = Normal
1h = VBUS_ERRHI status changed
3-0 RESERVED R 0h RESERVED

9.5.1.30 REG1D_MASK 1 Register (Offset = 1Dh) [reset = 0h]

REG1D_MASK 1 is shown in Table 9-38.
Return to the Summary Table.
MASK 1
Table 9-38. REG1D_MASK 1 Register Field Descriptions
Bit Field Type Reset Note Description
7 BATOVP_MASK R/W 0h Reset by: BATOVP Mask
REG_RST Type : R/W
POR: 0b
0h = BATOVP flag produce INT
1h = BATOVP flag does not produce INT

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Table 9-38. REG1D_MASK 1 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6 BATOVP_ALM_MASK R/W 0h Reset by: BATOVP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BATOVP_ALM flag produce INT
1h = BATOVP _ALM flag does not produce INT
5 VOUTOVP_MASK R/W 0h Reset by: VOUTOVP Mask
REG_RST Type : R/W
POR: 0b
0h = VOUTOVP flag produce INT
1h = VOUTOVP flag does not produce INT
4 BATOCP_MASK R/W 0h Reset by: BATOCP Mask
REG_RST Type : R/W
POR: 0b
0h = BATOCP flag produce INT
1h = BATOCP flag does not produce INT
3 BATOCP_ALM_MASK R/W 0h Reset by: BATOCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BATOCP_ALM flag produce INT
1h = BATOCP_ALM flag does not produce INT
2 BATUCP_ALM_MASK R/W 0h Reset by: BATUCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BATUCP_ALM flag produce INT
1h = BATUCP_ALM flag does not produce INT
1 BUSOVP_MASK R/W 0h Reset by: BUSOVP Mask
REG_RST Type : R/W
POR: 0b
0h = BUSOVP flag produce INT
1h = BUSOVP flag does not produce INT
0 BUSOVP_ALM_MASK R/W 0h Reset by: BUSOVP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BUSOVP_ALM flag produce INT
1h = BUSOVP_ALM flag does not produce INT

9.5.1.31 REG1E_MASK 2 Register (Offset = 1Eh) [reset = 0h]

REG1E_MASK 2 is shown in Table 9-39.
Return to the Summary Table.
MASK 2
Table 9-39. REG1E_MASK 2 Register Field Descriptions
Bit Field Type Reset Note Description
7 BUSOCP_MASK R/W 0h Reset by: BUSOCP Mask
REG_RST Type : R/W
POR: 0b
0h = BUSOCP flag produce INT
1h = BUSOCP flag does not produce INT
6 BUSOCP_ALM_MASK R/W 0h Reset by: BUSOCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BUSOCP_ALM flag produce INT
1h = BUSOCP_ALM flag does not produce INT

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Table 9-39. REG1E_MASK 2 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
5 BUSUCP_MASK R/W 0h Reset by: BUSUCP Mask
REG_RST Type : R/W
POR: 0b
0h = BUSUCP flag produce INT
1h = BUSUCP flag does not produce INT
4 BUSRCP_MASK R/W 0h Reset by: BUSRCP Mask
REG_RST Type : R/W
POR: 0b
0h = BUSRCP flag produce INT
1h = BUSRCP flag does not produce INT
3 RESERVED R/W 0h Reset by: RESERVED
REG_RST
2 CFLY_SHORT_MASK R/W 0h Reset by: CFLY_SHORT Mask
REG_RST Type : R/W
POR: 0b
0h = CFLY_SHORT flag produce INT
1h = CFLY_SHORT flag does not produce INT
1 RESERVED R/W 0h Reset by: RESERVED
REG_RST Type : R/W
POR: 0h
0 RESERVED R 0h RESERVED

9.5.1.32 REG1F_MASK 3 Register (Offset = 1Fh) [reset = 0h]

REG1F_MASK 3 is shown in Table 9-40.
Return to the Summary Table.
MASK 3
Table 9-40. REG1F_MASK 3 Register Field Descriptions
Bit Field Type Reset Note Description
7 VAC1OVP_MASK R/W 0h Reset by: VAC1OVP Mask
REG_RST Type : R/W
POR: 0b
0h = VAC1OVP flag produce INT
1h = VAC1OVP flag does not produce INT
6 VAC2OVP_MASK R/W 0h Reset by: VAC2OVP Mask
REG_RST Type : R/W
POR: 0b
0h = VAC2OVP flag produce INT
1h = VAC2OVP flag does not produce INT
5 VOUTPRESENT_MASK R/W 0h Reset by: VOUTPRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VOUTPRESENT flag produce INT
1h = VOUTPRESENT flag does not produce INT
4 VAC1PRESENT_MASK R/W 0h Reset by: VAC1PRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VAC1PRESENT flag produce INT
1h = VAC1PRESENT flag does not produce INT
3 VAC2PRESENT_MASK R/W 0h Reset by: VAC2PRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VAC2PRESENT flag produce INT
1h = VAC2PRESENT flag does not produce INT

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Table 9-40. REG1F_MASK 3 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
2 VBUSPRESENT_MASK R/W 0h Reset by: VBUSPRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VBUSPRESENT flag produce INT
1h = VBUSPRESENT flag does not produce INT
1 ACRB1_CONFIG_MASK R/W 0h Reset by: ACFET1-RBFET1 CONFIG Mask
REG_RST Type : R/W
POR: 0b
0h = ACRB1_CONFIG flag produce INT
1h = ACRB1_CONFIG flag does not produce INT
0 ACRB2_CONFIG_MASK R/W 0h Reset by: ACFET2-RBFET2 CONFIG Mask
REG_RST Type : R/W
POR: 0b
0h = ACRB2_CONFIG flag produce INT
1h = ACRB2_CONFIG flag does not produce INT

9.5.1.33 REG20_MASK 4 Register (Offset = 20h) [reset = 0h]

REG20_MASK 4 is shown in Table 9-41.
Return to the Summary Table.
MASK 4
Table 9-41. REG20_MASK 4 Register Field Descriptions
Bit Field Type Reset Note Description
7 ADC_DONE_MASK R/W 0h Reset by: ADC_DONE Mask
REG_RST Type : R/W
POR: 0b
0h = ADC_DONE flag produce INT
1h = ADC_DONE flag does not produce INT
6 SS_TIMEOUT_MASK R/W 0h Reset by: SS_TIMEOUT Mask
REG_RST Type : R/W
POR: 0b
0h = SS_TIMEOUT flag produce INT
1h = SS_TIMEOUT flag does not produce INT
5 TSBUS_TSBAT_ALM_MASK R/W 0h Reset by: TSBUS_TSBAT_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = TSBUS_TSBAT_ALM flag produce INT
1h = TSBUS_TSBAT_ALM flag does not produce INT
4 TSBUS_FLT_MASK R/W 0h Reset by: TSBUS_FLT Mask
REG_RST Type : R/W
POR: 0b
0h = TSBUS_FLT flag produce INT
1h = TSBUS_FLT flag does not produce INT
3 TSBAT_FLT_MASK R/W 0h Reset by: TSBAT_FLT Mask
REG_RST Type : R/W
POR: 0b
0h = TSBAT_FLT flag produce INT
1h = TSBAT_FLT flag does not produce INT
2 TDIE_FLT_MASK R/W 0h Reset by: TDIE_FLT Mask
REG_RST Type : R/W
POR: 0b
0h = TDIE_FLT flag produce INT
1h = TDIE_FLT flag does not produce INT

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Table 9-41. REG20_MASK 4 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
1 TDIE_ALM_MASK R/W 0h Reset by: TDIE_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = TDIE_ALM flag produce INT
1h = TDIE_ALM flag does not produce INT
0 WD_MASK R/W 0h Reset by: Watchdog Mask
REG_RST Type : R/W
POR: 0b
0h = WD flag produce INT
1h = WD flag does not produce INT

9.5.1.34 REG21_MASK 5 Register (Offset = 21h) [reset = 0h]

REG21_MASK 5 is shown in Table 9-42.
Return to the Summary Table.
MASK 5
Table 9-42. REG21_MASK 5 Register Field Descriptions
Bit Field Type Reset Note Description
7 REGN_GOOD_MASK R/W 0h Reset by: REGN_GOOD Mask
REG_RST Type : R/W
POR: 0b
0h = REGN_GOOD flag produce INT
1h = REGN_GOOD flag does not produce INT
6 CONV_ACTIVE_MASK R/W 0h Reset by: CONV_ACTIVE Mask
REG_RST Type : R/W
POR: 0b
0h = CONV_ACTIVE flag produce INT
1h = CONV_ACTIVE flag does not produce INT
5 RESERVED R/W 0h Reset by: RESERVED
REG_RST Type : R/W
POR: 0h
4 VBUS_ERRHI_MASK R/W 0h Reset by: VBUS_ERRHI Mask
REG_RST Type : R/W
POR: 0b
0h = VBUS_ERRHI flag produce INT
1h = VBUS_ERRHI flag does not produce INT
3-0 RESERVED R 0h RESERVED

9.5.1.35 REG22_DEVICE_INFO Register (Offset = 22h) [reset = 0h]

REG22_DEVICE_INFO is shown in Table 9-43.
Return to the Summary Table.
DEVICE INFO
Table 9-43. REG22_DEVICE_INFO Register Field Descriptions
Bit Field Type Reset Description
7-4 DEVICE_REV_3:0 R 0h Device Revision
Type : R
POR: 0h
3-0 DEVICE_ID_3:0 R 0h Device ID
Type : R
POR: 0h

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9.5.1.36 REG23_ADC_CONTROL 1 Register (Offset = 23h) [reset = 0h]

REG23_ADC_CONTROL 1 is shown in Table 9-44.
Return to the Summary Table.
ADC_CONTROL 1
Table 9-44. REG23_ADC_CONTROL 1 Register Field Descriptions
Bit Field Type Reset Note Description
7 ADC_EN R/W 0h Reset by: ADC Enable
WATCHDOG Type : R/W
REG_RST POR: 0b
0h = Disable
1h = Enable
6 ADC_RATE R/W 0h Reset by: ADC Rate
REG_RST Type : R/W
POR: 0b
0h = Continuous conversion
1h = 1 shot
5 ADC_AVG R/W 0h Reset by: ADC Average
REG_RST Type : R/W
POR: 0b
0h = Single value
1h = Running average
4 ADC_AVG_INIT R/W 0h Reset by: ADC Average Initial Value
REG_RST Type : R/W
POR: 0b
0h = Start average using the existing register value
1h = Start average using a new conversion
3-2 ADC_SAMPLE_1:0 R/W 0h Reset by: ADC Sample Speed
REG_RST Type : R/W
POR: 00b
0h = 15 bit
1h = 14 bit
2h = 13 bit
3h = 11 bit
1 IBUS_ADC_DIS R/W 0h Reset by: IBUS ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
0 VBUS_ADC_DIS R/W 0h Reset by: VBUS ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable

9.5.1.37 REG24_ADC_CONTROL 2 Register (Offset = 24h) [reset = 0h]

REG24_ADC_CONTROL 2 is shown in Table 9-45.
Return to the Summary Table.
ADC_CONTROL 2
Table 9-45. REG24_ADC_CONTROL 2 Register Field Descriptions
Bit Field Type Reset Note Description
7 VAC1_ADC_DIS R/W 0h Reset by: VAC1 ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable

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Table 9-45. REG24_ADC_CONTROL 2 Register Field Descriptions (continued)

Bit Field Type Reset Note Description
6 VAC2_ADC_DIS R/W 0h Reset by: VAC2 ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
5 VOUT_ADC_DIS R/W 0h Reset by: VOUT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
4 VBAT_ADC_DIS R/W 0h Reset by: VBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
3 IBAT_ADC_DIS R/W 0h Reset by: IBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
2 TSBUS_ADC_DIS R/W 0h Reset by: TSBUS ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
1 TSBAT_ADC_DIS R/W 0h Reset by: TSBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
0 TDIE_ADC_DIS R/W 0h Reset by: TDIE ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable

9.5.1.38 REG25_IBUS_ADC Register (Offset = 25h) [reset = 0h]

REG25_IBUS_ADC is shown in Table 9-46.
Return to the Summary Table.
IBUS_ADC
Table 9-46. REG25_IBUS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 IBUS_ADC_15:0 R 0h IBUS ADC Reading
Type : R
POR: 0 mA (0h)
Range : 0 mA - 7000 mA
Switched Cap Mode:
Fixed Offset : 66 mA
Bit Step Size : 0.9972 mA
Bypass Mode:
Fixed Offset : 64 mA
Bit Step Size : 1.0279 mA

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9.5.1.39 REG27_VBUS_ADC Register (Offset = 27h) [reset = 0h]

REG27_VBUS_ADC is shown in Table 9-47.
Return to the Summary Table.
VBUS_ADC
Table 9-47. REG27_VBUS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VBUS_ADC_15:0 R 0h VBUS ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 16385 mV
Fixed Offset : 0 mV
Bit Step Size : 1.002 mV

9.5.1.40 REG29_VAC1_ADC Register (Offset = 29h) [reset = 0h]

REG29_VAC1_ADC is shown in Table 9-48.
Return to the Summary Table.
VAC1_ADC
Table 9-48. REG29_VAC1_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VAC1_ADC_15:0 R 0h VAC1 ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 14000 mV
Fixed Offset : 3 mV
Bit Step Size : 1.0008 mV

9.5.1.41 REG2B_VAC2_ADC Register (Offset = 2Bh) [reset = 0h]

REG2B_VAC2_ADC is shown in Table 9-49.
Return to the Summary Table.
VAC2_ADC
Table 9-49. REG2B_VAC2_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VAC2_ADC_15:0 R 0h VAC2 ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 14000 mV
Fixed Offset : 5 mV
Bit Step Size : 1.0006 mV

9.5.1.42 REG2D_VOUT_ADC Register (Offset = 2Dh) [reset = 0h]

REG2D_VOUT_ADC is shown in Table 9-50.
Return to the Summary Table.
VOUT_ADC

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Table 9-50. REG2D_VOUT_ADC Register Field Descriptions

Bit Field Type Reset Description
15-0 VOUT_ADC_15:0 R 0h VOUT ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 6000 mV
Fixed Offset : 2 mV
Bit Step Size : 1.0037 mV

9.5.1.43 REG2F_VBAT_ADC Register (Offset = 2Fh) [reset = 0h]

REG2F_VBAT_ADC is shown in Table 9-51.
Return to the Summary Table.
VBAT_ADC
Table 9-51. REG2F_VBAT_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VBAT_ADC_15:0 R 0h VBAT ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 6000 mV
Fixed Offset : 1 mV
Bit Step Size : 1.017 mV

9.5.1.44 REG31_IBAT_ADC Register (Offset = 31h) [reset = 0h]

REG31_IBAT_ADC is shown in Table 9-52.
Return to the Summary Table.
IBAT_ADC
Table 9-52. REG31_IBAT_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 IBAT_ADC_15:0 R 0h IBAT ADC Reading
Type : R
POR: 0 mA (0h)
Range : 0 mA - 12000 mA
Fixed Offset : -150 mA
Bit Step Size : 0.999 mA

9.5.1.45 REG33_TSBUS_ADC Register (Offset = 33h) [reset = 0h]

REG33_TSBUS_ADC is shown in Table 9-53.
Return to the Summary Table.
TSBUS_ADC
Table 9-53. REG33_TSBUS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 TSBUS_ADC_15:0 R 0h TSBUS ADC Reading
Type : R
POR: 0% (0h)
Range : 0% - 50%
Fixed Offset : 0.1%
Bit Step Size : 0.09860%

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9.5.1.46 REG35_TSBAT_ADC Register (Offset = 35h) [reset = 0h]

REG35_TSBAT_ADC is shown in Table 9-54.
Return to the Summary Table.
TSBAT_ADC
Table 9-54. REG35_TSBAT_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 TSBAT_ADC_15:0 R 0h TSBAT ADC Reading
Type : R
POR: 0% (0h)
Range : 0% - 50%
Fixed Offset : 0.065%
Bit Step Size : 0.09762%

9.5.1.47 REG37_TDIE_ADC Register (Offset = 37h) [reset = 0h]

REG37_TDIE_ADC is shown in Table 9-55.
Return to the Summary Table.
TDIE_ADC
Table 9-55. REG37_TDIE_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 TDIE_ADC_15:0 R 0h TDIE ADC Reading
Type : R
POR: 0°C (0h)
Range : -40°C - 150°C
Fixed Offset : -3.5°C
Bit Step Size : 0.5079°C

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

A typical application consists of the device configured as an I2C controlled parallel charger along with a standard
switching charger, however, it can also be used with a linear charger or PMIC with integrated charger as well.
BQ25960 can start fast charging after the main charger completes pre-charging. BQ25960 will then hand back
charging to the main charger when final current tapering is desired. This point is usually where the efficiency of
the main charger is acceptable for the application. The device can be used to charge Li-Ion and Li-polymer
batteries used in a wide range of smartphones and other portable devices. To take advantage of the high charge
current capabilities of the BQ25960, it may be necessary to charge in excess of 1C. In this case, be sure to
follow the battery manufacturers recommendations closely.
10.2 Typical Application
A typical schematic is shown below with all the optional and required components shown.

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10.2.1 Standalone Application Information (for use with main charger)

System
VBUS SYS

Main Charger

GND
BAT

Adapter VBUS ACDRV2 VAC2

1µF BQ25960

Wireless
ACDRV1 SDA

QB Digital
Core SCL Host
VAC1

PMID /INT

10µF
QCH1 QCH2
CFH1 CFH2

CFLY1 QDH1 QDH2 CFLY2

1-3×22µF 1-3×22µF
VOUT

QCL1 22µF
QCL2
CFL1 CFL2

QDL1 100Ÿ
QDL2 Battery
GND BATP

BATN_SRP
Protection 16 bit ADC
2PŸ
SRN_SYNCIN
REGN

10NŸ
REGN
TSBUS
10NŸ 10NŸ 10NŸ
TSBAT_SYNCOUT
CDRVH 10NŸ 10NŸ
220nF
CDRVL_
ADDRMS REGN
75NŸ
4.7µF

Figure 10-1. BQ25960 Typical Application Diagram with Dual Input

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System
VBUS SYS

Main Charger

GND
BAT

Optional

Adapter ACDRV2 VAC2

VBUS
1µF
ACDRV1
BQ25960
SDA
VAC1
QB Digital
Core SCL Host

PMID INT

10µF
QCH1 QCH2
CFH1 CFH2

CFLY1 QDH1 QDH2 CFLY2

1-3×22µF 1-3×22µF
VOUT

QCL1 22µF
QCL2
CFL1 CFL2

QDL1 100Ÿ
QDL2

Battery
GND BATP

BATN_SRP
Protection 16 bit ADC
2PŸ
SRN_SYNCIN
REGN

10NŸ
TSBUS
REGN
10NŸ 10NŸ
10NŸ
TSBAT_SYNCOUT
CDRVH 10NŸ 10NŸ
220nF
CDRVL_
ADDRMS REGN
75NŸ 4.7µF

Figure 10-2. BQ25960 Typical Application Diagram with Single Input

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10.2.1.1 Design Requirements

The design requires a smart wall adapter to provide the proper input voltage and input current to the BQ25960,
following the USB_PD Programmable Power Supply (PPS) voltage steps and current steps. The design shown
is capable of charging up to 8 A, although this may not be practical for some applications due to the total power
loss at this operating point. Careful consideration of the thermal constraints, space constraints, and operating
conditions should be done to ensure acceptable performance.
10.2.1.2 Detailed Design Procedure
The first step is to determine the number of CFLY caps to put on each phase of the design. It is important to
consider the current rating of the caps, their ESR, and the capacitance rating. Be sure to consider the bias
voltage derating for the caps, as the CFLY caps are biased to half of the input voltage, and this will affect their
effective capacitance. An optimal system will have 3 22-µF caps per phase, for a total of 6 caps per device. It is
possible to use fewer caps if the board space is limited. Using fewer caps will result in higher voltage and current
ripple on the output, as well as lower efficiency.
The default switching frequency, fSW, for the power stage is 500 kHz. The switching frequency can be adjusted in
register 0x10h using the FSW_SET bits. It is recommended to select 500 kHz if IBATADC is not used and 375
kHz if IBATADC is used.
It is recommended to use 1-µF cap on VBUS, 10-µF cap on PMID and 22-µF cap on VOUT.
10.2.1.3 Application Curves

Figure 10-3. Switched Cap Mode Power Up Figure 10-4. Bypass Mode Power Up

Figure 10-5. Adapter Unplug in Switched Cap Mode Figure 10-6. Adapter Unplug in Bypass Mode

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Figure 10-7. VBUSOVP in Switched Cap Mode Figure 10-8. VBUSOVP in Bypass Mode

Figure 10-9. IBUSOCP in Switched Cap Mode Figure 10-10. IBUSOCP in Bypass Mode

Figure 10-11. VBATOVP in Switched Cap Mode Figure 10-12. VBATOVP in Bypass Mode

Figure 10-13. IBATOCP in Switched Cap Mode Figure 10-14. IBATOCP in Bypass Mode

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VAC1 and VAC2 short to VBUS, ACDRV1 and ACDRV2 short VAC1 connected to input source, VAC2 short to VBUS,
to ground ACDRV1 active, ACDRV2 short to ground

Figure 10-15. Power Up without AC-RFFET Figure 10-16. Power Up from VAC1 with Single
ACFET1

VAC1 connected to input source 1, VBUS connected to input VAC1 connected to input source 1, VBUS connected to input
source 2, VAC2 short to VBUS, ACDRV1 active, ACDRV2 source 2, VAC2 short to VBUS, ACDRV1 active, ACDRV2
short to ground short to ground

Figure 10-17. Power Up from VAC1 with ACFET1- Figure 10-18. Plugin VAC1 When Device is Power
RBFET1 Up From VBUS with ACFET1-RBFET1

VAC1 connected to input source 1, VAC2 connected to input VAC1 connected to input source 1, VAC2 connected to input
source 2, ACDRV1 and ACDRV2 active source 2, ACDRV1 and ACumDRV2 active

Figure 10-19. Power Up from VAC1 with ACFET1- Figure 10-20. Power Up from VAC2 with ACFET1-
RBFET1 and ACFET2-RBFET2 RBFET1 and ACFET2-RBFET2

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11 Power Supply Recommendations

The BQ25960 can be powered by a standard power supply capable of meeting the input voltage and current
requirements for evaluation. In the actual application, it must be used with a wall adapter that supports USB
Power Delivery (PD) Programmable Power Supply (PPS) specifications.

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12 Layout

12.1 Layout Guidelines

Layout is very important to maximize the electrical and thermal performance of the total system. General
guidelines are provided, but the form factor, board stack-up, and proximity of other components also need to be
considered to maximize the performance.
1. VBUS and VOUT traces should be as short and wide as possible to accommodate for high current.
2. Copper trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP ball
array) before making turns.
3. CFLY caps should be placed as close as possible to the device and CFLY trace should be as wide as
possible until close to the IC.
4. CLFY pours should be as symmetrical between CFH pads and CFL pads as possible.
5. Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be placed as
close to the device pins as possible.
6. The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the
device, as these are switching pins and this will help reduce EMI.
7. Do not route so the power planes are interrupted by signal traces.
Refer to the EVM design and more information in the BQ25960EVM (BMS041) Evaluation Module User's Guide
for the recommended component placement with trace and via locations.
12.2 Layout Example

CFLY1 CFLY2
0603 0603

CFLY1 CFLY2
0603 0603

1 2 3 4 5 6
Blind via
GND CFL1 VOUT CFH1 PMID VBUS
A
Top Layer

B GND CFL1 VOUT CFH1 PMID VBUS Bottom Layer

Mid Layer_1
GND CFL2 VOUT CFH2 PMID VBUS
C

Mid Layer_2
CDRVH CFL2 VOUT CFH2 /INT SRN
D

SCL SRP_
CDRVL VAC2 VAC1 TSBAT
E BATN

REGN ACDRV2 ACDRV1 TSBUS SDA BATP

F

Figure 12-1. BQ25960 Layout Example

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13 Device and Documentation Support

13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ25960EVM (BMS041) Evaluation Module User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

BQ25960YBGR Active Production DSBGA (YBG) | 36 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 BQ25960
BQ25960YBGR.A Active Production DSBGA (YBG) | 36 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 BQ25960
BQ25960YBGR.B Active Production DSBGA (YBG) | 36 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 BQ25960

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Feb-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25960YBGR DSBGA YBG 36 3000 180.0 8.4 2.73 2.73 0.68 4.0 8.0 Q1
BQ25960YBGR DSBGA YBG 36 3000 180.0 8.4 2.73 2.73 0.68 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Feb-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ25960YBGR DSBGA YBG 36 3000 182.0 182.0 20.0
BQ25960YBGR DSBGA YBG 36 3000 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
YBG0036 SCALE 6.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX
SEATING PLANE
0.20 BALL TYP 0.05 C
0.14

2 TYP

SYMM

2
TYP D
SYMM

C D: Max = 2.542 mm, Min =2.482 mm

E: Max = 2.542 mm, Min =2.482 mm

B
0.4 TYP
A
1 2 3 4 5 6
0.27
36X
0.23
0.015 C A B 0.4 TYP

4224846/A 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
YBG0036 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

36X ( 0.23)
1 2 3 4 5 6

A
(0.4) TYP

C
SYMM

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 30X

0.05 MAX 0.05 MIN METAL UNDER

( 0.23) SOLDER MASK
METAL

EXPOSED ( 0.23)
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL METAL OPENING
SOLDER MASK
NON-SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE

4224846/A 03/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YBG0036 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

36X ( 0.25)
(R0.05) TYP
1 2 3 4 5 6

A
(0.4) TYP

C
SYMM

METAL
TYP D

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 30X

4224846/A 03/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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