BQ25750

SLUSDY3 – DECEMBER 2023

BQ25750: Standalone/I2C Controlled, 1- to 14-Cell Bidirectional Buck-Boost Battery

Charge Controller with Direct Power Path Control

1 Features 2 Applications
• Wide input voltage operating range: 4.2 V to 70 V • Cordless power and garden tools
• Wide battery voltage operating range: up-to 70 V • Solar backup charger
with multi-chemistry support: • Energy storage systems
– 1- to 14-cell Li-ion charge profile • Drone
– 1- to 16-cell LiFePO4 charge profile • Ultrasound
• Synchronous buck-boost charge controller with • X-ray systems
NFET drivers • Electronic hospital beds and bed control
– Adjustable switching frequency from 200 kHz to • Multiparameter patient monitors
600 kHz 3 Description
– Optional synchronization to external clock
– Integrated loop compensation with soft start The BQ25750 is a wide input voltage, switched-mode
– Optional gate driver supply input for optimized buck-boost Li-Ion, Li-polymer, or LiFePO4 battery
efficiency charge controller with direct power path control.
• Bidirectional converter operation (Reverse Mode) The device offers high-efficiency battery charging
supporting USB-PD Extended Power Range (EPR) over a wide voltage range with accurate charge
– Adjustable input voltage (VAC) regulation from current and charge voltage regulation, in addition to
3.3 V to 65 V with 20-mV/step automatic charge preconditioning, termination, and
– Adjustable input current regulation (RAC_SNS) charge status indication. The device integrates all
from 400 mA to 20 A with 50-mA/step using the loop compensation for the buck-boost converter,
5-mΩ resistor thereby providing a high density solution with ease of
• Direct power path management for highest use. In reverse mode, the device draws power from
efficiency to power system the battery and regulates the SYS terminal voltage.
– System power selection from adapter or battery Package Information
– Dynamic power management PART PACKAGE BODY SIZE
PACKAGE(1)
– All N-channel FET drivers NUMBER SIZE(2) (NOM)
• High accuracy BQ25750 RRV (VQFN 36)
6.0 mm × 5.0 6.0 mm × 5.0
– ±0.5% charge voltage regulation mm mm
– ±3% charge current regulation (1) For all available packages, see Section 14.
– ±3% input current regulation (2) The package size (length × width) is a nominal value and
• I2C controlled for optimal system performance with includes pins, where applicable.
resistor-programmable option OPTIONAL

– Hardware adjustable input and output current

INPUT SYSTEM

+ CSYS
OPTIONAL

limits
• Integrated 16-bit ADC for voltage, current, and
temperature monitoring
• Low battery quiescent current
• High safety integration HIDRV1 SW1 SW2 HIDRV2
LODRV1 LODRV2

– Adjustable input overvoltage and undervoltage ACN

ACP
ACDRV
SYS
BATSRC
BATDRV

protection VAC

SRP

– Battery overvoltage and overcurrent protection

SRN
FB REGN
BATTERY
REGN

– Charging safety timer TS

– Battery short protection Host I2C

ILIM_HIZ
ICHG

– Thermal shutdown PGND

• Status outputs
BQ25750

– Adapter present status (PG) Simplified Schematic

– Charger operation status
• Package
– 36-pin 5 mm × 6 mm QFN

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 BQ25750 Registers...................................................40
2 Applications..................................................................... 1 9 Application and Implementation.................................. 62
3 Description.......................................................................1 9.1 Application Information............................................. 62
4 Description (continued).................................................. 3 9.2 Typical Applications.................................................. 62
5 Device Comparison......................................................... 4 10 Power Supply Recommendations..............................73
6 Pin Configuration and Functions...................................5 11 Layout........................................................................... 74
7 Specifications.................................................................. 8 11.1 Layout Guidelines................................................... 74
7.1 Absolute Maximum Ratings........................................ 8 11.2 Layout Example...................................................... 75
7.2 ESD Ratings............................................................... 8 12 Device and Documentation Support..........................77
7.3 Recommended Operating Conditions.........................8 12.1 Device Support....................................................... 77
7.4 Thermal Information....................................................9 12.2 Receiving Notification of Documentation Updates..77
7.5 Electrical Characteristics...........................................10 12.3 Support Resources................................................. 77
7.6 Timing Requirements................................................ 16 12.4 Trademarks............................................................. 77
7.7 Typical Characteristics (BQ25750)........................... 17 12.5 Electrostatic Discharge Caution..............................77
8 Detailed Description......................................................20 12.6 Glossary..................................................................77
8.1 Overview................................................................... 20 13 Revision History.......................................................... 77
8.2 Functional Block Diagram......................................... 21 14 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................22 Information.................................................................... 78
8.4 Device Functional Modes..........................................38

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4 Description (continued)
Besides the I2C host-controlled charging mode, the device also supports standalone charging mode via resistor
programmable limits. Input current, charge current and charge voltage regulation targets can be set via the
ILIM_HIZ, ICHG and FB pins, respectively.
The device has three status pins (STAT1, STAT2, and PG) to indicate the charging status and input voltage
status. These pins can be used to drive LEDs or communicate with a host processor. If needed, these pins can
also be used as general purpose indicators and their status controlled directly by the I2C interface. The INT pin
immediately notifies host when the device status changes, including faults.
The device also provides an analog-to-digital converter (ADC) for monitoring input current, charge current and
input/battery/system/thermistor voltages.
The device comes with a 36-pin 5.0 mm × 6.0 mm QFN package with 0.5 mm pin pitch.

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5 Device Comparison
PART NUMBER BQ25750 BQ25756E BQ25756
Key Feature Li-Ion, LFP Li-Ion, LFP Li-Ion, LFP
Charger Topology Buck-Boost Buck-Boost Buck-Boost
Power Topology Direct Power-Path Non Power-Path Non Power-Path
I2C Address 0X6B 0X6A 0X6B
Default Charge Profile Li-Ion (trickle, precharge, CC, CV) Li-Ion (trickle, precharge, CC, CV) Li-Ion (trickle, precharge, CC, CV)
Configuration I2C + Standalone I2C + Standalone I2C + Standalone
Operating VIN 4.2V → 70V 4.2V → 36V 4.2V → 70V
Pin Count 36 36 36
Package 5X6 QFN 5X6 QFN 5X6 QFN
TS Pin Function JEITA profile JEITA profile JEITA profile

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6 Pin Configuration and Functions

FSW_
ACOV ACUV VAC SYS ACDRV ACP ACN
SYNC

36 35 34 33 32 31 30 29

SCL 1 28 SW1

SDA 2 27 HIDRV1

INT 3 26 BTST1

STAT1 4 25 LODRV1

STAT2 5 24 REGN
37
PG 6 PGND 23 DRV_SUP

CE 7 22 PGND

TS 8 21 LODRV2

ICHG 9 20 BTST2

ILIM_HIZ 10 19 HIDRV2

11 12 13 14 15 16 17 18

BAT BAT
FBG FB SRN SRP PGND SW2
DRV SRC

Figure 6-1. BQ25750, RRV Package 36-Pin VQFN Top View

Table 6-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
SCL 1 I I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 2 IO I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
Open Drain Interrupt Output – Connect the INT pin to a logic rail via 10-kΩ resistor. The INT pin sends
INT 3 O
an active low, 256-μs pulse to host to report the charger device status and faults.
Open Drain Charge Status 1 Output – STAT1 and STAT2 indicate various charger operations, see
Table 8-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be
STAT1 4 O
disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general
purpose indicator via the FORCE_STAT1_ON bit.
Open Drain Charge Status 2 Output – STAT1 and STAT2 indicate various charger operations, see
Table 8-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be
STAT2 5 O
disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general
purpose indicator via the FORCE_STAT2_ON bit.
Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW
indicates a good input source if VAC is within the programmed ACUV / ACOV operating window. The
PG 6 O
PG pin function can be disabled when DIS_PG_PIN bit is set to 1. When disabled, this pin can be used
as a general purpose indicator via the FORCE_STAT3_ON bit.
Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is
LOW. CE pin must be pulled HIGH or LOW, do not leave floating. The CE pin function can be disabled
CE 7 IO
when DIS_CE_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator
via the FORCE_STAT4_ON bit.

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Table 6-1. Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor.
TS 8 I Program temperature window with a resistor divider from REGN to TS to PGND. Charge suspends
when TS pin voltage is out of range. Recommend 103AT-2 10-kΩ thermistor.
Charge Current Limit Setting – ICHG pin sets the maximum charge current, and can be used to
monitor the charge current. A programming resistor to PGND is used to set the charge current limit as
ICHG = KICHG / RICHG. When the device is under charge current regulation, the voltage at ICHG pin is
ICHG 9 I VREF_ICHG. When ICHG pin voltage is less than VREF_ICHG, the actual charge current can be calculated
as: IBAT = KICHG x VICHG / ( RICHG x VREF_ICHG). The actual charge current limit is the lower of the limits
set by ICHG pin or the ICHG_REG register bits. This pin function can be disabled when EN_ICHG_PIN
bit is 0. If ICHG pin is not used, this pin should be pulled to PGND, do not leave floating.
Input Current Limit Setting and HIZ Mode Control Pin – ILIM_HIZ pin sets the maximum input
current limit, can be used to monitor the input current and can be pulled HIGH to force device into
HIZ mode. A programming resistor to PGND is used to set the input current limit as ILIM = KILIM /
RILIM. When the device is under input current regulation, the voltage at ILIM_HIZ pin is VREF_ILIM. When
ILIM_HIZ 10 I
ILIM_HIZ pin voltage is less than VREF_ILIM, the actual input current can be calculated as: IAC = KILIM
x VILIM / ( RILIM x VREF_ILIM). The actual input current limit is the lower of the limits set by ILIM_HIZ
pin or the IAC_DPM register bits. This pin function can be disabled when EN_ILIM_HIZ_PIN bit is 0. If
ILIM_HIZ pin is not used, this pin should be pulled to PGND, do not leave floating.
Voltage Feedback Divider Return – Connect to the bottom of battery feedback resistor. When
FBG 11 I charging, this pin is driven to PGND internally. When input voltage is outside of the ACUV / ACOV
operating window, this pin is high-impedance, minimizing battery leakage current.
Charge Voltage Analog Feedback Adjustment – Connect the output of a resistive voltage divider
FB 12 I
from the battery terminals to this node to adjust the output battery regulation voltage.
Charge Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from SRN to
SRN 13 I SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN
pin to PGND for common-mode filtering.
Charge Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from SRN
SRP 14 I to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to
PGND for common-mode filtering.
N-Channel Battery FET Gate Drive – Connect directly to the BATFET gate. Pin drives the gate with
10 V relative to BATSRC to turn on BATFET when the input voltage is outside of the ACUV / ACOV
BATDRV 15 O
operating window. An optional capacitor from BATDRV to BATSRC can be used to slow down the turn
on transition.
BATSRC 16 I N-Channel Battery FET Source – Connect directly to the BATFETs common source.
PGND 17 I Tie this pin directly to PGND.
Boost Side Half Bridge Switching Node – Connect to the source of boost HS FET and the drain of
SW2 18 P
boost LS FET. Connect the inductor between SW1 and SW2.
HIDRV2 19 O Boost Side High-Side Gate Driver – Connect to the boost high-side N-channel MOSFET gate.
Boost Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between
BTST2 20 P
BTST2 and SW2 to provide bias to the high-side MOSFET gate driver.
LODRV2 21 O Boost Side Low-Side Gate Driver – Connect to the boost low-side N-channel MOSFET gate.
PGND 22 P Power Ground Return – The high current ground connection for the low-side gate drivers.
Charger Gate Drive Supply Input – Voltage on this pin is used to drive the gates of buck-boost
converter switching FET. Connect a 4.7-μF ceramic capacitor from DRV_SUP to power ground. REGN
LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to
DRV_SUP 23 P
DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with
an external supply up to 12 V to achieve higher switching efficiency. See Section 8.3.3.2 for more
details.
Charger Internal Linear Regulator Output – Connect a 4.7-μF ceramic capacitor from REGN to
power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by
REGN 24 P connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the
DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See
Section 8.3.3.2 for more details.
LODRV1 25 O Buck Side Low-Side Gate Driver – Connect to the buck low-side N-channel MOSFET gate.
Buck Side High-Side Power MOSFET Gate Driver Power Supply – Connect a capacitor between
BTST1 26 P
BTST1 and SW1 to provide bias to the high-side MOSFET gate driver.

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Table 6-1. Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
HIDRV1 27 O Buck Side High-Side Gate Driver – Connect to the buck high-side N-channel MOSFET gate.
Buck Side Half Bridge Switching Node – Connect to the source of buck HS FET and the drain of
SW1 28 P
buck LS FET. Connect the inductor between SW1 and SW2.
Adapter Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from ACN
ACN 29 I to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the
ACN pin to PGND for common-mode filtering.
Adapter Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from ACN
ACP 30 I to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to
PGND for common-mode filtering
N-Channel Input FET Gate Drive – Connect directly to the back-to-back input FETs (ACFETs) gates.
Pin drives the gate with 10V to turn on ACFETs when the input voltage is inside of the ACUV / ACOV
ACDRV 31 O
operating window. If input voltage is outside the valid operating window, this pin pulls to PGND to turn
off the FETs. Connect a 15-V Zener diode from ACDRV to the common source of the ACFETs.
System voltage sense point – Sense point for system voltage. If VAC is outside of the ACUV / ACOV
SYS 32 I operating window, the BATFET will only turn on once the SYS voltage falls below battery voltage
(ideal-diode turn on). When Reverse Mode is enabled, this pin voltage is regulated to VSYS_REV.
Input Voltage Detection and Power – VAC is the input bias to power the IC. Connect a 1-µF capacitor
VAC 33 P
from pin to PGND.
Input Undervoltage Comparator – Connect a resistor divider from VAC to PGND to program the
undervoltage protection. When this pin falls below VREF_ACUV, the device stops charging, disables
ACUV 34 I the ACFETs and enables the BATFET. The hardware limit for input voltage regulation reference is
VACUV_DPM. The actual input voltage regulation is the higher of the pin-programmed value and the
VAC_DPM register value. If ACUV programming is not used, pull this pin to VAC, do not leave floating.
Input Overvoltage Comparator – Connect a resistor divider from VAC to PGND to program the
overvoltage protection. When this pin rises above VREF_ACOV, the device stops charging, disables the
ACOV 35 I
ACFETs and enables the BATFET. If ACOV programming is not used, pull this pin to PGND, do not
leave floating.
Switching Frequency and Synchronization Input – An external resistor is connected to the
FSW_SYNC 36 I FSW_SYNC pin and PGND to set the nominal switching frequency. This pin can also be used to
synchronize the PWM controller to an external clock with 200-kHz to 600-kHz frequency.
Exposed pad beneath the IC – Always solder the thermal pad to the board, and have vias on the
Thermal Pad 37 - thermal pad plane star-connecting to PGND and ground plane for high-current power converter. It also
serves as a thermal pad to dissipate the heat.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VAC, ACUV, ACOV, ACP, ACN, SYS, ACDRV, BATDRV, BATSRC,
Voltage –0.3 85 V
SRP, SRN, FB, FBG
Voltage SW1, SW2 –2 85 V
Voltage SW1, SW2 (40ns transient) –4 85 V
Voltage PG –0.3 40 V
Voltage BATDRV with respect to BATSRC –0.3 12 V
Voltage BTST1, HIDRV1 with respect to SW1 –0.3 14 V
Voltage BTST2, HIDRV2 with respect to SW2 –0.3 14 V
Voltage DRV_SUP, LODRV1, LODRV2 –0.3 14 V
Voltage ACP with respect to ACN, SRP with respect to SRN –0.3 0.3 V
CE, FSW_SYNC, ICHG, ILIM_HIZ, INT, REGN, SCL, SDA, MODE,
Voltage –0.3 6 V
STAT1, STAT2, TS
Output Sink
CE, PG, STAT1, STAT2 5 mA
Current
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/
±500
JEDEC JS-002, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VAC Input voltage 4.2 70 V
VBAT Battery voltage 0 70 V
VDRV_SUP DRV_SUP pin direct drive voltage range 4.0 12 V
FSW Switching Frequency 200 600 kHz
TJ Junction temperature –40 125 °C
TA Ambient temperature –40 105 °C
CVAC VAC capacitor 1 µF
CIN Buck-boost input capacitance (minimum value after derating) 160 µF
COUT Buck-boost output capacitance (minimum value after derating) 160 µF
CREGN REGN capacitor (nominal value before derating) 4.7 µF
CDRV_SUP DRV_SUP capacitor (nominal value before derating) 4.7 µF

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7.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
L Switched Inductor 2.2 15 µH
RDCR Inductor DC resistance 1.75 60 mΩ
RAC_SNS Input current sense resistor 0(1) 2 10 mΩ
RBAT_SNS Battery current sense resistor 5 mΩ
RICHG ICHG programming pulldown resistor 0.0(2) 100 kΩ
RILIM_HIZ ILIM_HIZ programming pulldown resistor 0.0(3) 50 kΩ

(1) When RAC_SNS is 0mΩ, input current limit function is disabled

(2) When RICHG is pulled to GND, the hardware charge current limit is disabled, actual charge current is controlled by the ICHG_REG
register setting
(3) When RILIM_HIZ is pulled to GND, the hardware input current limit is disabled, actual input current is controlled by the IAC_DPM register
setting

7.4 Thermal Information

BQ25750
THERMAL METRIC(1) RRV UNIT
36 PINS
RθJA Junction-to-ambient thermal resistance (JEDEC(1)) 29.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.8 °C/W
RθJB Junction-to-board thermal resistance 9.9 °C/W
ΨJT Junction-to-top characterization parameter 0.2 °C/W
ΨJB Junction-to-board characterization parameter 9.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
Shutdown battery current with VBAT = 28V, VAC = 0V, ADC_EN = 0,
ISD_BAT 10 µA
BATFET off (ISRN + ISRP) FORCE_BATFET_OFF = 1, TJ < 105 °C
VBAT = 28V, VAC = 0V, ADC_EN = 0, TJ <
17 µA
Quiescent battery current with 105 °C
IQ_BAT
BATFET on (ISRN + ISRP) VBAT = 28V, VAC = 0V, ADC_EN = 1, TJ <
500 700 µA
105 °C
IHIZ_VAC HIZ input current (IVAC) EN_HIZ = 1 10 30 µA
IQ_VAC Quiescent input current (IVAC) Not switching 0.75 1 mA
Quiescent battery current in Reverse
IQ_REV Not switching 0.75 1 mA
mode (ISRN + ISRP)
VAC / BAT POWER UP
VVAC_OP VAC operating range 4.2 70 V
VVAC_OK VAC converter enable threshold VAC rising, no battery 4.2 V
VVAC_OKZ VAC converter disable threshold VAC falling, no battery 3.5 V
ACUV comparator threshold to enter
VREF_ACUV VACUV falling 1.095 1.1 1.106 V
VAC_UVP
ACUV comparator threshold
VREF_ACUV_HYS VACUV rising 50 mV
hysteresis
VAC internal threshold to enter
VVAC_INT_OV IN rising 72 74 76 V
VAC_OVP
VAC internal thresholds to exit
VVAC_INT_OVZ IN falling 69 71 73 V
VAC_OVP
ACOV comparator threshold to enter
VREF_ACOV VACOV rising 1.184 1.2 1.206 V
VAC_OVP
ACOV comparator threshold
VREF_ACOV_HYS VACOV falling 50 mV
hysteresis
VSRN_OK Battery voltage to enable BATFET VSRN rising, no input 3.1 V
VSRN_OKZ Battery voltage to disable BATFET VSRN falling, no input 2.15 2.5 V
CHARGE VOLTAGE REGULATION
VVFB_RANGE Feedback voltage range 1.504 1.566 V
VVFB_NOM Nominal feedback voltage VFB_REG = 0x10 1.536 V
TJ = 0°C to 85°C –0.5 0.5 %
VVFB_ACC Feedback voltage regulation accuracy
TJ = -40°C to 125°C –0.7 0.7 %
RFBG FBG resistance to PGND IFBG = 1mA 33 55 Ω
FAST CHARGECURRENT REGULATION
ICHG_REG_RANGE Charge current regulation range 0.4 20 A

RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 55V. 15 A

ICHG_REG = 0x012C –3 3 %

I2Csetting charge current regulation RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 55V. 5 A
ICHG_REG_ACC
accuracy ICHG_REG = 0x0064 –3 3 %

RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 55V. 2 A

ICHG_REG = 0x0028 –5 5 %
Hardware charge current limit set
RBAT_SNS = 5mΩ, RICHG = 10kΩ, 5kΩ, and Ax
KICHG factor (Amperes of charge current per 48 50 52
3.33kΩ kΩ
kΩ on ICHG pin)

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7.5 Electrical Characteristics (continued)

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICHG pin voltage when ICHG pin is in
VREF_ICHG 2.0 V
regulation
PRE-CHARGE CURRENT REGULATION
IPRECHG_RANGE Precharge current regulation range VFB < VBAT_LOWV * VVFB_REG 0.25 10 A

RBAT_SNS = 5mΩ, VFB < VBAT_LOWV * 3.0 A

VVFB_REG. IPRECHG = 0x003C –4 4 %

I2C setting precharge current RBAT_SNS = 5mΩ, VFB < VBAT_LOWV * 1.0 A
IPRECHG_ACC
accuracy VVFB_REG. IPRECHG[1:0] = 0x0014 –10 10 %

RBAT_SNS = 5mΩ, VFB < VBAT_LOWV * 0.50 A

VVFB_REG. IPRECHG[1:0] = 0x000A –30 30 %
CHARGE TERMINATION
ITERM_RANGE Termination current range VFB = VVFB_REG 0.25 10 A

RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 1.5 A

55V . ITERM = 0x001E –7 7 %

RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 55V. 0.50 A

ITERM_ACC Termination current accuracy
ITERM = 0x000A –20 20 %

RBAT_SNS = 5mΩ, VBAT = 12V, 36V, 55V. 0.250 A

ITERM = 0x0005 –50 50 %
BATTERY VOLTAGE COMPARATORS
Trickle charge to pre-charge transition VSRN rising 2.8 3 3.2 V
VBAT_SHORT
Pre-charge to trickle charge transition VSRN falling 2.2 2.4 2.6 V
VFB rising, as percentage of VFB_REG,
69.0 71.7 73.8 %
VBAT_LOWV[2:0] = 3
VFB rising, as percentage of VFB_REG,
64.3 66.7 69.0 %
VBAT_LOWV[2:0] = 2
VBAT_LOWV Pre-charge to fast-charge transition
VFB rising, as percentage of VFB_REG,
52 55 58 %
VBAT_LOWV[2:0] = 1
VFB rising, as percentage of VFB_REG,
27 30 33 %
VBAT_LOWV[2:0] = 0
VBAT_LOWV_HYS BAT_LOWV hysteresis 5 %
VFB falling, as percentage of VFB_REG,
97.6 %
VRECHG[1:0] = 3
VFB falling, as percentage of VFB_REG,
95.2 %
Battery recharge threshold for Li-Ion VRECHG[1:0] = 2
VRECHG
and LiFePO4 VFB falling, as percentage of VFB_REG,
94.3 %
VRECHG[1:0] = 1
VFB falling, as percentage of VFB_REG,
93.0 %
VRECHG[1:0] = 0
INPUT CURRENT REGULATION
20 A
RAC_SNS = 2mΩ, IAC_DPM = 0x00A0
–3 3 %

I2Csetting input current regulation 10 A

IIREG_DPM_ACC RAC_SNS = 2mΩ, IAC_DPM = 0x0050
accuracy in forward mode –4 4 %
5.0 A
RAC_SNS = 2mΩ, IAC_DPM = 0x0028
–7 7 %

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7.5 Electrical Characteristics (continued)

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Hardware input current limit set factor
RAC_SNS = 2mΩ, RILIM = 5kΩ, 2.5kΩ, and Ax
KILIM (Amperes of input current per kΩ on 48 50 52
1.67kΩ kΩ
ILIM_HIZ pin)
ILIM_HIZ pin voltage when ILIM_HIZ
VREF_ILIM_HIZ 2.0 V
pin is in regulation
ILIM_HIZ input high threshold to enter
VIH_ILIM_HIZ VILIM_HIZ rising 3.7 V
HIZ mode
INPUT VOLTAGE REGULATION
VVREG_DPM_RANGE Input voltage DPM regulation range 4.2 65 V

I2Csetting input voltage regulation 38 V

VVREG_DPM_ACC VAC_DPM = 0x076C
accuracy –2 2 %
25 V
VAC_DPM = 0x04E2
I2Csetting input voltage regulation –2 2 %
VVREG_DPM_ACC
accuracy in forward mode 19 V
VAC_DPM = 0x03B6
–2 2 %
ACUV pin voltage when in VDPM
VACUV_DPM 1.198 1.210 1.222 V
regulation
REVERSE MODE VOLTAGE REGULATION
SYS Voltage regulation range in
VREV_RANGE 3.3 65 V
Reverse mode
48 V
VSYS_REV = 0x0960
Voltage regulation accuracy in –2 2 %
VREV_ACC
Reverse mode 28 V
VSYS_REV = 0x0578
–2 2 %
15 V
VSYS_REV = 0x02EE
VAC Voltage regulation accuracy in –2 2 %
VREV_ACC
Reverse mode 5 V
VSYS_REV = 0x00FA
–2 2 %
REVERSE MODE CURRENT REGULATION
20 A
RAC_SNS = 2mΩ, IAC_REV = 0x00A0
Input current regulation accuracy in –3.5 3.5 %
IIREV_ACC
Reverse mode 5.0 A
RAC_SNS = 2mΩ, IAC_REV = 0x0028
–5.5 5.5 %
CHARGE MODE BATTERY-PACK NTC MONITOR
TS pin voltage rising T1 threshold, As Percentage to REGN, TS_T1=0°C w/
VT1_RISE 72.75 73.25 73.85 %
charge suspended above this voltage. 103AT
TS pin voltage falling T1 threshold, As Percentage to REGN, TS_T1=0°C w/
VT1_FALL 71.5 72 72.5 %
charge re-enabled below this voltage. 103AT
TS pin voltage rising T2 threshold,
As Percentage to REGN, TS_T2=10°C w/
VT2_RISE charge back to reduced ICHG above 67.75 68.25 68.75 %
103AT
this voltage
TS pin voltage falling T2 threshold.
As Percentage to REGN, TS_T2=10°C w/
VT2_FALL Charge back to normal below this 66.45 66.95 67.45 %
103AT
voltage
TS pin voltage falling T3 threshold,
As Percentage to REGN, TS_T3=45°C w/
VT3_FALL charge to ICHG and reduced VFB_REG 44.25 44.75 45.25 %
103AT
below this voltage.

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7.5 Electrical Characteristics (continued)

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TS pin voltage rising T3 threshold.
As Percentage to REGN, TS_T3=45°C w/
VT3_RISE Charge back to normal above this 45.55 46.05 46.55 %
103AT
voltage.
TS pin voltage falling T5 threshold, As Percentage to REGN, TS_T5=60°C w/
VT5_FALL 33.875 34.375 34.875 %
charge suspended below this voltage 103AT
TS pin voltage rising T5 threshold.
As Percentage to REGN, TS_T5=60°C w/
VT5_RISE Charge back to ICHG and reduced 35 35.5 36 %
103AT
VFB_REG above this voltage.
REVERSE MODE BATTERY-PACK NTC MONITOR
TS pin voltage rising TCOLD
As Percentage to REGN (BCOLD = –20°C
VBCOLD_RISE threshold. Reverse mode suspended 79.45 80.0 80.55 %
w/ 103AT)
above this voltage
TS pin voltage rising TCOLD
As Percentage to REGN (BCOLD = –10°C
VBCOLD_RISE threshold. Reverse mode suspended 76.65 77.15 77.65 %
w/ 103AT)
above this voltage
VBCOLD_FALL TCOLD comparator falling threshold. As Percentage to REGN (–20°C w/ 103AT) 78.2 78.7 79.2 %
VBCOLD_FALL TCOLD comparator falling threshold. As Percentage to REGN (–10°C w/ 103AT) 75.5 75.6 76.5 %
TS pin voltage falling THOT
As Percentage to REGN, (BHOT = 55°C w/
VBHOT_FALL threshold. Reverse mode suspends 37.2 37.7 38.2 %
103AT)
below this voltage
TS pin voltage falling THOT
As Percentage to REGN, (BHOT = 60°C w/
VBHOT_FALL threshold. Reverse mode suspends 33.875 34.375 34.875 %
103AT)
below this voltage
TS pin voltage falling THOT
As Percentage to REGN, (BHOT 65°C w/
VBHOT_FALL threshold. Reverse mode suspends 30.75 31.25 31.75 %
103AT)
below this voltage
TS pin voltage rising THOT threshold.
As Percentage to REGN, (BHOT = 55°C w/
VBHOT_RISE Reverse mode allowed above this 38.5 39.0 39.95 %
103AT)
voltage
TS pin voltage rising THOT threshold.
As Percentage to REGN, (BHOT = 60°C w/
VBHOT_RISE Reverse mode allowed above this 35 35.5 36 %
103AT)
voltage
TS pin voltage rising THOT threshold.
As Percentage to REGN, (BHOT 65°C w/
VBHOT_RISE Reverse mode allowed above this 32.0 32.5 33.0 %
103AT)
voltage
BATTERY CHARGER PROTECTION
VBAT_OV Battery overvoltage threshold VFB rising, as percentage of VFB_REG 102.5 104 105.5 %
VBAT_OVZ Battery overvoltage falling threshold VFB falling, as percentage of VFB_REG 100.5 102 103.5 %
VICHG_OC Battery charge over-current threshold VSRP - VSRN rising 120 170 mV
THERMAL SHUTDOWN
Thermal shutdown rising threshold Temperature increasing 150 °C
TSHUT
Thermal shutdown falling threshold Temperature decreasing 135 °C
REGN REGULATOR AND GATE DRIVE SUPPLY (DRV_SUP)
IREGN = 20mA 4.8 5 5.2 V
VREGN REGN LDO output voltage
VAC = 5V, IREGN = 20mA 4.35 4.6 V
IREGN REGN LDO current limit VREGN = 4.5V 70 mA
REGN OK threshold to allow
VREGN_OK REGN rising 3.55 V
switching
DRV_SUP under-voltage threshold to
VDRV_UVPZ DRV_SUP rising 3.7 V
allow switching

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7.5 Electrical Characteristics (continued)

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRV_SUP over-voltage threshold to
VDRV_OVP DRV_SUP rising 12.8 13.2 13.6 V
disable switching
POWER-PATH MANAGER
VACDRV_REG ACFET drive voltage VACDRV - VVAC, IACDRV = 10µA 10 V
IACDRV_ON ACFET charge pump current limit VACDRV - VVAC = 5V 40 µA
IACDRV_OFF ACFET turnoff current 3 mA
VBATDRV - VBATSRC, VAC = 0V, IBATDRV =
VBATDRV_REG BATFET drive voltage 10 V
10µA
IBATDRV_REG BATFET charge pump current limit VBATDRV - VBATSRC = 5V, VAC = 0V 40 µA
IBATDRV_OFF BATFET turnoff current 400 µA
IAC_LOAD VAC discharge load current 16 mA
IBAT_LOAD Battery (SRN) discharge load current 16 mA
SWITCHING FREQUENCY AND SYNC
RFSW_SYNC = 133kΩ 212 250 288 kHz
fSW Switching Frequency
RFSW_SYNC = 50kΩ 425 500 575 kHz
VIH_SYNC FSW_SYNC input high threshold 1.3 V
VIL_SYNC FSW_SYNC input low threshold 0.4 V
PWSYNC FSW_SYNC input pulse width 80 ns
PWM DRIVERS
RHIDRV1_ON Buck side high-side turnon resistance VBTST1 - VSW1 = 5V 3.4 Ω
RHIDRV1_OFF Buck side high-side turnoff resistance VBTST1 - VSW1 = 5V 1.0 Ω
Bootstrap refresh comparator BTST1 falling, VBTST1 - VSW1 when low-side
VBTST1_REFRESH 2.7 3.1 3.9 V
threshold voltage refresh pulse is requested
RLODRV1_ON Buck side low-side turnon resistance VREGN = 5V 3.4 Ω
RLODRV1_OFF Buck side low-side turnoff resistance VREGN = 5V 1.0 Ω
tDT1 Buck side dead time, both edges 45 ns
Boost side high-side turnon
RHIDRV2_ON VBTST2 - VSW2 = 5V 3.4 Ω
resistance
Boost side high-side turnoff
RHIDRV2_OFF VBTST2 - VSW2 = 5V 1.0 Ω
resistance
Bootstrap refresh comparator BTST2 falling, VBTST2 - VSW2 when low-side
VBTST2_REFRESH 2.7 3.1 3.9 V
threshold voltage refresh pulse is requested
RLODRV2_ON Boost side low-side turnon resistance VREGN = 5V 3.4 Ω
RLODRV2_OFF Boost side low-side turnoff resistance VREGN = 5V 1.0 Ω
tDT2 Boost side dead time, both edges 45 ns
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC_SAMPLE[1:0] = 00 24 ms
tADC_CONV Conversion-time, each measurement ADC_SAMPLE[1:0] = 01 12 ms
ADC_SAMPLE[1:0] = 10 6 ms
ADC_SAMPLE[1:0] = 00 14 15 bits
ADCRES Effective resolution ADC_SAMPLE[1:0] = 01 13 14 bits
ADC_SAMPLE[1:0] = 10 12 13 bits
ADC MEASUREMENT RANGE AND LSB

Input current ADC reading (positive or Range with 2mΩ RAC_SNS –50000 50000 mA
IAC_ADC
negative) LSB with 2mΩ RAC_SNS 2 mA

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7.5 Electrical Characteristics (continued)

VAC = ACP = ACN = SYS = SRP = SRN = 28V, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Battery current ADC reading (positive Range with 5mΩ RBAT_SNS –20000 20000 mA
IBAT_ADC
or negative) LSB with 5mΩ RBAT_SNS 2 mA
Range 0 65534 mV
VAC_ADC Input voltage ADC reading
LSB 2 mV
Range 0 65534 mV
VBAT_ADC Battery voltage ADC reading
LSB 2 mV
Range 0 65534 mV
VSYS_ADC System voltage ADC reading
LSB 2 mV

TS voltage ADC reading, as Range 0 99.9 %

TSADC
percentage of REGN LSB 0.098 %
Range 0 2047 mV
VFB_ADC FB voltage ADC reading
LSB 1 mV
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level 1.3 V
VIL Input low threshold level 0.4 V
VOL Output low threshold level Sink current = 5mA 0.4 V
IIN_BIAS High-level leakage current Pull up rail 3.3V 1 µA
LOGIC I/O PIN (CE, PG , STAT1, STAT2)
VIH Input high threshold level (CE) 1.3 V
Output low threshold level (CE, PG,
VOL Sink current = 5mA 0.4 V
STAT1, STAT2)
VIL Input low threshold level (CE) 0.4 V
High-level leakage current (CE, PG,
IOUT_BIAS Pull up rail 3.3V 1 µA
STAT1, STAT2)

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7.6 Timing Requirements

MIN NOM MAX UNIT
VAC / BAT POWER UP
tACOV_DGL Enter ACOV deglitch time, ACOV rising 100 µs
tACOVZ_DGL Exit ACOV deglitch time, ACOV falling 12 ms
tACUV_DGL Enter ACUV deglitch time, ACUV falling 100 µs
tACUVZ_DGL Exit ACUV deglitch time, ACUV rising 12 ms
BATTERY CHARGER
Deglitch time for charge termination, VSRP - VSRN
tTERM_DGL 220 ms
falling
tRECHG_DGL Deglitch time for recharge threshold, VFB falling 200 ms
tPRECHG Pre-charge safety timer accuracy 1.7 2 2.3 hr
tSAFETY Fast-charge safety timer accuracy, CHG_TMR = 8hr 6.8 8 9.2 hr
tTOPOFF Top-off timer accuracy, TOPOFF_TMR = 30 min 25.5 30 34.5 min
tCV_TIMER CV timer accuracy, CV_TMR = 10hr 8.5 10 11.5 hr
BATTERY-PACK NTC MONITOR
tTS_DGL Deglitch time for TS threshold crossing 25 ms
MPPT TIMERS
Full Panel Sweep timer accuracy, FULL_SWEEP_TMR
tFULL_SWEEP 8.5 10 11.5 min
= 10 min
I2C INTERFACE
fSCL SCL clock frequency 1000 kHZ
DIGITAL CLOCK AND WATCHDOG
I2C Watchdog reset time (EN_HIZ = 1,
tLP_WDT 100 160 s
WATCHDOG[1:0] = 160s)
I2C Watchdog reset time (EN_HIZ = 0,
tWDT 130 160 s
WATCHDOG[1:0] = 160s)

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7.7 Typical Characteristics (BQ25750)

CVAC = 160 µF, COUT= 160 µF, fSW = 250 kHz, L = 10 μH, TA = 25°C (unless otherwise specified)

100 100
98 98
96 96
94 94
Efficiency (%)

Efficiency (%)
92 92
90 90
88 5VIN 88 5VIN
15VIN 15VIN
86 20VIN 86 20VIN
24VIN 24VIN
84 36VIN 84 36VIN
82 48VIN 82 48VIN
60VIN 60VIN
80 80
0 2 4 6 8 10 12 14 0 1 2 3 4 5 6 7 8 9 10
Charging Current (A) Charging Current (A)
VBAT = 20 V VBAT = 28 V
Figure 7-1. Charge Efficiency vs Charge Current (5s battery Figure 7-2. Charge Efficiency vs Charge Current (7s battery
configuration) configuration)
100 0.5
20Vin, 29.2Vbat
98 0.4 28Vin, 29.2Vbat
96 0.3 36Vin, 29.2Vbat

94 0.2
Efficiency (%)

Accuracy (%)

92 0.1
90 0
88 5VIN -0.1
15VIN
86 20VIN -0.2
24VIN
84 36VIN -0.3
82 48VIN
60VIN -0.4
80 -0.5
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -40 -25 -10 5 20 35 50 65 80
Charging Current (A) Temperature ( C)
VBAT = 38 V Figure 7-4. Charge Voltage Accuracy vs Temperature
Figure 7-3. Charge Efficiency vs Charge Current (10s battery
configuration)

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7.7 Typical Characteristics (BQ25750) (continued)

CVAC = 160 µF, COUT= 160 µF, fSW = 250 kHz, L = 10 μH, TA = 25°C (unless otherwise specified)

5 0.50
20Vin, 27Vbat IQ_BAT
4 28Vin, 27Vbat 0.45 IQ_VAC
3 36Vin, 27Vbat 0.40
2 0.35
Accuracy (%)

Current (mA)
1 0.30
0 0.25
-1 0.20
-2 0.15
-3 0.10
-4 0.05
-5 0.00
-40 -25 -10 5 20 35 50 65 80 -40 -20 0 20 40 60 80 100 120
Temperature ( C) Temperature ( C)
ICHG = 5 A IQ_BAT: VAC = 0 V IQ_VAC: VAC = 20 V EN_HIZ = 1
Figure 7-5. Charge Current Accuracy vs Temperature Figure 7-6. Battery and Input Quiescent Current vs Temperature
with VBAT = 28 V
2 5
VINPM = 19V 20Vin, 28Vbat
VINPM = 34V 4 28Vin, 28Vbat
3 36Vin, 28Vbat
1
2
Accuracy (%)
Accuracy (%)

1
0 0
-1
-2
-1
-3
-4
-2 -5
-40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80
Temperature ( C) Temperature ( C)
VBAT = 28 V IAC_DPM = 3 A
Figure 7-7. Input Voltage (VAC_DPM) Regulation Accuracy vs Figure 7-8. Input Current (IAC_DPM) Regulation Accuracy vs
Temperature Temperature
100 100
98 98
96 96
94 94
Efficiency (%)

Efficiency (%)

92 92
90 90
88 88
5VSYS_REV 5VSYS_REV
86 9VSYS_REV 86 9VSYS_REV
15VSYS_REV 15VSYS_REV
84 20VSYS_REV 84 20VSYS_REV
82 36VSYS_REV 82 36VSYS_REV
48VSYS_REV 48VSYS_REV
80 80
0 20 40 60 80 100 120 140 160 180 200 220 240 0 20 40 60 80 100 120 140 160 180 200 220 240
Reverse Mode Output Power (W) Reverse Mode Output Power (W)
VBAT = 20 V VBAT = 28 V
Figure 7-9. Reverse Mode Efficiency (5s battery configuration) Figure 7-10. Reverse Mode Efficiency (7s battery configuration)

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7.7 Typical Characteristics (BQ25750) (continued)

CVAC = 160 µF, COUT= 160 µF, fSW = 250 kHz, L = 10 μH, TA = 25°C (unless otherwise specified)

100 3
19VBAT
98 27VBAT
2 38VBAT
96
94
1
Efficiency (%)

Accuracy (%)
92
90 0
88
5VSYS_REV -1
86 9VSYS_REV
15VSYS_REV
84 20VSYS_REV -2
82 36VSYS_REV
48VSYS_REV
80 -3
0 20 40 60 80 100 120 140 160 180 200 220 240 5 10 15 20 25 30 35 40 45 50
Reverse Mode Output Power (W) Reverse Mode Regulation Voltage Setting (V)
VBAT = 38 V Figure 7-12. Reverse Mode Output Voltage Accuracy vs
VAC_REV Setting
Figure 7-11. Reverse Mode Efficiency (10s battery
configuration)

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8 Detailed Description
8.1 Overview
The BQ25750 is a wide input voltage, Li-Ion, Li-polymer, and LiFePO4 switched-mode buck-boost battery
charge controller with direct power path control. The device offers high-efficiency battery charging over a wide
voltage range with accurate and programmable charge current and charge voltage regulation, in addition to
automatic charge preconditioning, termination, and charge status indication. The device integrates all the loop
compensation and 5-V gate drivers for the buck-boost converter, thereby providing a high density solution
with ease of use. The switching frequency of the device can be programmed or forced to follow an external
clock frequency via the FSW_SYNC pin. While switching under light-load the device offers an optional Pulse
Frequency Modulation (PFM) mode to increase efficiency. The charger has a digital state machine that advances
the charger's states as the converter analog feedback loops hand off control to each other. It also manages the
fault protection comparators. The loops regulate and comparators compare against reference values in the I2C
registers, unless clamped by external resistors.
Besides the I2C host-controlled charging mode, the device also supports autonomous charging mode via resistor
programmable limits. Input current, charge current and charge voltage regulation targets can be changed via
the ILIM_HIZ, ICHG, and FB pins, respectively. The device can complete a charging cycle without any software
intervention. Charging function is controlled via the CE pin.
For Li-Ion and LiFePO4 chemistries, the device checks battery voltage and charges the battery in different
phases accordingly: trickle charging, pre-charging, constant current (CC) charging and constant voltage (CV)
charging. At the end of the charging cycle, the charger automatically terminates when the charge current is
below the termination current limit in the constant voltage phase. When the full battery falls below the recharge
threshold, the charger automatically starts a new charge cycle.
The input operating window is programmed via the ACUV and ACOV pins. When the input voltage is outside
the programmed window, the device automatically stops the charger, transitions to power the system load from
the battery, and the PG pin pulls HIGH. In the absence of an input source, the device can power the system
load from battery through BATFET or via reverse power flow, discharging the battery through the buck-boost
converter to generate a programmable, regulated voltage on system which is above or below the battery voltage.
The charger provides various safety features for battery charging and system operation, including battery
temperature negative thermistor (NTC) monitoring, charge timers and over-voltage/over-current protections on
battery and input. The thermal shutdown prevents charging when the junction temperature exceeds the TSHUT
limit.
The device has three status pins (STAT1, STAT2, and PG) to indicate the charging status and input voltage
status. These pins can be used to drive LEDs or communicate with a host processor. If needed, these pins can
also be used as general purpose indicators and their status controlled directly by the I2C interface. In addition,
the CE pin can also be used as a general purpose indicator. The INT pin immediately notifies host when the
device status changes, including faults.
The device also provides a 16-bit analog-to-digital converter (ADC) for monitoring input current, charge current
and input/battery/system/thermistor voltages (IAC, IBAT, VAC, VBAT, VSYS, TS).
The device comes with a 36-pin 5-mm × 6-mm QFN package with 0.5-mm pin pitch.

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8.2 Functional Block Diagram

VACDRV_REG
VAC VSRN
VACOV ACDRV
ACOV + VAC_OVP EN_ACFET VAC
VREF_ACOV EN_BATFET POWER-PATH
MANAGER VBATDRV_REG
REGN REGN
VACUV
ACUV VAC_UVP LDO BATDRV
VREF_ACUV + HIZ_MODE
BATSRC

REGN

IAC IBAT BQ25750

VILIM_HIZ
ILIM_HIZ
VICHG REGN VDRV_SUP
ICHG DRV_SUP

VO,REF
SRP + IBAT VICHG
– – VFB BTST1
+ BAT_OVP
SRN – ICHG_REG VREF_ICHG VBAT_OV
+ + HIDRV1
ACP + IBAT
IAC VILIM_HIZ + BAT_OCP
– – VICHG_OC SW1
ACN – IAC_DPM VREF_ILIM_HIZ
+ + VDRV_SUP DRV_SUP
+ DRV_OVP
VFB VACUV VDRV_OVP
FB – – LODRV1
VFB_REG VACUV_DPM VDRV_SUP
DRV_UVP BUCK-BOOST
+ + VDRV_UVP CONTROLLER
+
VSYS VAC VSYS
SYS + + SYS_OVP BTST2
+
VSYS_REV VAC_DPM VSYS_REV_OV
– – HIDRV2

HIZ_MODE SW2
VFB_REG DRV_SUP
EN_CHARGE
ICHG_REG
EN_PFM
IAC_DPM
EN_REVERSE
VAC_DPM CONVERTER LODRV2
REF EN_ACFET
VSYS_REV CONTROL
DAC EN_BATFET
IAC_REV
VILIM_HIZ
VREF_ICHG IC_TJ
TSHUT +
VACUV_DPM TSHUT CLK
VREF_ILIM_HIZ OSCILLATOR FSW_SYNC
SYNC_DET
IAC
IBAT
SCL ADC VAC
VBAT
SDA I2C VSYS
VTS
VFB_REG

INT VRECHG MODE
RECHRG +
CE VFB
PG IBAT
TERMINATION + PGND
STAT2 ITERM
STAT1 CHARGE VBAT_LOWV
BAT_LOWV +
CONTROL VFB
FBG

STATUS VBAT_SHORT
BAT_SHORT +
PIN VBAT BATTERY
VTS
CNTRL THERMISTOR TS
TS_SUSPEND
SENSING

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8.3 Feature Description

8.3.1 Device Power-On-Reset
The internal bias circuits are powered from either VAC or SRN. When VAC rises above VVAC_OK, the ACFET
driver is active and charging is allowed. When BAT rises above 3 V, the BATFET driver is active, and reverse
mode operation is allowed.
A POR occurs when one of these supplies rises above its corresponding VOK level, while the other supply is
below its corresponding VOK level. After the POR, I2C interface is ready for communication and all the registers
are reset to default value. The host can access all the registers after POR.
8.3.2 Device Power-Up From Battery Without Input Source
If only battery is present and the voltage is above VSRN_OK threshold, the BATFET turns on and connects battery
to system. The REGN LDO stays off to minimize the quiescent current. The N-type driver allows for use of
low RDS,ON external BATFET, minimizing the conduction loss. The low quiescent current on BAT maximizes the
battery run time. The ADC can be used to monitor discharge current through SRP and SRN pins. The BATFET
can be forced to turn off via the FORCE_BATFET_OFF register bit.
8.3.3 Device Power Up from Input Source
When a valid input source (VVAC_OK < VAC and VAC within the ACUV and ACOV operating window) is detected,
the ACFET turns on to connect the input to the system, and the PG pin pulls LOW. If charging is enabled, the
device proceeds to enable the REGN LDO and power up the buck-boost converter.
8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
The VAC operating window can be programmed via the ACUV and ACOV pins using a three-resistor divider
from VAC to PGND as shown in Figure 8-1.

INPUT
VAC

RAC1
ACUV
RAC2
ACOV
RAC3

Figure 8-1. ACUV and ACOV Programming

When VACUV falls and reaches VACUV_DPM, the device enters input voltage regulation, thereby reducing the
charge current. VACUV continues falling below VREF_ACUV, the device automatically stops the converter, turns off
the ACFET, turns on the BATFET and the PG pin pulls high.
System Note: if VAC_DPM register is programmed to a value higher than POR, the device regulates the
VAC voltage to the higher of VAC_DPM register or VACUV_DPM pin voltage. Refer to Section 8.3.5.1.2 for more
information.
When VACOV rises above VREF_ACOV, the device automatically stops the converter, turns off the ACFET, turns on
the BATFET and the PG pin pulls high.
The following equations govern the relationship between the resistor divider and the target operating voltage
window programmed by ACOV and ACUV pins:

R +R + RAC3
VACOV_TARGET = VREF_ACOV × AC1 RAC2 (1)
AC3

R + RAC2 + RAC3
VACUV_TARGET = VREF_ACUV × AC1
R +R (2)
AC2 AC3

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If unused, tie ACUV to VAC and ACOV to PGND in order to apply the internal VAC operating window (VVAC_OP).
8.3.3.2 REGN Regulator (REGN LDO)
The REGN LDO regulator provides a regulated bias supply for the IC and the TS external resistors. Additionally,
REGN voltage can be used to drive the buck-boost switching FETs directly by tying the DRV_SUP pin to REGN.
The pull-up rail of PG, STAT1, and STAT2 can be connected to REGN as well. The REGN LDO is enabled when
below conditions are valid:
1. VAC voltage above VVAC_OK and charge is enabled in forward mode.
2. BAT voltage above 3 V in Reverse mode and Reverse Mode is enabled (EN_REV = 1)
At high input voltages and/or large gate drive requirements, the power loss from gate driving via the REGN LDO
can be excessive. This power for the gate drivers can be provided externally by directly driving the DRV_SUP
pin with a high efficiency supply ranging from 4.5 V to 12 V. This supply should be able to provide at least 50 mA
or more as required to drive the switching FET gate charge.
The power dissipation for driving the gates via the REGN LDO is: PREGN = VAC − VREGN × QG TOT 1,2, 3,4 × f SW ,
where QG(TOT)1,2,3,4 is the sum of the total gate charge for all switching FETs and fSW is the programmed
switching frequency. The Safe Operating Area (SOA) below is based on a 1-W power loss limit.
80

70

60
Input Voltage (V)

50

40

30

20

10

0
0 10 20 30 40 50 60 70 80 90 100
QG(TOT)1,2,3,4 x fSW (mA)

Figure 8-2. REGN LDO Safe Operating Area (SOA)

8.3.3.3 Compensation-Free Buck-Boost Converter Operation

The device integrates all the loop compensation, thereby providing a high density solution with ease of use. At
startup, the device toggles the SW node for about 40 ms to determine the correct compensation values for a
given set of passives. If the battery is above VBAT_LOWV, then SW2 is toggled. SW1 is toggled otherwise.
The charger employs a synchronous buck-boost converter that allows charging from a wide range of input
voltage sources. The charger operates in buck, buck-boost or boost mode. The converter can operate
uninterruptedly and continuously across the three operation modes. During buck-boost mode, the converter
alternates a SW1 pulse with a SW2 pulse, with effective switching frequency interleaved among these pulses for
highest efficiency operation.
During boost mode operation, the HS FET is forced to turn on for 225 ns in each switching cycle to ensure
inductor energy is delivered to the output, effectively limiting the maximum boosting ratio. For example, when
device is configured to switch at 500 kHz, the switching period is 2 μs, yielding a duty cycle limit of (1 - 0.225
μs/2 μs) = 88.75%. Given a 5-V input, this translates to a maximum 44-V output assuming 100% efficiency. The
true output will be lower than this ideal limit. At lower switching frequencies, the maximum duty cycle increases,
making the limitation less significant.

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Table 8-1. Switching MOSFET Operation

MODE BUCK BUCK-BOOST BOOST
Switching (fSW interleaved
HS BUCK FET Switching at fSW ON
between SW1 and SW2)
Switching (fSW interleaved
LS BUCK FET Switching at fSW OFF
between SW1 and SW2)
Switching (fSW interleaved
LS BOOST FET OFF Switching at fSW
between SW1 and SW2)
Switching (fSW interleaved
HS BOOST FET ON Switching at fSW
between SW1 and SW2)

8.3.3.3.1 Light-Load Operation

In order to improve converter light-load efficiency, the device switches to Pulse Frequency Modulation (PFM)
control at light load when the EN_PFM bit is set to 1. The effective switching frequency will decrease accordingly
when output load decreases.
EN_PFM bit is automatically cleared to 0 every time the converter starts and a valid SYNC clock input is
detected on the FSW_SYNC pin, thereby ensuring fixed frequency operation regardless of output current. The
bit can be overwritten to 1 to allow PFM after startup even when SYNC signal is present.
Light-load PFM mode can be disabled by clearing the EN_PFM bit. In this case, the device switches in PWM
mode at a fixed switching frequency. It is recommended to disable PFM mode (EN_PFM = 0) when termination
is enabled and set lower than 2 A.
8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
The device switching frequency can be programmed between 200 kHz to 600 kHz using a resistor from the
FSW_SYNC pin to PGND. The RFSW resistor is related to the nominal switching frequency (fSW) by the equation:

1
RFSW = (3)
10 × f SW × 5 × 10−12 − 500 × 10−9

This pin must be pulled to PGND using a RFSW, do not leave floating. In addition to programming the nominal
switching frequency, the FSW_SYNC pin can also be used to synchronize the internal oscillator to an external
clock signal. The synchronization feature works over the same range as the switching frequency: 200-kHz to
600-kHz range.
Table 8-2. Common RFSW and Switching Frequency Values
RFSW (kΩ) SWITCHING FREQUENCY (kHz)

200 200

133 250

100 300

80 350

66.67 400

57.1 450

50 500

44.4 550

40 600

8.3.3.5 Device HIZ Mode

When a valid input supply is present, it is possible to force the device into HIZ Mode which disables switching,
disables REGN LDO, turns off the ACFET, turns on the BATFET. The system load is provided by the battery in

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this mode. The device draws less than IHIZ_VAC from the input supply in this mode. The charger enters HIZ Mode
when EN_HIZ bit is set to 1 or the ILIM_HIZ pin is pulled above VIH_ILIM_HIZ (refer to Section 8.3.5.1.1.1).
If the device is operating in reverse mode with the converter turned on, and the device enters HIZ mode
(EN_HIZ bit is set to 1 or ILIM_HIZ pin is pulled above VIH_ILIM_HIZ), switching stops and the system load is
provided by the battery through the BATFETs. Once HIZ mode condition is cleared by the host, the device
resumes reverse mode operation, powering the system through the converter with the BATFET off.
The device exits HIZ Mode when the EN_HIZ bit is cleared to 0 and the ILIM_HIZ pin is pulled below 0.4 V.
8.3.4 Battery Charging Management
The device charges 1-cell up-to 14-cell Li-Ion batteries and 1-cell up-to 16-cell LiFePO4 batteries. The charge
cycle is autonomous and requires no host interaction.
8.3.4.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG bit =1 and CE pin is LOW), the device autonomously completes
a charging cycle without host involvement. The device charging parameters can be set by hardware through
the FB pin to set regulation voltage and the ICHG pin to set charging current. The host can always control the
charging operation and optimize the charging parameters by writing to the corresponding registers through I2C.
Table 8-3. Li-Ion & LiFePO4 Charging Parameter Default Settings
PARAMETER VALUE
Precharge → Fast Charge (CC) → Taper Charge (CV) →
Charge Stages
Termination → Recharge
FB Voltage Regulation Target (VFB_REG) 1.536 V
Battery Low Voltage (VBAT_LOWV ) 66.7% x VFB_REG = 1.0245 V
Recharge Voltage (VRECHG) 97.6% x VFB_REG =1.4991 V
Charging Current HW Limit (ICHG pin) ICHG = KICHG / RICHG
Pre-Charge Current HW Limit (ICHG pin) 20% x ICHG
Termination Current HW Limit (ICHG pin) 10% x ICHG
CV Timer Disabled
NTC Temperature Profile JEITA
Safety Timer 12 hours

A new charge cycle starts when the following conditions are valid:
• VAC is within the ACUV and ACOV operating window
• Device is not in HIZ mode (EN_HIZ = 0 and ILIM_HIZ pin voltage is below VIH_ILIM_HIZ)
• REGN is above VREGN_OK
• Battery charging is enabled (EN_CHG = 1 and CE pin is LOW )
• No thermistor fault on TS
• No safety timer fault
For lithium-ion battery charging, the charger device automatically terminates the charging cycle when the
charging current is below termination threshold, charge voltage is above recharge threshold, and device is
not in DPM mode. When a full battery voltage is discharged below recharge threshold (threshold selectable via
VRECHG[1:0] bits), the device automatically starts a new charging cycle. After the charge is done, toggle either
CE pin or EN_CHG bit can initiate a new charging cycle. In addition, the device offers a dedicated CV timer to
stop the charging after a programmable period (CV_TMR bits) in CV mode, regardless of the charge current
value.
The status register (CHARGE_STAT) indicates the different charging phases as:
• 000 – Not Charging
• 001 – Trickle Charge (VFB < VBAT_SHORT)
• 010 – Pre-charge (VBAT_SHORT < VFB < VBAT_LOWV)

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• 011 – Fast-charge (CC mode)

• 100 – Taper Charge (CV mode)
• 101 – Reserved
• 110 – Top-off Timer Active Charging
• 111 – Charge Termination Done
When the charger transitions to any of these states, including when charge cycle is completed, an INT pulse is
asserted to notify the host.
Supercapacitors do not require Trickle Charge or Pre-charge regions when their voltage is low. For
supercapacitor charging, setting the EN_PRECHG bit to 0 can disable both of these charging regions. In this
case, the charger outputs ICHG current as long as the feedback voltage (VFB) is below VFB_REG. The following
settings are recommended for supercapacitor charging:
• EN_PRECHG = 0
• EN_TERM = 0
• EN_CHG_TMR = 0
8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
There are two distinct thresholds to limit the charge current (if both are enabled, the lowest limit of these will
apply):
1. ICHG pin pull down resistor (hardware control)
2. ICHG_REG register bits (host software control)
To set the maximum charge current using the ICHG pin, a pull-down resistor to PGND is used. It is required to
use a 5-mΩ RBAT_SNS sense resistor. The charge current limit is controlled by:

K
ICHG_MAX = RICHG (4)
ICHG

The precharge current limit is defined as IPRECHG_MAX = 20% x ICHG_MAX, and the termination current is ITERM =
10% x ICHG_MAX.
The actual charge current limit is the lower value between ICHG pin setting and I2C register setting
(ICHG_REG). For example, if the register setting is 10 A (0xC8), and ICHG pin has a 10-kΩ resistor (KICHG
= 50 A-kΩ) to ground for 5 A, the actual charge current limit is 5 A. The device regulates ICHG pin at VREF_ICHG.
If ICHG pin voltage exceeds VREF_ICHG, the device enters charge current regulation.
The ICHG pin can also be used to monitor charge current when device is not in charge current regulation. When
not in charge current regulation, the voltage on ICHG pin (VICHG) is proportional to the actual charging current.
ICHG pin can be used to monitor battery current with the following relationship:

K ×V
IBAT = R ICHG ICHG
(5)
ICHG × VREF_ICHG

For example, if ICHG pin is set with 10-kΩ resistor, and the ICHG voltage 1.0V, the actual charge current is
between 2.4 A to 2.6 A (based on KICHG specified).
If ICHG pin is shorted to PGND, the charge current limit is set by the ICHG_REG register. If hardware charge
current limit function is not needed, it is recommended to short this pin to PGND. The ICHG pin function can be
disabled by setting the EN_ICHG_PIN bit to 0 (recommended when pin is shorted to PGND). When the pin is
disabled, charge current limit and monitoring functions via ICHG pin are not available.
To set the maximum charge current using the ICHG_REG register bits, write to the ICHG_REG register bits.
The charge current limit range is from 400 mA to 20,000 mA with 50 mA/step. The default ICHG_REG is set to
maximum code, allowing ICHG pin to limit the current in hardware.

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8.3.4.2 Li-Ion Battery Charging Profile

The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and
regulates current/voltage accordingly.
Table 8-4. Recommended Li-Ion Charge Settings
EQUIVALENT PER 4.2-V
PARAMETER I2C REGISTER BITS VALUE
CHARGE (V)
Battery Low Voltage VBAT_LOWV 0x3 = 71.4% x VFB_REG 3.0 V
Recharge Voltage VRECHG 0x3 = 97.6% x VFB_REG 4.1 V

If the charger device is in DPM regulation during charging, the actual charging current will be less than the
programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at
half the clock rate, as explained in Charging Safety Timer.

Charge Voltage
VFB_REG
VRECHG Battery Voltage

Charge Current
ICHG

Charge Current

VBATLOWV

VBAT_SHORT

IPRECHG
ITERM
IBAT_SHORT

Auto-
Trickle Charge Pre-charge Fast-Charge Taper-Charge
Top-off Timer Recharge
CC CV
(optional) CV

CHARGE_STAT 001 010 011 100 110 111 100

Precharge Timer Safety Timer Safety Timer

(2hrs) CHG_TMR[1:0]

Figure 8-3. Typical Li-Ion Battery Charging Profile

8.3.4.3 LiFePO4 Battery Charging Profile

The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and
regulates current/voltage accordingly.
Table 8-5. Recommended LiFePO4 Charge Settings
EQUIVALENT PER 3.6-V
PARAMETER I2C REGISTER BITS VALUE
CHARGE (V)
Battery Low Voltage VBAT_LOWV 0x1 = 55% x VFB_REG 1.98 V
Recharge Voltage VRECHG 0x0 = 93% x VFB_REG 3.35 V

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If the charger device is in DPM regulation during charging, the actual charging current will be less than the
programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at
half the clock rate, as explained in Charging Safety Timer. The typical charging cycle for LiFePO4 follows the
same profile as Typical Li-Ion Battery Charging Profile.
8.3.4.4 Charging Termination for Li-ion and LiFePO4
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. The termination current threshold is controlled by the lower option between 10% x
ICHG pin setting or the ITERM register setting.
In standalone applications using the ICHG pin to program the current, the termination threshold is set at 10% of
the ICHG pin value (10-A ICHG pin programming results in 1-A termination).
In host-controlled applications, the termination current can be programmed using the ITERM register bits. The
ICHG pin can still be used to set a hardware limit for the charge current.
After the charging cycle is completed, the buck-boost converter turns off. The ACFET stays on to power the
system. When termination occurs, the status register CHARGE_STAT is set to 111, and an INT pulse is asserted
to the host. Termination is temporarily disabled when the charger device is in input current, or input voltage
regulation. Termination can be permanently disabled by writing 0 to EN_TERM.
At low termination currents, due to the comparator offset, the actual termination current may be up to 20% higher
than the termination target. In order to compensate for comparator offset, a programmable top-off timer (default
disabled) can be applied after termination is detected. The top-off timer follows safety timer constraints, such that
if safety timer is suspended, so is the top-off timer. Similarly, if safety timer is doubled, so is the top-off timer.
CHARGE_STAT reports whether the top off timer is active via the 110 code. Once the Top-Off timer expires, the
CHARGE_STAT register is set to 111 and an INT pulse is asserted to the host.
8.3.4.5 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
user can program fast charge safety timer through I2C (CHG_TMR bits). When safety timer expires, the fault
register CHG_TMR_STAT bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can
be disabled by clearing EN_CHG_TMR bit.
During input voltage or input current regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the programmed setting. For example, if the charger is in input current regulation
(IAC_DPM_STAT=1) throughout the whole charging cycle, and the safety timer is set to 5 hours, then the timer
will expire in 10 hours. The timer also counts at half clock rate for TS pin events which reduce charge current
(refer to JEITA Guideline Compliance in Charge Mode section). This half clock rate feature can be disabled by
setting EN_TMR2X = 0.
During faults which disable charging, timer is suspended. Once the fault goes away, safety timer resumes. If
the charging cycle is stopped and started again, the timer gets reset (toggle CE pin or EN_CHG bit restarts the
timer).
The pre-charge safety timer is a fixed 2 hour counter that runs when VBAT < VBAT_LOWV. The pre-charge safety
timer is disabled when EN_PRECHG bit is 0.
8.3.4.6 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.4.6.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.

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To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1 to T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to
T5 range.
At cool temperature, T1 to T2, JEITA recommends the charge current to be reduced to half of the charge current
or lower. The device allows charge current in the cool temperature region to be progrramed to 20%, 40% or
100% of the charge current at T2 to T3 or charge suspend, which is controlled by the register bits JEITA_ISETC.
If charge current is reduced in the cool temperature region, the safety timer counts at half clock rate when
EN_TMR2X = 1.
At warm temperature, T3 to T5, JEITA recommends charge voltage less than 4.1 V / cell. The device provides
the programmability of the charge voltage at T3-T5, to be with a voltage offset less than charge voltage at T2 to
T3 or charge suspend, which is controlled by the register bits JEITA_VSET.
The charger also provides flexible voltage/current settings beyond the JEITA requirements. The charge current
setting at warm temperature T3 to T5 can be configured to be 40%, or 100% of the programmed charge current
or charge suspend, which is programmed by the register bit JEITA_ISETH. If charge current is reduced in the
JEITA warm region, the safety timer counts at half clock rate when EN_TMR2X = 1.
The default charging profile for JEITA is shown in the figure below, in which the blue line is the default setting
and the red dash line is the programmable options.
ISETC=11 ISETH=1 VSET = 11
100% VFB_REG
Percentage of VFB_REG
Percentage of ICHG

80%
VSET = 10
60% 97.6%
ISETC=10 ISETH=0 VSET = 01
40% 94.3%
ISETC=01
20%
ISETC=00 VSET = 00

T1 T2 T3 T5 T1 T2 T3 T5
0°C 10°C TS Temperature 45°C 60°C 0°C 10°C TS Temperature 45°C 60°C

Figure 8-4. TS Charging Values

REGN
RT1

TS
RT2

10K

PGND

Assuming a 103AT NTC thermistor on the battery pack as shown above, the value of RT1 and RT2 can be
determined by:

1 − 1
RTHCOLD × RTHHOT × VT1
VT5
RT2 = (6)
RTHHOT × 1 − 1 − RTHCOLD × VT1
1 −1
VT5

1
VT1 − 1
RT1 = 1 1 (7)
RT2 + RTHCOLD

Select 0°C to 60°C range for Li-ion or Li-polymer battery:

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RTHT1 = 27.28 kΩ
RTHT5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ
The device also offers programmability for all the thresholds via the TS Charging Threshold Control register
(REG0x1B). This flexibility can help to change the charger's operating window in software.
The JEITA profile can be disabled by clearing the EN_JEITA register bit. In this case, the device still limits the
charging window from T1 to T5, but no special charge profile is employed within the Cool (T1 to T2) or Warm (T3
to T5) regions.
The NTC monitoring window can be disabled by clearing the EN_TS register bit. In this case, the TS pin voltage
is ignored, and the device always reports normal TS status. If EN_TS is set to 0, TS pin can be floated or
connected to PGND.
8.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
For battery protection during reverse or auto-reverse mode operation, the device monitors the battery
temperature to be within the VBCOLD to VBHOT thresholds. When temperature is outside of the thresholds,
the reverse mode is shut off and device returns to powering the system from the battery. In addition, EN_REV,
EN_AUTO_REV and REVERSE_STAT bits are cleared to 0 and corresponding TS_STAT is reported (TS Cold or
TS Hot). The temperature protection in reverse mode can be completely disabled by clearing the EN_TS bit to 0.
Temperature Range for Reverse Mode
VREGN

Reverse Mode Suspended

VBCOLDx
(±10°C / ±20°C)

Reverse Mode Enable

VBHOTx
(55°C / 60°C / 65°C)

Reverse Mode Suspended

GND

Figure 8-5. TS Pin Thermistor Sense Threshold in Reverse Mode

8.3.5 Power Path Management

The device accommodates a wide range of input sources from 4.2 V up to 70 V. The device provides dynamic
power management and automatic power path selection to supply the system (SYS) from input source (VAC), or
battery (BAT).
8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
The device features Dynamic Power Management (DPM), which continuously monitors the input current and
input voltage. When input source is over-loaded, either the current exceeds the input current limit (lower of
IAC_DPM or ILIM_HIZ pin setting), or the voltage falls below the input voltage limit (higher of VAC_DPM or
ACUV pin setting, VACUV_DPM). The device then reduces the charge current until the input current falls below the
input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the input voltage continues
to drop. Once the input voltage drops below the ACUV limit (VACUV < VREF_ACUV), the charger stops switching
and the device automatically transitions to Battery Only Mode so that the system is supported by the battery.

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8.3.5.1.1 Input Current Regulation

The total input current is a function of the system supply current and the battery charging current. System current
normally fluctuates as portions of the systems are powered up or down. Without DPM, the source must be able
to supply the maximum system current and the maximum charger input current simultaneously. By using DPM,
the battery charger reduces the charging current when the input current exceeds the input current limit set by
the lower of IAC_DPM register bits, or ILIM_HIZ pin. This allows the current capability of the input source to be
lowered, reducing system cost.
There are two thresholds to limit the input current (if both are enabled, the lower limit of these two will apply):
1. IAC_DPM register bits (host software control)
2. ILIM_HIZ pull down resistor (hardware control)
To set the maximum current using the IAC_DPM register bits, write to the IAC_DPM register bits. When using a
2-mΩ resistor, the input current limit range is from 1 A to 50 A with 125 mA/step. The default IAC_DPM is set to
maximum code, allowing ILIM_HIZ pin to limit the current in hardware.
To set the maximum current using the ILIM_HIZ pin, refer to Section 8.3.5.1.1.1.
Although both limits are referenced to a 2-mΩ sense resistor, other values can also be used. A larger sense
resistor provides a larger sense voltage and higher regulation accuracy, but at the expense of higher conduction
loss. For example, using a 5-mΩ resistor yields programmability from 400 mA to 20 A with 50 mA/step.
8.3.5.1.1.1 ILIM_HIZ Pin
To set the maximum input current using the ILIM_HIZ pin, a pull-down resistor to PGND is used. When using a
2-mΩ RAC_SNS resistor, the input current limit is controlled by: IAC_MAX = KILIM / RILIM_HIZ.
The actual input current limit is the lower value between ILIM_HIZ pin setting and register setting (IAC_DPM).
For example, if the register setting is 20 A, and ILIM_HIZ pin has a 5-kΩ resistor (KILIM = 50 A-kΩ) to ground
for 10 A, the actual input current limit is 10 A. ILIM_HIZ pin can be used to set the input current limit
when EN_ILIM_HIZ_PIN bit is set to 1. The device regulates the pin at VREF_ILIM_HIZ. If pin voltage exceeds
VREF_ILIM_HIZ, the device enters input current regulation. Entering input current regulation through the pin sets
the IAC_DPM_STAT and FLAG bits, and produces an interrupt to host. The interrupt can be masked via the
IAC_DPM_MASK bit.
The ILIM_HIZ pin can also be used to monitor input current. When not in input current regulation, the voltage on
ILIM_HIZ pin (VILIM_HIZ) is proportional to the input current. Pin voltage can be used to monitor input current with
the following relationship: IAC = KILIM x VILIM_HIZ / (RILIM_HIZ x VREF_ILIM_HIZ).
For example, if the pin is set with 5-kΩ resistor, and the pin voltage is 1.0 V, the actual input current is between
4.8 A to 5.2 A (based on KILIM specified).
If ILIM_HIZ pin is shorted, the input current limit is set by the IAC_DPM register. If hardware input current limit
function is not needed, it is recommended to short this pin to GND. If ILIM_HIZ pin is pulled above VIH_ILIM_HIZ,
the device enters HIZ mode (refer to Section 8.3.3.5). The ILIM_HIZ pin function can be disabled by setting the
EN_ILIM_HIZ_PIN bit to 0. When the pin is disabled, input current limit and monitoring functions as well as HIZ
mode control via the pin are not available.
8.3.5.1.2 Input Voltage Regulation
In addition to input current regulation, the device also offers input voltage regulation to limit the input power. This
is especially useful when dealing with input sources such as solar panels, where the operating voltage must be
controlled to extract the maximum power. Alternatively, if the input source current limitation is not known, input
voltage regulation can be used to limit the power draw from the input source. By using input voltage regulation,
the battery charger reduces the charging current when the input voltage falls below the input voltage limit set by
the higher of VAC_DPM register bits, or ACUV pin.
There are two thresholds to limit the input voltage (the higher limit of these will apply)
1. VAC_DPM register bits (host software control)
2. ACUV pin falling threshold (hardware control)

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To set the minimum input voltage using the VAC_DPM register bits, write the desired value directly to the
VAC_DPM register bits. The default VAC_DPM is set to minimum code, allowing ACUV pin to limit the input
voltage in hardware.
To set the minimum input voltage using the ACUV pin, refer to Section 8.3.3.1.
8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
When EN_MPPT bit is 1, the device provides a maximum power point tracking (MPPT) algorithm for solar PV
panel input sources. The Input Power Maximizer algorithm finds and tracks the maximum power point by full
panel sweep.
The full panel sweep is used to find the input operating voltage which delivers the maximum charge current
to the battery. Before running a full panel sweep, the device momentarily enters HIZ mode to measure input
source open-circuit voltage (VOC). The device proceeds to reduce the input voltage regulation target, measuring
the charge current output at each setting. The VAC_DPM register is used to program the minimum voltage
to exit the full panel sweep. After the sweep is complete, the device updates the VAC_MPP register to the
input voltage regulation value producing the maximum charge current. The device then waits for a period of
FULL_SWEEP_TMR[1:0] before performing a new full panel sweep. A full panel sweep can be forced at any
time by setting the FORCE_SWEEP bit to 1. Note that EN_MPPT = 1 is required for FORCE_SWEEP to work.
The FORCE_SWEEP bit is automatically cleared to 0 after the full panel sweep is completed. Note that the
device uses the internal ADC to determine the charge current at each step of the full panel sweep, therefore
writes to the IBAT_ADC_DIS bit are ignored while MPPT is enabled (EN_MPPT = 1).

Note that when the system is directly connected to the input supply, the device cannot limit the system load.
Therefore, the MPPT algorithm may not find and track the true MPP under all conditions. To enable MPPT
operation, it is recommended to connect the system load directly in parallel to the battery pack.
8.3.6 Reverse Mode Power Direction
The device supports buck-boost reverse power direction to deliver power from the battery to the system when
the adapter is not present. During this mode of operation, the ACFET and BATFET both remain off. The reverse
mode output voltage regulation is set in VSYS_REV register bits. The reverse mode also offers output current
regulation via the R AC_SNS resistor. This parameter is controlled by the IAC_REV register bits. The reverse mode
operation can be enabled if the following conditions are valid:
1. SRN above 3 V.
2. DRV_SUP voltage within valid operating window (VDRV_UVP < VDRV < VDRV_OVP.
3. VAC outside the ACOV / ACUV operating window, or VVAC < VVAC_OK, or VVAC> VVAC_INT_OV
4. Reverse mode operation is enabled (EN_REV = 1)
5. Voltage at TS (thermistor) pin is within range configured by Reverse Temperature Monitor as configured by
BHOT and BCOLD register bits
While the reverse mode is active, the device sets the REVERSE_STAT bit to 1. Host can disable the reverse
operation at any time by setting EN_REV bit to 0. The device disables the converter, and turns the BATFET on to
connect the battery directly to the system.
The charger also monitors and regulates the battery discharging current in reverse mode. When the battery
discharge current rises above the IBAT_REV register setting, the charger reduces the reverse mode power flow
to limit the discharge current.
Once a valid VAC voltage is detected for forward operation, the device automatically disables reverse mode
(EN_REV = 0), turns on the ACFETs and proceeds to charge the battery if enabled.
8.3.6.1 Auto Reverse Mode
In some applications, a regulated system voltage is required when the adapter power is removed. The BQ25750
integrates an auto-reverse function which provides a regulated system voltage using the buck-boost converter in
reverse direction once the input power is removed.

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When enabled by setting the AUTO_REV register bit to 1, Auto Reverse mode can be used to provide a
regulated system voltage immediately after the input power is removed. The device transitions to reverse mode
with the BATFET off and the converter on when the input falls below the ACUV threshold.

VAC VSYS

VBAT

VSYS_REV
VAC_DPM
VACUV

IBAT

SYS_REV Regulation
(Buck from BAT to SYS)
Battery Charging VAC_DPM
(CC Mode) Reg

Reverse
Mode ON

Figure 8-6. Auto Reverse Mode if BAT > VSYS_REV When VAC is Removed

While the Auto reverse mode is active, the device sets the REVERSE_STAT bit to 1. Host can disable the Auto
reverse operation at any time by setting EN_AUTO_REV = 0 and EN_REV = 0. The device then disables the
converter, and turns the BATFET on to connect the battery directly to the system.
8.3.7 Integrated 16-Bit ADC for Monitoring
The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of
operation. The ADC is allowed to operate if either the VVAC>VVAC_OK or VBAT>VREGN_OK is valid. The ADC_EN
bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous
conversion or one-shot behavior. After a one-shot conversion finishes, the ADC_EN bit is cleared, and must be
re-asserted to start a new conversion.

The ADC_SAMPLE bits control the resolution and sample speed of the ADC. By default, ADC channels will be
converted in one-shot or continuous conversion mode unless disabled in the ADC Function Disable register. If
an ADC parameter is disabled by setting the corresponding bit, then the read-back value in the corresponding
register will be from the last valid ADC conversion or the default POR value (all zeros if no conversions have
taken place). If an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish
the conversion of that parameter, but will not convert the parameter starting the next conversion cycle. If all
channels are disabled in one-shot conversion mode, the ADC_EN bit is cleared.
The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is complete in one-shot mode
only. This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous
conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will
remain unchanged in continuous conversion mode.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set

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ADC_EN = ‘0’ to disable the ADC. ADC readings are only valid for DC states and not for transients. When host
writes ADC_EN = 0, the ADC stops immediately, and ADC measurement values correspond to last valid ADC
reading.
If the host wants to exit ADC more gracefully, it is possible to do either of the following:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Disable all ADC conversion channels, and the ADC will stop at the end of the current measurement.
When system load is powered from the battery (input source is removed, or device in HIZ mode), enabling the
ADC automatically powers up REGN and increases the quiescent current. To keep the battery leakage low, it is
recommended to duty cycle or completely disable the ADC.
8.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
8.3.8.1 Power Good Indicator (PG)
The PG_STAT bit goes HIGH and the PG pin pulls LOW to indicate a good input source when a valid VAC
voltage is detected. The PG pin can drive an LED. All conditions must be met to indicate power good:
1. VVAC_OK < VVAC < VVAC_INT_OV
2. VACUV > VREF_ACUV
3. VACOV < VREF_ACOV
4. Device not in HIZ mode
The PG pin can be disabled via the DIS_PG_PIN bit. When disabled, this pin can be controlled to pull LOW
using the FORCE_STAT3_ON bit.
8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
The device indicates charging state on the open drain STAT1 and STAT2 pins. The STAT1, STAT2 pins can drive
LEDs.
Table 8-6. STAT1, STAT2 Pin State
CHARGING STATE STAT1 STAT2
Charge in progress (including recharge) ON OFF
Charge done OFF ON
Charging fault detected (TS out of range, safety timer fault,
ON ON
etc.)
Charge disabled (EN_CHG = 0, or CE pin high) OFF OFF

The STAT1, STAT2 pin function can be disabled via the DIS_STAT_PINS bit. When disabled, these pins can
be controlled to independently pull LOW using the FORCE_STAT1_ON and FORCE_STAT2_ON bits. The STAT
pins are not affected by the Reverse mode and remain OFF during this mode.
8.3.8.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT pin notifies the system
host on the device operation. By default, the following events will generate an active-low, 256-µs INT pulse.
1. Valid input source conditions detected (see conditions for PG pin)
2. Valid input source conditions removed (see conditions for PG pin)
3. Entering IAC_DPM regulation through register or ILIM_HIZ pin
4. Entering VAC_DPM regulation through register or ACUV pin
5. I2C Watchdog timer expired
6. Charger status changes state (CHARGE_STAT value change), including Charge Complete
7. TS_STAT changes state (TS_STAT value change)
8. Junction temperature shutdown (TSHUT)
9. Battery overvoltage detected (BATOVP)
10. Charge safety timer expired (including pre-charge or CV timer expiration)
11. A rising edge on any of the *_STAT bits

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Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.
Three bits exist for each one of these events:
• The STAT bit holds the current status of each INT source
• The FLAG bit holds information on which source produced an INT, regardless of the current status
• The MASK bit is used to prevent the device from sending out INT for each particular event
When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an
INT pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are
automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the
FLAG.

IAC_DPM_STAT

IAC_DPM_FLAG

TS_STAT

TS_FLAG

/INT

I2C Flag Read

Figure 8-7. INT Generation Behavior Example

8.3.9 Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a
serial data line (SDA), and a serial clock line (SCL). Devices can be considered as controllers or targets when
performing data transfers. A controller is a device which initiates a data transfer on the bus and generates the
clock signals to permit that transfer. At that time, any device addressed is considered a target.
The device operates as a target device with address 0x6B, receiving control inputs from the controller device like
a micro-controller or digital signal processor through the registers defined in the Register Map. Registers read
outside those defined in the map, return 0xFF. The I2C interface supports standard mode (up to 100 kbits/s), fast
mode (up to 400 kbits/s), and fast mode plus (up to 1 Mbit/s). When the bus is free, both lines are HIGH. The
SDA and SCL pins are open drain and must be connected to the positive supply voltage via a current source or
pull-up resistor.
System Note: All 16-bit registers are defined as Little Endian, with the most-significant byte allocated to the
higher address. 16-bit register writes must be done sequentially and are recommended to be programmed using
multi-write approach described in the Section 8.3.9.7.

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8.3.9.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data
bit transferred.

SDA

SCL

Data line stable;

Data valid Change of
data allowed

Figure 8-8. Bit Transfers on the I2C Bus

8.3.9.2 START and STOP Conditions

All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the controller. The bus is considered busy after the
START condition, and free after the STOP condition. When timeout condition is met, for example START
condition is active for more than 2 seconds and there is no STOP condition triggered, the charger I2C
communication will automatically reset and communication lines are free for another transmission.

SDA SDA

SCL SCL

START (S) STOP (P)

Figure 8-9. START and STOP Conditions on the I2C Bus

8.3.9.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the
Most Significant Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it
has performed some other function, it can hold the SCL line low to force the controller into a wait state (clock
stretching). Data transfer then continues when the target is ready for another byte of data and releases the SCL
line.

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Acknowledgement Acknowledgement
signal from target signal from target

MSB
SDA

SCL S or Sr 1 2 7 8 9 1 2 8 9 P or Sr
START or ACK ACK STOP or
Repeated Repeated
START START

Figure 8-10. Data Transfer on the I2C Bus

8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The ACK signaling takes place after byte. The ACK bit allows the target to signal the controller that the byte was
successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse,
are generated by the controller.
The controller releases the SDA line during the acknowledge clock pulse so the target can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The controller can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.9.5 Target Address and Data Direction Bit
After the START signal, a target address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/ W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B) by default.

SDA

SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

Figure 8-11. Complete Data Transfer on the I2C Bus

8.3.9.6 Single Write and Read

S Target Addr 0 ACK Reg Addr ACK Data to Addr ACK P

Figure 8-12. Single Write

S Target Addr 0 ACK Reg Addr ACK S Target Addr 1 ACK

Data NCK P

Figure 8-13. Single Read

If the register address is not defined, the charger IC sends back NACK and returns to the idle state.

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8.3.9.7 Multi-Write and Multi-Read

The charger device supports multi-read and multi-write of all registers.

S Target Addr 0 ACK Reg Addr ACK

Data to Addr ACK Data to Addr+1 ACK Data to Addr+N ACK P

Figure 8-14. Multi-Write

S Target Addr 0 ACK Reg Addr ACK S Target Addr 1 ACK

Data @ Addr ACK Data @ Addr+1 ACK Data @ Addr+N NCK P

Figure 8-15. Multi-Read

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and a INT is asserted low to
alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as a '1' upon the first read and then
'0' upon subsequent reads. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the
default settings.
In default mode, the device keeps charging the battery with default 2-hour pre-charging safety timer and the
12-hour fast charging safety timer. At the end of the 2-hour or 12-hour timer expiration, the charging is stopped if
termination has not been detected.
A write to any I2C register transitions the charger from default mode to host mode, and initiates the watchdog
timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has
to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set),
or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer is expired, the device returns to default mode and select registers are reset to default
values as detailed in the Register Map section. The Watchdog timer will be reset on any write if the watchdog
timer has expired. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1, and /INT is asserted low
to alert the host (unless masked by WD_MASK).

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Reset
Default Mode
POR Selective
WD_STAT=1 Registers

I2C Write

Reset
Watchdog
Timer

Yes
Host Mode
WD_STAT=0

I2C Write to
WD_RST

No

No Watchdog Timer Expired? Yes

Figure 8-16. Watchdog Timer Flow Chart

8.4.2 Register Bit Reset

Beside the register reset by the watchdog timer in the default mode, the register and the timer could be reset
to the default value by writing the REG_RST bit to 1. The register bits which can be reset by the REG_RST
bit, are noted in the Register Map section. After the register reset, the REG_RST bit will go back from 1 to 0
automatically.

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8.5 BQ25750 Registers

Table 8-7 lists the memory-mapped registers for the BQ25750 registers. All register offset addresses not listed in
Table 8-7 should be considered as reserved locations and the register contents should not be modified.
Table 8-7. BQ25750 Registers
Address Acronym Register Name Section
0x0 REG0x00_Charge_Voltage_Limit Charge Voltage Limit Go
0x2 REG0x02_Charge_Current_Limit Charge Current Limit Go
0x6 REG0x06_Input_Current_DPM_Limit Input Current DPM Limit Go
0x8 REG0x08_Input_Voltage_DPM_Limit Input Voltage DPM Limit Go
0xA REG0x0A_Reverse_Mode_Input_Current_Limit Reverse Mode Input Current Limit Go
0xC REG0x0C_Reverse_Mode_System_Voltage_Limit Reverse Mode System Voltage Limit Go
0x10 REG0x10_Precharge_Current_Limit Precharge Current Limit Go
0x12 REG0x12_Termination_Current_Limit Termination Current Limit Go
0x14 REG0x14_Precharge_and_Termination_Control Precharge and Termination Control Go
0x15 REG0x15_Timer_Control Timer Control Go
0x16 REG0x16_Three-Stage_Charge_Control Three-Stage Charge Control Go
0x17 REG0x17_Charger_Control Charger Control Go
0x18 REG0x18_Pin_Control Pin Control Go
0x19 REG0x19_Power_Path_and_Reverse_Mode_Control Power Path and Reverse Mode Control Go
0x1A REG0x1A_MPPT_Control MPPT Control Go
0x1B REG0x1B_TS_Charging_Threshold_Control TS Charging Threshold Control Go
0x1C REG0x1C_TS_Charging_Region_Behavior_Control TS Charging Region Behavior Control Go
0x1D REG0x1D_TS_Reverse_Mode_Threshold_Control TS Reverse Mode Threshold Control Go
0x1E REG0x1E_Reverse_Undervoltage_Control Reverse Undervoltage Control Go
0x1F REG0x1F_VAC_Max_Power_Point_Detected VAC Max Power Point Detected Go
0x21 REG0x21_Charger_Status_1 Charger Status 1 Go
0x22 REG0x22_Charger_Status_2 Charger Status 2 Go
0x23 REG0x23_Charger_Status_3 Charger Status 3 Go
0x24 REG0x24_Fault_Status Fault Status Go
0x25 REG0x25_Charger_Flag_1 Charger Flag 1 Go
0x26 REG0x26_Charger_Flag_2 Charger Flag 2 Go
0x27 REG0x27_Fault_Flag Fault Flag Go
0x28 REG0x28_Charger_Mask_1 Charger Mask 1 Go
0x29 REG0x29_Charger_Mask_2 Charger Mask 2 Go
0x2A REG0x2A_Fault_Mask Fault Mask Go
0x2B REG0x2B_ADC_Control ADC Control Go
0x2C REG0x2C_ADC_Channel_Control ADC Channel Control Go
0x2D REG0x2D_IAC_ADC IAC ADC Go
0x2F REG0x2F_IBAT_ADC IBAT ADC Go
0x31 REG0x31_VAC_ADC VAC ADC Go
0x33 REG0x33_VBAT_ADC VBAT ADC Go
0x35 REG0x35_VSYS_ADC VSYS ADC Go
0x37 REG0x37_TS_ADC TS ADC Go
0x39 REG0x39_VFB_ADC VFB ADC Go
0x3B REG0x3B_Gate_Driver_Strength_Control Gate Driver Strength Control Go
0x3C REG0x3C_Gate_Driver_Dead_Time_Control Gate Driver Dead Time Control Go

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Table 8-7. BQ25750 Registers (continued)

Address Acronym Register Name Section
0x3D REG0x3D_Part_Information Part Information Go
0x62 REG0x62_Reverse_Mode_Battery_Discharge_Current Reverse Mode Battery Discharge Current Go

Complex bit access types are encoded to fit into small table cells. Table 8-8 shows the codes that are used for
access types in this section.
Table 8-8. BQ25750 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

8.5.1 REG0x00_Charge_Voltage_Limit Register (Address = 0x0) [Reset = 0x0010]

REG0x00_Charge_Voltage_Limit is shown in Table 8-9.
Return to the Summary Table.
I2C REG0x01=[15:8], I2C REG0x00=[7:0]
Table 8-9. REG0x00_Charge_Voltage_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:5 RESERVED R 0x0 Reserved
4:0 VFB_REG R/W 0x10 Reset by: FB Voltage Regulation Limit:
REG_RESET
POR: 1536mV (10h)
Range: 1504mV-1566mV (0h-1Fh)
Bit Step: 2mV
Offset: 1504mV

8.5.2 REG0x02_Charge_Current_Limit Register (Address = 0x2) [Reset = 0x0640]

REG0x02_Charge_Current_Limit is shown in Table 8-10.
Return to the Summary Table.
I2C REG0x03=[15:8], I2C REG0x02=[7:0]
Table 8-10. REG0x02_Charge_Current_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:11 RESERVED R 0x0 Reserved
10:2 ICHG_REG R/W 0x190 Reset by: Fast Charge Current Regulation Limit with 5mΩ
REG_RESET RBAT_SNS:
WATCHDOG Actual charge current is the lower of ICHG_REG and
ICHG pin
POR: 20000mA (190h)
Range: 400mA-20000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 50mA

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Table 8-10. REG0x02_Charge_Current_Limit Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
1:0 RESERVED R 0x0 Reserved

8.5.3 REG0x06_Input_Current_DPM_Limit Register (Address = 0x6) [Reset = 0x0640]

REG0x06_Input_Current_DPM_Limit is shown in Table 8-11.
Return to the Summary Table.
I2C REG0x07=[15:8], I2C REG0x06=[7:0]
Table 8-11. REG0x06_Input_Current_DPM_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:11 RESERVED R 0x0 Reserved
10:2 IAC_DPM R/W 0x190 Reset by: Input Current DPM Regulation Limit with 2mΩ
REG_RESET RAC_SNS:
Actual input current limit is the lower of IAC_DPM and
ILIM_HIZ pin
POR: 50000mA (190h)
Range: 1000mA-50000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 125mA
1:0 RESERVED R 0x0 Reserved

8.5.4 REG0x08_Input_Voltage_DPM_Limit Register (Address = 0x8) [Reset = 0x0348]

REG0x08_Input_Voltage_DPM_Limit is shown in Table 8-12.
Return to the Summary Table.
I2C REG0x09=[15:8], I2C REG0x08=[7:0]
Table 8-12. REG0x08_Input_Voltage_DPM_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:14 RESERVED R 0x0 Reserved
13:2 VAC_DPM R/W 0xD2 Reset by: Input Voltage Regulation Limit:
REG_RESET Note if EN_MPPT = 1, the Full Sweep method will use
this limit as the lower search window for Full Panel
Sweep
POR: 4200mV (D2h)
Range: 4200mV-65000mV (D2h-CB2h)
Clamped Low
Clamped High
Bit Step: 20mV
1:0 RESERVED R 0x0 Reserved

8.5.5 REG0x0A_Reverse_Mode_Input_Current_Limit Register (Address = 0xA) [Reset = 0x0640]

REG0x0A_Reverse_Mode_Input_Current_Limit is shown in Table 8-13.
Return to the Summary Table.
I2C REG0x0B=[15:8], I2C REG0x0A=[7:0]

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Table 8-13. REG0x0A_Reverse_Mode_Input_Current_Limit Register Field Descriptions

Bit Field Type Reset Notes Description
15:11 RESERVED R 0x0 Reserved
10:2 IAC_REV R/W 0x190 Reset by: Input Current Regulation in Reverse Mode with 2mΩ
REG_RESET RAC_SNS:
POR: 50000mA (190h)
Range: 1000mA-50000mA (8h-190h)
Clamped Low
Clamped High
Bit Step: 125mA
1:0 RESERVED R 0x0 Reserved

8.5.6 REG0x0C_Reverse_Mode_System_Voltage_Limit Register (Address = 0xC) [Reset = 0x03E8]

REG0x0C_Reverse_Mode_System_Voltage_Limit is shown in Table 8-14.
Return to the Summary Table.
I2C REG0x0D=[15:8], I2C REG0x0C=[7:0]
Table 8-14. REG0x0C_Reverse_Mode_System_Voltage_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:14 RESERVED R 0x0 Reserved
13:2 VSYS_REV R/W 0xFA Reset by: System Voltage Regulation in Reverse Mode:
REG_RESET
POR: 5000mV (FAh)
Range: 3300mV-65000mV (A5h-CB2h)
Clamped Low
Clamped High
Bit Step: 20mV
1:0 RESERVED R 0x0 Reserved

8.5.7 REG0x10_Precharge_Current_Limit Register (Address = 0x10) [Reset = 0x0140]

REG0x10_Precharge_Current_Limit is shown in Table 8-15.
Return to the Summary Table.
I2C REG0x11=[15:8], I2C REG0x10=[7:0]
Table 8-15. REG0x10_Precharge_Current_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:10 RESERVED R 0x0 Reserved
9:2 IPRECHG R/W 0x50 Actual pre-charge current Pre-charge current regulation limit with 5mΩ
is the lower of IPRECHG RBAT_SNS:
and ICHG pin
POR: 4000mA (50h)
Reset by:
Range: 250mA-10000mA (5h-C8h)
REG_RESET
Clamped Low
Clamped High
Bit Step: 50mA
1:0 RESERVED R 0x0 Reserved

8.5.8 REG0x12_Termination_Current_Limit Register (Address = 0x12) [Reset = 0x00A0]

REG0x12_Termination_Current_Limit is shown in Table 8-16.
Return to the Summary Table.

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I2C REG0x13=[15:8], I2C REG0x12=[7:0]

Table 8-16. REG0x12_Termination_Current_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15:10 RESERVED R 0x0 Reserved
9:2 ITERM R/W 0x28 Actual termination current Termination Current Threshold with 5mΩ RBAT_SNS:
is the lower of ITERM and
POR: 2000mA (28h)
ICHG pin if both functions
Range: 250mA-10000mA (5h-C8h)
enabled
Clamped Low
Reset by:
Clamped High
REG_RESET
Bit Step: 50mA
1:0 RESERVED R 0x0 Reserved

8.5.9 REG0x14_Precharge_and_Termination_Control Register (Address = 0x14) [Reset = 0x0F]

REG0x14_Precharge_and_Termination_Control is shown in Table 8-17.
Return to the Summary Table.
Table 8-17. REG0x14_Precharge_and_Termination_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:4 RESERVED R 0x0 Reserved
3 EN_TERM R/W 0x1 Reset by: Enable termination control
REG_RESET
0b = Disable
1b = Enable
2:1 VBAT_LOWV R/W 0x3 Reset by: Battery threshold for PRECHG to FASTCHG transition,
REG_RESET as percentage of VFB_REG:
00b = 30% x VFB_REG
01b = 55% x VFB_REG
10b = 66.7% x VFB_REG
11b = 71.4% x VFB_REG
0 EN_PRECHG R/W 0x1 Reset by: Enable pre-charge and trickle charge functions:
REG_RESET
0b = Disable
1b = Enable

8.5.10 REG0x15_Timer_Control Register (Address = 0x15) [Reset = 0x1D]

REG0x15_Timer_Control is shown in Table 8-18.
Return to the Summary Table.
Table 8-18. REG0x15_Timer_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 TOPOFF_TMR R/W 0x0 Reset by: Top-off timer control:
REG_RESET
00b = Disable
01b = 15 mins
10b = 30 mins
11b = 45 mins
5:4 WATCHDOG R/W 0x1 Reset by: Watchdog timer control:
REG_RESET
00b = Disable
01b = 40s
10b = 80s
11b = 160s
3 EN_CHG_TMR R/W 0x1 Reset by: Enable charge safety timer:
REG_RESET
0b = Disable
WATCHDOG
1b = Enable

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Table 8-18. REG0x15_Timer_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
2:1 CHG_TMR R/W 0x2 Reset by: Charge safety timer setting:
REG_RESET
00b = 5hr
01b = 8hr
10b = 12hr
11b = 24hr
0 EN_TMR2X R/W 0x1 Reset by: Charge safety timer speed in DPM:
REG_RESET
0b = Timer always counts normally
1b = Timer slowed by 2x during input DPM

8.5.11 REG0x16_Three-Stage_Charge_Control Register (Address = 0x16) [Reset = 0x00]

REG0x16_Three-Stage_Charge_Control is shown in Table 8-19.
Return to the Summary Table.
Table 8-19. REG0x16_Three-Stage_Charge_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 RESERVED R 0x0 Reserved
5 RESERVED R 0x0 Reserved
4 RESERVED R 0x0 Reserved
3:0 CV_TMR R/W 0x0 Reset by: CV timer setting:
REG_RESET 0000b = disable
WATCHDOG 0001b = 1hr
0010b = 2hr
... = ...
1110b = 14hr
1111b = 15hr

8.5.12 REG0x17_Charger_Control Register (Address = 0x17) [Reset = 0xC9]

REG0x17_Charger_Control is shown in Table 8-20.
Return to the Summary Table.
Table 8-20. REG0x17_Charger_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 VRECHG R/W 0x3 Reset by: Battery auto-recharge threshold, as percentage of
REG_RESET VFB_REG:
00b = 93.0% x VFB_REG
01b = 94.3% x VFB_REG
10b = 95.2% x VFB_REG
11b = 97.6% x VFB_REG
5 WD_RST R/W 0x0 Reset by: I2C Watchdog timer reset control:
REG_RESET
0b = Normal
1b = Reset (bit goes back to 0 after timer reset)
4 DIS_CE_PIN R/W 0x0 Reset by: /CE pin function disable:
REG_RESET
0b = /CE pin enabled
1b = /CE pin disabled
3 EN_CHG_BIT_RES R/W 0x1 Reset by: Controls the EN_CHG bit behavior when WATCHDOG
ET_BEHAVIOR REG_RESET expires:
0b = EN_CHG bit resets to 0
1b = EN_CHG bit resets to 1

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Table 8-20. REG0x17_Charger_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
2 EN_HIZ R/W 0x0 Reset by: HIZ mode enable:
REG_RESET
0b = Disable
WATCHDOG
1b = Enable
Adapter Plug In
1 EN_IBAT_LOAD R/W 0x0 Sinks current from SRN Battery Load (IBAT_LOAD) Enable:
to GND. Recommend
0b = Disabled
to disable IBAT ADC
1b = Enabled
(IBAT_ADC_DIS = 1)
while this bit is active.
Reset by:
REG_RESET
WATCHDOG
0 EN_CHG R/W 0x1 Reset by: Charge enable control:
REG_RESET
0b = Disable
WATCHDOG
1b = Enable

8.5.13 REG0x18_Pin_Control Register (Address = 0x18) [Reset = 0xC0]

REG0x18_Pin_Control is shown in Table 8-21.
Return to the Summary Table.
Table 8-21. REG0x18_Pin_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 EN_ICHG_PIN R/W 0x1 Reset by: ICHG pin function enable:
REG_RESET
0b = ICHG pin disabled
WATCHDOG
1b = ICHG pin enabled
6 EN_ILIM_HIZ_PIN R/W 0x1 Reset by: ILIM_HIZ pin function enable:
REG_RESET
0b = ILIM_HIZ pin disabled
WATCHDOG
1b = ILIM_HIZ pin enabled
5 DIS_PG_PIN R/W 0x0 Reset by: PG pin function disable:
REG_RESET
0b = PG pin enabled
1b = PG pin disabled
4 DIS_STAT_PINS R/W 0x0 Reset by: STAT1, STAT2 pin function disable:
REG_RESET
0b = STAT pins enabled
1b = STAT pins disabled
3 FORCE_STAT4_ON R/W 0x0 Reset by: CE_STAT4 pin override:
REG_RESET Can only be forced on if DIS_CE_PIN = 1
0b = CE_STAT4 open-drain off
1b = CE_STAT4 pulls LOW
2 FORCE_STAT3_ON R/W 0x0 Reset by: PG_STAT3 pin override:
REG_RESET Can only be forced on if DIS_PG_PIN = 1
0b = PG_STAT3 open-drain off
1b = PG_STAT3 pulls LOW
1 FORCE_STAT2_ON R/W 0x0 Reset by: STAT2 pin override:
REG_RESET Can only be forced on if DIS_STAT_PINS = 1
0b = STAT2 open-drain off
1b = STAT2 pulls LOW
0 FORCE_STAT1_ON R/W 0x0 Reset by: STAT1 pin override:
REG_RESET Can only be forced on if DIS_STAT_PINS = 1
0b = STAT1 open-drain off
1b = STAT1 pulls LOW

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8.5.14 REG0x19_Power_Path_and_Reverse_Mode_Control Register (Address = 0x19) [Reset = 0x20]

REG0x19_Power_Path_and_Reverse_Mode_Control is shown in Table 8-22.
Return to the Summary Table.
Table 8-22. REG0x19_Power_Path_and_Reverse_Mode_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 REG_RST R/W 0x0 Reset by: Register reset to default values:
REG_RESET
0b = Not reset
1b = Reset (bit goes back to 0 after register reset)
6 EN_IAC_LOAD R/W 0x0 Reset by: VAC Load (IAC_LOAD) Enable:
REG_RESET
0b = Disabled
WATCHDOG
1b = Enabled
5 EN_PFM R/W 0x1 It is recommended to Enable PFM mode in light-load:
disable PFM when ITERM Note this bit is reset upon a valid SYNC signal
< 2A detection on FSW_SYNC pin. Host can set this bit
Reset by: back to 1 to force PFM operation even with a valid
REG_RESET SYNC input
0b = Disable (Fixed-frequency DCM operation)
1b = Enable (PFM operation)
4 FORCE_BATFET_O R/W 0x0 Reset by: Force BATFET off control:
FF REG_RESET
0b = Allow normal BATFET operation
Adapter Plug In
1b = Force BATFET off
3 PWRPATH_REDUC R/W 0x0 Reset by: Power-Path (ACFET, BATFET) Drive Voltage Select:
E_VDRV REG_RESET
0b = 10V
WATCHDOG
1b = 7V
2 EN_BATFET_IDEAL R/W 0x0 Reset by: Enable BATFET ideal diode turn-on mode:
_DIODE REG_RESET Note: Only recommended for single BATFET
0b = Disable
1b = Enable
1 EN_AUTO_REV R/W 0x0 To exit reverse mode, it Auto Reverse Mode to regulate SYS when VBAT <
is recommended to clear VSYS_REV register:
both EN_AUTO_REV and
0b = Disable Auto Reverse
EN_REV bits
1b = Enable Auto Reverse
Reset by:
REG_RESET
WATCHDOG
0 EN_REV R/W 0x0 To exit reverse mode, it Reverse Mode control:
is recommended to clear
0b = Disable
both EN_AUTO_REV and
1b = Enable
EN_REV bits
Reset by:
REG_RESET
WATCHDOG
Adapter Plug In

8.5.15 REG0x1A_MPPT_Control Register (Address = 0x1A) [Reset = 0x20]

REG0x1A_MPPT_Control is shown in Table 8-23.
Return to the Summary Table.
Table 8-23. REG0x1A_MPPT_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 FORCE_SWEEP R/W 0x0 Reset by: Force Full Panel Sweep and reset MPPT timers:
REG_RESET
0b = Normal
1b = Start Full Panel Sweep (bit goes back to 0 after
Full Panel Sweep complete)

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Table 8-23. REG0x1A_MPPT_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
6:3 RESERVED R 0x0 Reserved
2:1 FULL_SWEEP_TMR R/W 0x0 Reset by: Full Panel Sweep timer control:
REG_RESET
00b = 3 min
01b = 10 min
10b = 15 min
11b = 20 min
0 EN_MPPT R/W 0x0 When MPPT is enabled, MPPT algorithm control:
the ADC is controlled
0b = Disable MPPT
by the device, writes to
1b = Enable MPPT
REG2A are ignored
Reset by:
REG_RESET

8.5.16 REG0x1B_TS_Charging_Threshold_Control Register (Address = 0x1B) [Reset = 0x96]

REG0x1B_TS_Charging_Threshold_Control is shown in Table 8-24.
Return to the Summary Table.
Table 8-24. REG0x1B_TS_Charging_Threshold_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 TS_T5 R/W 0x2 Reset by: TS T5 (HOT) threshold control:
REG_RESET
00b = 41.2% (50C)
01b = 37.7% (55C)
10b = 34.375% (60C)
11b = 31.25%(65C)
5:4 TS_T3 R/W 0x1 Reset by: JEITA TS T3 (WARM) threshold control:
REG_RESET
00b = 48.4% (40C)
01b = 44.8% (45C)
10b = 41.2% (50C)
11b = 37.7% (55C)
3:2 TS_T2 R/W 0x1 Reset by: JEITA TS T2 (COOL) threshold control:
REG_RESET
00b = 71.1% (5C)
01b = 68.4% (10C)
10b = 65.5% (15C)
11b = 62.4% (20C)
1:0 TS_T1 R/W 0x2 Reset by: TS T1 (COLD) threshold control:
REG_RESET
00b = 77.15% (-10C)
01b = 75.32% (-5C)
10b = 73.25% (0C)
11b = 71.1% (5C)

8.5.17 REG0x1C_TS_Charging_Region_Behavior_Control Register (Address = 0x1C) [Reset = 0x57]

REG0x1C_TS_Charging_Region_Behavior_Control is shown in Table 8-25.
Return to the Summary Table.
Table 8-25. REG0x1C_TS_Charging_Region_Behavior_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 RESERVED R 0x0 Reserved

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Table 8-25. REG0x1C_TS_Charging_Region_Behavior_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
6:5 JEITA_VSET R/W 0x2 Reset by: JEITA Warm (T3 < TS < T5) regulation voltage setting,
REG_RESET as percentage of VFB_REG:
00b = Charge Suspend
01b = 94.3% x VFB_REG
10b = 97.6% x VFB_REG
11b = 100% x VFB_REG
4 JEITA_ISETH R/W 0x1 Reset by: JEITA Warm (T3 < TS < T5) regulation current setting,
REG_RESET as percentage of ICHG_REG:
0b = 40% x ICHG_REG
1b = 100% x ICHG_REG
3:2 JEITA_ISETC R/W 0x1 Reset by: JEITA Cool (T1 < TS < T2) regulation current setting,
REG_RESET as percentage of ICHG_REG:
00b = Charge Suspend
01b = 20% x ICHG_REG
10b = 40% x ICHG_REG
11b = 100% x ICHG_REG
1 EN_JEITA R/W 0x1 EN_VREG_TEMP_COMP JEITA profile control:
and EN_JEITA cannot be
0b = Disabled (COLD/HOT control only)
set to 1 at the same time.
1b = Enabled (COLD/COOL/WARM/HOT control)
Reset by:
REG_RESET
0 EN_TS R/W 0x1 Reset by: TS pin function control (applies to forward charging
REG_RESET and reverse discharging modes):
0b = Disabled (ignore TS pin)
1b = Enabled

8.5.18 REG0x1D_TS_Reverse_Mode_Threshold_Control Register (Address = 0x1D) [Reset = 0x40]

REG0x1D_TS_Reverse_Mode_Threshold_Control is shown in Table 8-26.
Return to the Summary Table.
Table 8-26. REG0x1D_TS_Reverse_Mode_Threshold_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 BHOT R/W 0x1 Reset by: Reverse Mode TS HOT temperature threshold control:
REG_RESET
00b = 37.7% (55C)
01b = 34.2% (60C)
10b = 31.25%(65C)
11b = Disable
5 BCOLD R/W 0x0 Reset by: Reverse Mode TS COLD temperature threshold
REG_RESET control:
0b = 77.15% (-10C)
1b = 80% (-20C)
4:0 RESERVED R 0x0 Reserved

8.5.19 REG0x1E_Reverse_Undervoltage_Control Register (Address = 0x1E) [Reset = 0x00]

REG0x1E_Reverse_Undervoltage_Control is shown in Table 8-27.
Return to the Summary Table.
Table 8-27. REG0x1E_Reverse_Undervoltage_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 RESERVED R 0x0 Reserved
6 RESERVED R 0x0 Reserved

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Table 8-27. REG0x1E_Reverse_Undervoltage_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
5 SYSREV_UV R/W 0x0 Reset by: Reverse Mode System UVP:
REG_RESET
0b = 80% of VSYS_REV target
1b = Fixed at 3.3V
4 RESERVED R 0x0 Reserved
3 RESERVED R 0x0 Reserved
2 RESERVED R 0x0 Reserved
1 RESERVED R 0x0 Reserved
0 RESERVED R 0x0 Reserved

8.5.20 REG0x1F_VAC_Max_Power_Point_Detected Register (Address = 0x1F) [Reset = 0x0000]

REG0x1F_VAC_Max_Power_Point_Detected is shown in Table 8-28.
Return to the Summary Table.
I2C REG0x20=[15:8], I2C REG0x1F=[7:0]
Table 8-28. REG0x1F_VAC_Max_Power_Point_Detected Register Field Descriptions
Bit Field Type Reset Notes Description
15:14 RESERVED R 0x0 Reserved
13:2 VAC_MPP R 0x0 Input Voltage for Max Power Point detected:
POR: 0mV (0h)
Range: 0mV-60000mV (0h-BB8h)
Clamped High
Bit Step: 20mV
1:0 RESERVED R 0x0 Reserved

8.5.21 REG0x21_Charger_Status_1 Register (Address = 0x21) [Reset = 0x00]

REG0x21_Charger_Status_1 is shown in Table 8-29.
Return to the Summary Table.
Table 8-29. REG0x21_Charger_Status_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 ADC_DONE_STAT R 0x0 ADC conversion status (in one-shot mode only):
0b = Conversion not complete
1b = Conversion complete
6 IAC_DPM_STAT R 0x0 Input Current regulation status:
0b = Normal
1b = In Input Current regulation (ILIM pin or IAC_DPM)
5 VAC_DPM_STAT R 0x0 Input Voltage regulation status:
0b = Normal
1b = In Input Voltage regulation (VAC_DPM or
VSYS_REV)
4 RESERVED R 0x0 Reserved
3 WD_STAT R 0x0 I2C Watchdog timer status:
0b = Normal
1b = WD timer expired

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Table 8-29. REG0x21_Charger_Status_1 Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
2:0 CHARGE_STAT R 0x0 Charge cycle status:
000b = Not charging
001b = Trickle Charge (VBAT < VBAT_SHORT)
010b = Pre-Charge (VBAT < VBAT_LOWV)
011b = Fast Charge (CC mode)
100b = Taper Charge (CV mode)
101b = Reserved
110b = Top-off Timer Charge
111b = Charge Termination Done

8.5.22 REG0x22_Charger_Status_2 Register (Address = 0x22) [Reset = 0x00]

REG0x22_Charger_Status_2 is shown in Table 8-30.
Return to the Summary Table.
Table 8-30. REG0x22_Charger_Status_2 Register Field Descriptions
Bit Field Type Reset Notes Description
7 PG_STAT R 0x0 Input Power Good status:
0b = Not Power Good
1b = Power Good
6:4 TS_STAT R 0x0 TS (Battery NTC) status:
000b = Normal
001b = TS Warm
010b = TS Cool
011b = TS Cold
100b = TS Hot
3:2 RESERVED R 0x0 Reserved
1:0 MPPT_STAT R 0x0 Max Power Point Tracking Algorithm status:
00b = MPPT Disabled
01b = MPPT Enabled, But Not Running
10b = Full Panel Sweep In Progress
11b = Max Power Voltage Detected

8.5.23 REG0x23_Charger_Status_3 Register (Address = 0x23) [Reset = 0x00]

REG0x23_Charger_Status_3 is shown in Table 8-31.
Return to the Summary Table.
Table 8-31. REG0x23_Charger_Status_3 Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 RESERVED R 0x0 Reserved
5:4 FSW_SYNC_STAT R 0x0 FSW_SYNC pin status:
00b = Normal, no external clock detected
01b = Valid ext. clock detected
10b = Pin fault (frequency out-of-range)
11b = Reserved
3 CV_TMR_STAT R 0x0 CV Timer status:
0b = Normal
1b = CV Timer Expired
2 REVERSE_STAT R 0x0 Converter Reverse Mode status:
0b = Reverse Mode off
1b = Reverse Mode On

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Table 8-31. REG0x23_Charger_Status_3 Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
1 ACFET_STAT R 0x0 ACFET driver status:
0b = ACFET off
1b = ACFET on
0 BATFET_STAT R 0x0 BATFET driver status:
0b = BATFET off
1b = BATFET on

8.5.24 REG0x24_Fault_Status Register (Address = 0x24) [Reset = 0x00]

REG0x24_Fault_Status is shown in Table 8-32.
Return to the Summary Table.
Table 8-32. REG0x24_Fault_Status Register Field Descriptions
Bit Field Type Reset Notes Description
7 VAC_UV_STAT R 0x0 Input under-voltage status:
0b = Input Normal
1b = Device in Input under-voltage protection
6 VAC_OV_STAT R 0x0 Input over-voltage status:
0b = Input Normal
1b = Device in Input over-voltage protection
5 IBAT_OCP_STAT R 0x0 Battery over-current status:
0b = Battery current normal
1b = Battery over-current detected
4 VBAT_OV_STAT R 0x0 Battery over-voltage status:
0b = Normal
1b = Device in Battery over-voltage protection
3 TSHUT_STAT R 0x0 Thermal shutdown status:
0b = Normal
1b = Device in thermal shutdown protection
2 CHG_TMR_STAT R 0x0 Charge safety timer status:
0b = Normal
1b = Charge safety timer expired
1 DRV_OKZ_STAT R 0x0 In battery-only mode with DRV_SUP pin voltage status:
ADC disabled, this bit
0b = Normal
always reads '1'
1b = DRV_SUP pin voltage is out of valid range
0 RESERVED R 0x0 Reserved

8.5.25 REG0x25_Charger_Flag_1 Register (Address = 0x25) [Reset = 0x00]

REG0x25_Charger_Flag_1 is shown in Table 8-33.
Return to the Summary Table.
Table 8-33. REG0x25_Charger_Flag_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 ADC_DONE_FLAG R 0x0 ADC conversion INT flag (in one-shot mode only):
Note: always reads 0 in continuous mode
Access: R (ClearOnRead)
0b = Conversion not complete
1b = Conversion complete

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Table 8-33. REG0x25_Charger_Flag_1 Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
6 IAC_DPM_FLAG R 0x0 Input Current regulation INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Device entered Input Current regulation
5 VAC_DPM_FLAG R 0x0 Input Voltage regulation INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Device entered Input Voltage regulation
4 RESERVED R 0x0 Reserved
3 WD_FLAG R 0x0 I2C Watchdog timer INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = WD_STAT rising edge detected
2 RESERVED R 0x0 Reserved
1 CV_TMR_FLAG R 0x0 CV timer INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = CV timer expired rising edge detected
0 CHARGE_FLAG R 0x0 Charge cycle INT flag:
Access: R (ClearOnRead)
0b = Not charging
1b = CHARGE_STAT[2:0] bits changed (transition to
any state)

8.5.26 REG0x26_Charger_Flag_2 Register (Address = 0x26) [Reset = 0x00]

REG0x26_Charger_Flag_2 is shown in Table 8-34.
Return to the Summary Table.
Table 8-34. REG0x26_Charger_Flag_2 Register Field Descriptions
Bit Field Type Reset Notes Description
7 PG_FLAG R 0x0 Input Power Good INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = PG signal toggle detected
6 ACFET_FLAG R 0x0 ACFET driver INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = ACFET signal toggle detected
5 BATFET_FLAG R 0x0 BATFET driver INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = BATFET signal toggle detected
4 TS_FLAG R 0x0 TS (Battery NTC) INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = TS_STAT[2:0] bits changed (transitioned to any
state)
3 REVERSE_FLAG R 0x0 Reverse Mode INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Reverse Mode toggle detected

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Table 8-34. REG0x26_Charger_Flag_2 Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
2 RESERVED R 0x0 Reserved
1 FSW_SYNC_FLAG R 0x0 FSW_SYNC pin signal INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = FSW_SYNC status changed
0 MPPT_FLAG R 0x0 Max Power Point Tracking INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = MPPT_STAT[1:0] bits changed (transitioned to
any state)

8.5.27 REG0x27_Fault_Flag Register (Address = 0x27) [Reset = 0x00]

REG0x27_Fault_Flag is shown in Table 8-35.
Return to the Summary Table.
Table 8-35. REG0x27_Fault_Flag Register Field Descriptions
Bit Field Type Reset Notes Description
7 VAC_UV_FLAG R 0x0 Input under-voltage INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Entered input under-voltage fault
6 VAC_OV_FLAG R 0x0 Input over-voltage INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Entered Input over-voltage fault
5 IBAT_OCP_FLAG R 0x0 Battery over-current INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Entered Battery over-current fault
4 VBAT_OV_FLAG R 0x0 Battery over-voltage INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Entered battery over-voltage fault
3 TSHUT_FLAG R 0x0 Thermal shutdown INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Entered TSHUT fault
2 CHG_TMR_FLAG R 0x0 Charge safety timer INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = Charge Safety timer expired rising edge detected
1 DRV_OKZ_FLAG R 0x0 DRV_SUP pin voltage INT flag:
Access: R (ClearOnRead)
0b = Normal
1b = DRV_SUP pin fault detected
0 RESERVED R 0x0 Reserved

8.5.28 REG0x28_Charger_Mask_1 Register (Address = 0x28) [Reset = 0x00]

REG0x28_Charger_Mask_1 is shown in Table 8-36.

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Return to the Summary Table.

Table 8-36. REG0x28_Charger_Mask_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 ADC_DONE_MASK R/W 0x0 Reset by: ADC conversion INT mask (in one-shot mode only):
REG_RESET
0b = ADC_DONE produces INT pulse
1b = ADC_DONE does not produce INT pulse
6 IAC_DPM_MASK R/W 0x0 Reset by: Input Current regulation INT mask:
REG_RESET
0b = IAC_DPM_FLAG produces INT pulse
1b = IAC_DPM_FLAG does not produce INT pulse
5 VAC_DPM_MASK R/W 0x0 Reset by: Input Voltage regulation INT mask:
REG_RESET
0b = VAC_DPM_FLAG produces INT pulse
1b = VAC_DPM_FLAG does not produce INT pulse
4 RESERVED R 0x0 Reserved
3 WD_MASK R/W 0x0 Reset by: I2C Watchdog timer INT mask:
REG_RESET
0b = WD expiration produces INT pulse
1b = WD expiration does not produce INT pulse
2 RESERVED R 0x0 Reserved
1 CV_TMR_MASK R/W 0x0 Reset by: CV timer INT mask:
REG_RESET
0b = CV Timer expired rising edge produces INT pulse
1b = CV Timer expired rising edge does not produce
INT pulse
0 CHARGE_MASK R/W 0x0 Reset by: Charge cycle INT mask:
REG_RESET
0b = CHARGE_STAT change produces INT pulse
1b = CHARGE_STAT change does not produces INT
pulse

8.5.29 REG0x29_Charger_Mask_2 Register (Address = 0x29) [Reset = 0x00]

REG0x29_Charger_Mask_2 is shown in Table 8-37.
Return to the Summary Table.
Table 8-37. REG0x29_Charger_Mask_2 Register Field Descriptions
Bit Field Type Reset Notes Description
7 PG_MASK R/W 0x0 Reset by: Input Power Good INT mask:
REG_RESET
0b = PG toggle produces INT pulse
1b = PG toggle does not produce INT pulse
6 ACFET_MASK R/W 0x0 Reset by: ACFET driver INT mask:
REG_RESET
0b = ACFET toggle produces INT pulse
1b = ACFET toggle does not produce INT pulse
5 BATFET_MASK R/W 0x0 Reset by: BATFET driver INT mask:
REG_RESET
0b = BATFET toggle produces INT pulse
1b = BATFET toggle does not produce INT pulse
4 TS_MASK R/W 0x0 Reset by: TS (Battery NTC) INT mask:
REG_RESET
0b = TS_STAT change produces INT pulse
1b = TS_STAT change does not produce INT pulse
3 REVERSE_MASK R/W 0x0 Reset by: Reverse Mode INT mask:
REG_RESET
0b = REVERSE_STAT toggle produces INT pulse
1b = REVERSE_STAT toggle does no produce INT
pulse
2 RESERVED R 0x0 Reserved

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Table 8-37. REG0x29_Charger_Mask_2 Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
1 FSW_SYNC_MASK R/W 0x0 Reset by: FSW_SYNC pin signal INT mask:
REG_RESET
0b = FSW_SYNC status change produces INT pulse
1b = FSW_SYNC status change does not produce INT
pulse
0 MPPT_MASK R/W 0x0 Reset by: Max Power Point Tracking INT mask:
REG_RESET
0b = MPPT_STAT rising edge produces INT pulse
1b = MPPT_STAT rising edge does no produce INT
pulse

8.5.30 REG0x2A_Fault_Mask Register (Address = 0x2A) [Reset = 0x00]

REG0x2A_Fault_Mask is shown in Table 8-38.
Return to the Summary Table.
Table 8-38. REG0x2A_Fault_Mask Register Field Descriptions
Bit Field Type Reset Notes Description
7 VAC_UV_MASK R/W 0x0 Reset by: Input under-voltage INT mask:
REG_RESET
0b = Input under-voltage event produces INT pulse
1b = Input under-voltage event does not produce INT
pulse
6 VAC_OV_MASK R/W 0x0 Reset by: Input over-voltage INT mask:
REG_RESET
0b = Input over-voltage event produces INT pulse
1b = Input over-voltage event does not produce INT
pulse
5 IBAT_OCP_MASK R/W 0x0 Reset by: Battery over-current INT mask:
REG_RESET
0b = Battery over-current event produces INT pulse
1b = Battery over-current event does not produce INT
pulse
4 VBAT_OV_MASK R/W 0x0 Reset by: Battery over-voltage INT mask:
REG_RESET
0b = Battery over-voltage event produces INT pulse
1b = Battery over-voltage event does not produce INT
pulse
3 TSHUT_MASK R/W 0x0 Reset by: Thermal shutdown INT mask:
REG_RESET
0b = TSHUT event produces INT pulse
1b = TSHUT event does not produce INT pulse
2 CHG_TMR_MASK R/W 0x0 Reset by: Charge safety timer INT mask:
REG_RESET
0b = Timer expired rising edge produces INT pulse
1b = Timer expired rising edge does not produce INT
pulse
1 DRV_OKZ_MASK R/W 0x0 Reset by: DRV_SUP pin voltage INT mask:
REG_RESET
0b = DRV_SUP pin fault produces INT pulse
1b = DRV_SUP pin fault does not produce INT pulse
0 RESERVED R 0x0 Reserved

8.5.31 REG0x2B_ADC_Control Register (Address = 0x2B) [Reset = 0x60]

REG0x2B_ADC_Control is shown in Table 8-39.
Return to the Summary Table.

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Table 8-39. REG0x2B_ADC_Control Register Field Descriptions

Bit Field Type Reset Notes Description
7 ADC_EN R/W 0x0 When ADC control:
EN_VREG_TEMP_COMP
0b = Disable ADC
= 1, the ADC will
1b = Enable ADC
be automatically enabled,
regardless of the status of
ADC_EN
Reset by:
REG_RESET
WATCHDOG
6 ADC_RATE R/W 0x1 Reset by: ADC conversion rate control:
REG_RESET
0b = Continuous conversion
1b = One-shot conversion
5:4 ADC_SAMPLE R/W 0x2 Reset by: ADC sample speed:
REG_RESET
00b = 15 bit effective resolution
01b = 14 bit effective resolution
10b = 13 bit effective resolution
11b = Reserved
3 ADC_AVG R/W 0x0 Reset by: ADC average control:
REG_RESET
0b = Single value
1b = Running average
2 ADC_AVG_INIT R/W 0x0 Reset by: ADC average initial value control:
REG_RESET
0b = Start average using existing register value
1b = Start average using new ADC conversion
1:0 RESERVED R 0x0 Reserved

8.5.32 REG0x2C_ADC_Channel_Control Register (Address = 0x2C) [Reset = 0x02]

REG0x2C_ADC_Channel_Control is shown in Table 8-40.
Return to the Summary Table.
Table 8-40. REG0x2C_ADC_Channel_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 IAC_ADC_DIS R/W 0x0 Reset by: IAC ADC control
REG_RESET
0b = Enable
1b = Disable
6 IBAT_ADC_DIS R/W 0x0 Recommend to disable IBAT ADC control
IBAT ADC channel when
0b = Enable
EN_IBAT_LOAD bit is 1
1b = Disable
Reset by:
REG_RESET
5 VAC_ADC_DIS R/W 0x0 Reset by: VAC ADC control
REG_RESET
0b = Enable
1b = Disable
4 VBAT_ADC_DIS R/W 0x0 Reset by: VBAT ADC control
REG_RESET
0b = Enable
1b = Disable
3 VSYS_ADC_DIS R/W 0x0 Reset by: VSYS ADC control
REG_RESET
0b = Enable
1b = Disable
2 TS_ADC_DIS R/W 0x0 Reset by: TS ADC control
REG_RESET
0b = Enable
1b = Disable

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Table 8-40. REG0x2C_ADC_Channel_Control Register Field Descriptions (continued)

Bit Field Type Reset Notes Description
1 VFB_ADC_DIS R/W 0x1 Reset by: VFB ADC control
REG_RESET Recommend to disable this channel when charging is
enabled
0b = Enable
1b = Disable
0 RESERVED R 0x0 Reserved

8.5.33 REG0x2D_IAC_ADC Register (Address = 0x2D) [Reset = 0x0000]

REG0x2D_IAC_ADC is shown in Table 8-41.
Return to the Summary Table.
I2C REG0x2E=[15:8], I2C REG0x2D=[7:0]
Table 8-41. REG0x2D_IAC_ADC Register Field Descriptions
Bit Field Type Reset Notes Description
15:0 IAC_ADC R 0x0 IAC ADC reading with 2mΩ RAC_SNS:
Reported as 2s complement
POR: 0mA (0h)
Format: 2s Complement
Range: -50000mA-50000mA (9E58h-61A8h)
Clamped Low
Clamped High
Bit Step: 2mA

8.5.34 REG0x2F_IBAT_ADC Register (Address = 0x2F) [Reset = 0x0000]

REG0x2F_IBAT_ADC is shown in Table 8-42.
Return to the Summary Table.
I2C REG0x30=[15:8], I2C REG0x2F=[7:0]
Table 8-42. REG0x2F_IBAT_ADC Register Field Descriptions
Bit Field Type Reset Notes Description
15:0 IBAT_ADC R 0x0 IBAT ADC reading with 5mΩ RBAT_SNS:
Reported as 2s complement
POR: 0mA (0h)
Format: 2s Complement
Range: -20000mA-20000mA (D8F0h-2710h)
Clamped Low
Clamped High
Bit Step: 2mA

8.5.35 REG0x31_VAC_ADC Register (Address = 0x31) [Reset = 0x0000]

REG0x31_VAC_ADC is shown in Table 8-43.
Return to the Summary Table.
I2C REG0x32=[15:8], I2C REG0x31=[7:0]

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Table 8-43. REG0x31_VAC_ADC Register Field Descriptions

Bit Field Type Reset Notes Description
15:0 VAC_ADC R 0x0 VAC ADC reading:
Reported as unsigned integer
POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

8.5.36 REG0x33_VBAT_ADC Register (Address = 0x33) [Reset = 0x0000]

REG0x33_VBAT_ADC is shown in Table 8-44.
Return to the Summary Table.
I2C REG0x34=[15:8], I2C REG0x33=[7:0]
Table 8-44. REG0x33_VBAT_ADC Register Field Descriptions
Bit Field Type Reset Notes Description
15:0 VBAT_ADC R 0x0 VBAT ADC reading:
Reported as unsigned integer
POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

8.5.37 REG0x35_VSYS_ADC Register (Address = 0x35) [Reset = 0x0000]

REG0x35_VSYS_ADC is shown in Table 8-45.
Return to the Summary Table.
I2C REG0x36=[15:8], I2C REG0x35=[7:0]
Table 8-45. REG0x35_VSYS_ADC Register Field Descriptions
Bit Field Type Reset Notes Description
15:0 VSYS_ADC R 0x0 VSYS ADC reading:
Reported as unsigned integer
POR: 0mV (0h)
Format: 2s Complement
Range: 0mV-65534mV (0h-7FFFh)
Clamped Low
Bit Step: 2mV

8.5.38 REG0x37_TS_ADC Register (Address = 0x37) [Reset = 0x0000]

REG0x37_TS_ADC is shown in Table 8-46.
Return to the Summary Table.
I2C REG0x38=[15:8], I2C REG0x37=[7:0]

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Table 8-46. REG0x37_TS_ADC Register Field Descriptions

Bit Field Type Reset Notes Description
15:0 TS_ADC R 0x0 TS ADC reading as percentage of REGN:
Reported as unsigned integer
POR: 0%(0h)
Range: 0% - 99.90234375% (0h-3FFh)
Clamped High
Bit Step: 0.09765625%

8.5.39 REG0x39_VFB_ADC Register (Address = 0x39) [Reset = 0x0000]

REG0x39_VFB_ADC is shown in Table 8-47.
Return to the Summary Table.
I2C REG0x3A=[15:8], I2C REG0x39=[7:0]
Table 8-47. REG0x39_VFB_ADC Register Field Descriptions
Bit Field Type Reset Notes Description
15:0 VFB_ADC R 0x0 VFB ADC reading:
POR: 0mV (0h)
Range: 0mV-2047mV (0h-7FFh)
Clamped High
Bit Step: 1mV

8.5.40 REG0x3B_Gate_Driver_Strength_Control Register (Address = 0x3B) [Reset = 0x00]

REG0x3B_Gate_Driver_Strength_Control is shown in Table 8-48.
Return to the Summary Table.
Table 8-48. REG0x3B_Gate_Driver_Strength_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 BOOST_HS_DRV R/W 0x0 Reset by: Boost High Side FET Gate Driver Strength:
REG_RESET
00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
5:4 BUCK_HS_DRV R/W 0x0 Reset by: Buck High Side FET Gate Driver Strength:
REG_RESET
00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
3:2 BOOST_LS_DRV R/W 0x0 Reset by: Boost Low Side FET Gate Driver Strength:
REG_RESET
00b = Fastest
01b = Faster
10b = Slower
11b = Slowest
1:0 BUCK_LS_DRV R/W 0x0 Reset by: Buck Low Side FET Gate Driver Strength:
REG_RESET
00b = Fastest
01b = Faster
10b = Slower
11b = Slowest

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8.5.41 REG0x3C_Gate_Driver_Dead_Time_Control Register (Address = 0x3C) [Reset = 0x00]

REG0x3C_Gate_Driver_Dead_Time_Control is shown in Table 8-49.
Return to the Summary Table.
Table 8-49. REG0x3C_Gate_Driver_Dead_Time_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7:4 RESERVED R 0x0 Reserved
3:2 BOOST_DEAD_TIM R/W 0x0 Reset by: Boost Side FETs Dead Time Control:
E REG_RESET
00b = 45ns
01b = 75ns
10b = 105ns
11b = 135ns
1:0 BUCK_DEAD_TIME R/W 0x0 Reset by: Buck Side FETs Dead Time Control:
REG_RESET
00b = 45ns
01b = 75ns
10b = 105ns
11b = 135ns

8.5.42 REG0x3D_Part_Information Register (Address = 0x3D) [Reset = 0x02]

REG0x3D_Part_Information is shown in Table 8-50.
Return to the Summary Table.
Table 8-50. REG0x3D_Part_Information Register Field Descriptions
Bit Field Type Reset Notes Description
7 RESERVED R 0x0 Reserved
6:3 PART_NUM R 0x0 Part Number:
000 - BQ25750
2:0 DEV_REV R 0x2 Device Revision:

8.5.43 REG0x62_Reverse_Mode_Battery_Discharge_Current Register (Address = 0x62) [Reset = 0x02]

REG0x62_Reverse_Mode_Battery_Discharge_Current is shown in Table 8-51.
Return to the Summary Table.
Table 8-51. REG0x62_Reverse_Mode_Battery_Discharge_Current Register Field Descriptions
Bit Field Type Reset Notes Description
7:6 IBAT_REV R/W 0x0 Reset by: Reverse mode battery discharge current limit:
REG_RESET
00b = 20A
01b = 15A
10b = 10A
11b = 5A
5:2 RESERVED R 0x0 Reserved
1 EN_CONV_FAST_T R/W 0x1 Reset by: Enable converter fast transient response in reverse
RANSIENT REG_RESET mode only -
0b = Disable
1b = Enable
0 RESERVED R 0x0 Reserved

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The BQ25750 battery charger is ideal for high current charging (up-to 20 A) and can charge multi-chemistry
battery packs consisting of single cells or multiple cells in series up-to 70 V. The BQ25750EVM evaluation
module is a complete charge module for evaluating the device performance. The application curves were taken
using the BQ25750EVM.
9.2 Typical Applications

9.2.1 Typical Application

The device can be configured for direct power path applications, where the input source can be used to power
both system as well as charge the battery. When the input source falls outside the VAC operating window
programmed through ACUV and ACOV, the battery is automatically connected to the system. Figure 9-1 shows
a typical schematic when using the device as a 14S Li-Ion charger from a 48V input. The charging parameters
are programmed via the I2C registers.
Q1 Q2
2m

48Vin
SYS
40V ~ 56V
+ CSYS
RAC_SNS 80µF Q3

10 10 2
Q4
2.2µF
2x 100nF
Q5 Q8
80µF
L1

470nF 47nF 47nF

Q6 Q7
DRV_SUP DRV_SUP

2x 100nF 10

HIDRV1 SW1 SW2 HIDRV2 470nF RBAT_SNS

BTST1 LODRV1 LODRV2 BTST2 5m
ACN SYS 10
ACP BATSRC
ACDRV BATDRV
VAC
1000k
ACUV SRP
6.26k SRN 250k
ACOV FB REGN
22.1k 12k
SYS BUCK 5V BATTERY
DRV_SUP 5.24k
REGN
4.7µF
TS
14S Li-Ion
CE 42V ~ 59V
3.3k
INT ILIM_HIZ
4.2k
SDA ICHG
SCL FSW_SYNC 80k
Host
PG
STAT1 PGND 30.31k
STAT2 BQ25750

PGND AGND

Figure 9-1. BQ25750: I2C Controlled, 48 VAC with 14-S Li-Ion Battery, 10-A Charge Current and 350-kHz
Switching Frequency

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Table 9-1. Recommended Part Numbers:

COMPONENT VALUE RECOMMENDED PART NO.
Q1, Q2 80V, 2.6mΩ AONS6276
Q3, Q4 80V, 2.6mΩ AONS6276
Q5, Q6, Q7, Q8 80V, 6.5mΩ SiR880BDP
L1 10uH IHLP6767GZ-01

9.2.1.1 Design Requirements

For this design example, use the parameters shown in the table below.
Table 9-2. Design Parameters
PARAMETER VALUE
Input voltage operating range (VAC) 40V to 56V
Input current limit (IAC) 12 A
Fast-charge current limit (ICHG) 10 A
Battery Charge Voltage (VBAT_REG) 58.8V
Switching frequency 350 kHz

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
The input voltage operating window is programmed by an ACUV / ACOV window with a resistor divider from
VAC to GND. The top resistor, RAC1 is typically selected as 1,000 kΩ to minimize the input voltage leakage
current. Assuming the desired trip-points for under-voltage and over-voltage protection are labeled VVACUVP and
VVACOVP, the resistor divider required can be calculated as follows. The internal reference for the over-voltage
threshold (VREF_ACOV) is 1.2 V. The internal reference for the under-voltage threshold (VREF_ACUV) is 1.1 V.

INPUT
VAC

RAC1
ACUV
RAC2
ACOV
RAC3

Figure 9-2. ACUV and ACOV Resistor Divider

1.2V 1,000kΩ + RAC2 + RAC3

VVACOVP = RAC3 (8)

1.1V 1,000kΩ + RAC2 + RAC3

VVACUVP = RAC2 + RAC3 (9)

Solving this system of equations and finding the nearest 0.1% resistor value for the desired trip-points as 40 V
and 56 V for undervoltage and overvoltage yields:
RAC2 = 6.26 kΩ
RAC3 = 22.1 kΩ
The resulting overvoltage trip point can be calculated as:
VVACOVP = 1.2 V (1,000 kΩ + 6.26 kΩ + 22.1 kΩ) / (22.1 kΩ) = 55.8 V

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Similarly, the VVACUVP can be calculated as: 39.9 V

Note that in addition to programming the input undervoltage threshold, the ACUV pin also programs a hardware
input voltage regulation limit when the pin voltage reaches the reference (VACUV_DPM, typically 1.2 V). When the
input voltage reaches this threshold, the charger will reduce charge current to regulate the ACUV pin to the 1.2 V
reference. For the above example, the hardware ACUV_DPM level can be calculated as:
ACUV_DPM = 1.2 V (1,000 kΩ + 6.26 kΩ + 22.1 kΩ) / (6.26 kΩ + 22.1 kΩ) = 43.5 V
For the default device operating window of 4.2 V to 60 V, the ACUV can be pulled up directly to VAC, while the
ACOV can be pulled directly to GND.
9.2.1.2.2 Charge Voltage Selection
The battery regulation voltage is programmed using a resistor divider to the FB pin. The default internal voltage
reference is 1.536 V, and can be changed via the VFB_REG register bits. The top of the resistor divider is
selected to be 249 kΩ.
RTOP = 249 kΩ
The bottom resistor can be calculated as:

FB V
RBOT = RTOP × V + RFBG (10)
BATREG − VFB

where
• VFB is the target feedback voltage programmed through I2C (default 1.536 V),
• VBATREG is the desired battery regulation target (58.8 V in this example)
• RFBG is the internal FBG pull-down resistor (33 Ω)
RFB_BOT = 6.712 kΩ.
Choosing the nearest 0.1% resistor value, gives RFB_BOT = 6.65 kΩ, for a nominal charge voltage of 58.75 V.
Further fine-tuning of the regulation voltage can be achieved by changing the internal feedback reference.
It is recommended to use 0.1% accurate resistors to maximize the charge voltage accuracy.
9.2.1.2.3 Switching Frequency Selection
The switching frequency is set by a resistor connected from the FSW_SYNC pin to PGND. The RFSW resistor
required to set the desired frequency is calculated using Equation 3 or Table 8-2. A 0.1% standard resistor of 80
kΩ is selected to set fSW = 350 kHz.
9.2.1.2.4 Inductor Selection
Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current
should be higher than the inductor current (IL) plus half the ripple current (IRIPPLE):

ISAT ≥ IL + 12 IRIPPLE (11)

The inductor ripple current in buck operation depends on input voltage (VAC), duty cycle (DBUCK = VBAT/VAC),
switching frequency (fSW) and inductance (L):

V × DBUCK × 1 − DBUCK
IRIPPLE_BUCK = AC f ×L (12)
SW

During boost operation, the duty cycle is: DBOOST = 1 – (VAC/VBAT). The inductor ripple current is:

V ×D
IRIPPLE_BOOST = ACf BOOST
×L (13)
SW

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The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Ripple calculations should be
analyzed for both forward and reverse operating modes if applicable.
Usually inductor ripple is designed in the range of (20 – 40%) maximum inductor current (in either forward or
reverse mode) as a trade-off between inductor size and efficiency for a practical design.
9.2.1.2.5 Input (VAC / SYS) Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the output when duty cycle is 0.5 in forward buck mode, or reverse boost mode. If
the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the
duty cycle is closest to 50% and can be estimated by Equation 14:

ICIN = ICHG × D × 1 − D (14)

A combination of ceramic and bulk capacitors should be used to provide a short path for high di/dt current
and to reduce the voltage ripple. Ceramic capacitors should be placed close to the switching half-bridge. Given
total bulk input capacitance, it is recommended to distribute equally on either side of RAC_SNS. The complete
schematic is a good starting point for input capacitor for typical applications.
9.2.1.2.6 Output (VBAT) Capacitor
In forward boost mode or reverse buck mode, the output capacitor conducts high ripple current. The output
capacitor RMS ripple current is given by where the minimum VAC corresponds to the maximum capacitor
current.

VBAT
ICBAT = IBAT VAC − 1 (15)

58V
In this case, the highest ripple occurs with highest VBAT and lowest VAC: ICBAT = 10A 40V − 1 = 6.9A . A 5-mΩ
output capacitor ESR causes an output voltage ripple of 74 mV as given by:

V
ΔVRIPPLE ESR = IBAT × V BAT × ESR (16)
AC, min

A 140-μF output capacitor causes a capacitive ripple voltage of 66 mV as given by:

VAC,min
1− V
BAT
ΔVRIPPLE CBAT = IBAT × C (17)
BAT × fSW

A combination of ceramic and bulk capacitors should be used to provide low ESR and high ripple current
capacity. Ceramic capacitors should be placed close to the switching half-bridge. Given total bulk output
capacitance, it is recommended to distribute equally on either side of RBAT_SNS. The complete schematic is
a good starting point for CBAT for typical applications.
9.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
The battery current sense resistor between SRP and SRN is fixed at 5 mΩ; using a different value is not
recommended. The input current sense resistor between ACP and ACN is typically 2 mΩ, but can be increased
to achieve better accuracy at lower sensed currents. In USB-PD EPR applications, a 5-mΩ sense resistor is
recommended to achieve programmability in 50 mA/step. In addition, if input current limit function is not desired,
ACP and ACN may be shorted together. For both of these sense resistors, a filter network is recommended as
shown in the Typical Application.
For both the input current and the output current, the limits may be programmed using the I2C interface or an
external programming resistor on ILIM_HIZ and ICHG pins, respectively.

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PARAMETER FORMULA VALUE

Input Current Hardware Limit RILIM_HIZ = KILIM / 15 A 3.3 kΩ for 15 A with 2-mΩ RAC_SNS
Input Current Software Limit IAC_DPM = 12 A REG06 = 0x0180 (12 A with 2-mΩ RAC_SNS)
Charge Current Hardware Limit RICHG = KICHG / 12 A 4.2 kΩ for 15 A with 5-mΩ RBAT_SNS
Charge Current Software Limit ICHG = 15 A REG02 = 0x04B0 (15 A)

The default input sense resistor (RAC_SNS) is 2 mΩ, and the register allows for a range of up-to 50-A input
current limit. If lower currents are desired, it is possible to use a higher resistor, such as 5 mΩ. In this case, the
IAC_DPM register value should be multiplied by a factor of 2/5 to program the correct current. For example, if
a 5-mΩ RAC_SNS is used, and the register is programmed to a value of 0x60, the true maximum current across
the RAC_SNS will be: 12A * 2/5 = 4.8 A. Similarly, the KILIM parameter used to set the ILIM_HIZ pull-down resistor
should be scaled by 2/5. For example, with a 5-mΩ RAC_SNS resistor, a 6-A current limit would be achieved as:
RILIM = KILIM * (2/5) / 6A = 3.3 kΩ.
9.2.1.2.8 Power MOSFETs Selection
Four external N-channel MOSFETs are used for a synchronous switching buck-boost battery charger. The gate
drivers are integrated into the IC with 5 V of gate drive voltage. An external gate drive voltage can be provided
directly into the DRV_SUP pin for increased efficiency.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.

FOMtop = RDS(on) · QGD; FOMbottom = RDS(on) · QG (18)

The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as
an example the power loss is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-
resistance (RDS(ON)_top), input voltage (VIN), switching frequency (fS), turn-on time (ton) and turn-off time (toff):

Ptop =Pcon_top+Psw_top (19)

Pcon_top =D · IL_RMS 2 · RDS(on)_top; (20)

IL_RMS 2=IL_DC 2+Iripple 2/12 (21)

• IL_DC is the average inductor DC current;

• Iripple is the inductor current ripple peak-to-peak value;

Psw_top =PIV_top+PQoss_top+PGate_top; (22)

The first item Pcon_top represents the conduction loss which is straight forward. The second term Psw_top
represents the multiple switching loss items in top MOSFET including voltage and current overlap losses
(PIV_top), MOSFET parasitic output capacitance loss (PQoss_top) and gate drive loss (PGate_top). To calculate
voltage and current overlap losses (PIV_top):

PIV_top =0.5x VIN · Ivalley · ton· fS+0.5x VIN · Ipeak · toff · fS (23)

Ivalley =IL_DC- 0.5 · Iripple (inductor current valley value); (24)

Ipeak =IL_DC+ 0.5 · Iripple (inductor current peak value); (25)

• ton is the MOSFET turn-on time that VDS falling time from VIN to almost zero (MOSFET turn on conduction
voltage);
• toff is the MOSFET turn-off time that IDS falling time from Ipeak to zero;
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The MOSFET turn-on and turn-off times are given by:

QSW Q
t on = , t off = SW
Ion Ioff (26)

where Qsw is the switching charge, Ion is the turn-on gate driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):

Qsw =QGD+QGS (27)

Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:

VREGN - Vplt Vplt

Ion = , Ioff =
Ron Roff (28)

To calculate top MOSFET parasitic output capacitance loss (PQoss_top):

PQoss_top =0.5 · VIN· Qoss · fS (29)

• Qoss is the MOSFET parasitic output charge which can be found in MOSFET datasheet. It is recommended
to limit the total switch node capacitance CSW (nF) < 160/VIN; for example, for a 60-V application, it is
recommended to keep the total CSW < 2.67 nF
To calculate top MOSFET gate drive loss (PGate_top):

PGate_top =VIN· QGate_top · fS (30)

• QGate_top is the top MOSFET gate charge which can be found in MOSFET datasheet;
• Note here VIN is used instead of real gate drive voltage because the gate drive is generated based on LDO
from VIN, the total gate drive related loss are all considered when VIN is used for gate drive loss calculation.
• Alternatively, gate drive voltage can be supplied directly by external high efficiency supply into the DRV_SUP
pin. In this case, the power loss to drive the gates becomes: PGate_top =VDRV_SUP· QGate_top · fS
The bottom-side MOSFET loss also includes conduction loss and switching loss:

Pbottom =Pcon_bottom+Psw_bottom (31)

Pcon_bottom =(1 - D) · IL_RMS 2 · RDS(on)_bottom; (32)

Psw_bottom =PRR_bottom+PDead_bottom+PGate_bottom; (33)

The first item Pcon_bottom represents the conduction loss which is straight forward. The second term Psw_bottom
represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (PRR_bottom),
Dead time body diode conduction loss (PDead_bottom) and gate drive loss (PGate_bottom). The detail calculation can
be found below:

PRR_bottom=VIN · Qrr · fS (34)

• Qrr is the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;

PDead_bottom=VF · Ivalley · fS · tdead_rise+VF · Ipeak · fS · tdead_fall (35)

• VF is the body diode forward conduction voltage drop;

• tdead_rise is the SW rising edge deadtime between top and bottom MOSFETs which is around 45 ns;
• tdead_fall is the SW falling edge deadtime between top and bottom MOSFETs which is around 45 ns;

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PGate_bottom can follow the same method as top MOSFET gate drive loss calculation approach.
Power-path FETs for providing power to SYS from either VAC or VBAT are selected as N-channel MOSFETs.
The gate drivers are integrated into the IC with 10 V of gate drive voltage; however, the gate drive voltage can be
reduced to 7 V using the PWRPATH_REDUCE_VDRV register bit if desired.
9.2.1.2.9 ACFETs and BATFETs Selection
Four external N-channel MOSFETs are used for power path transfer. Two on the VAC side called ACFETs and
two on the VBAT side called BATFETs.
The proper trade off for selecting these MOSFETs depends on the SOA characteristics. All four FETs follow the
same trend hence the same FET can be used at all four places. It is essential to select a MOSFET that offers
close to 10A Drain Current at 30V VDS at DC and also has the capability to offer 100A Drain Current at 30V
VDS at 10 μs without breaking. Furthermore, the SOA characteristics should be such that the maximum junction
temperature should be at least 125°C. The FETs selected for this application are AONS6276 and can withstand
a voltage swing of up-to 30V from VAC to VBAT and vice-versa.

9.2.1.2.10 Converter Fast Transient Response

The device integrates all the loop compensation, thereby providing a high density solution with ease of use. For
faster transient reponse in reverse operating mode, the EN_CONV_FAST_TRANSIENT bit can be set to 1. If
device is not used in reverse boost mode operation, this section can be disregarded.
When the converter is operating in boost mode, the non-continuous inductor current flow to the load results in a
right-half plane (RHP) zero. The RHP zero location is:

V
RHPz = I IN, boost 2πL
1
(36)
IN, boost

For good phase margin, the unity gain bandwidth (UGBW) of the converter should be about 1/3 of the RHPz.
The boost output capacitor (Cload), and the converter transient parameters (R1, gm1) need to be scaled to move
the location of the UGBW of the converter.

Adiv × gm1 sR1C1 + 1 Vi 1

1≈ sC1 Io × 50m CloadRload (37)
1+s 2

The device adjusts Adiv, gm1 and R1 based on the output voltage and the EN_CONV_FAST_TRANSIENT bit
setting per the table below. During some boost case scenarios, the Cload needs to be adjusted to limit the
converter bandwidth.

BOOST OUTPUT EN_CONV_FAST_TRANSIENT = 0 EN_CONV_FAST_TRANSIENT = 1

Adiv C1
VOLTAGE gm1 R1 gm1 R1
≤8 V 1/5 75 pF 0.4 μ 600 kΩ 2μ 1.3 MΩ
8 V to 16 V 1/10 75 pF 0.47 μ 1 MΩ 2μ 1.8 MΩ
16 V to 32 V 1/20 75 pF 0.67 μ 2.8 MΩ 2μ 2.8 MΩ
>32 V 1/40 75 pF 2μ 2.8 MΩ 2μ 2.8 MΩ

As an example, assume the device operates in reverse boost mode from a 5V supply to provide a 7V boost
output voltage with load up-to 5A and 10μH inductor. The RHPz is approximately located at:

V
RHPz = I IN, boost 2πL
1
= 11.4kHz (38)
IN, boost

For best stability, the UGBW of the converter should be limited to 1/3 of the RHP zero, or 3.8kHz. If
EN_CONV_FAST_TRANSIENT = 1, the equation becomes:

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0.2 × 2μ jω × 1.3MΩ × 75pF + 1 5V 1

1≈ jω × 75pF 5A × 50m C × 1.4 (39)
1 + jω load2

Solving the above for Cload gives ≥674 μF capacitor requirement.

Conversely, if EN_CONV_FAST_TRANSIENT = 0, the UGBW equation becomes:

0.2 × 0.4μ jω × 0.6MΩ × 75pF + 1 5V 1

1≈ jω × 75pF 5A × 50m C × 1.4 (40)
1 + jω load2

Solving the above for Cload gives ≥51 μF capacitor requirement. However, the minimum recommended capacitor
for converter stability is 80 μF, so this minimum value should be used.

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9.2.1.3 Application Curves

CVAC = 160 µF, COUT = 160 µF, VVAC = 20 V, VBAT = 29.4 V (unless otherwise specified)

VAC = 20 V VBAT = 20 V ICHG = 5 A VAC = 20 V → 0 V VBAT = 20 V ICHG = 5 A

Figure 9-3. VAC Plug-In Power Up with 5-A ICHG Figure 9-4. VAC Un-plug Power Down with 5-A
ICHG

VAC = 20 V VBAT = 24 V ICHG = 5 A

VAC = 20 V VBAT = 24 V ICHG = 5 A Figure 9-6. Charge Disable via I2C with 5-A ICHG
Figure 9-5. Charge Enable via I2C with 5-A ICHG

VAC = 20 V VBAT = 24 V ICHG = 5 A VAC = 20 V VBAT = 24 V ICHG = 5 A

Figure 9-7. Charge Enable via CE Pin with 5-A Figure 9-8. Charge Disable via CE Pin with 5-A
ICHG ICHG

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VAC = 24 V VBAT = 20 V ICHG = 5 A VAC = 24 V VOUT = 28 V ICHG = 5 A

Figure 9-9. Buck Switching Waveform Figure 9-10. Boost Switching Waveform

VAC = 24 V VBAT = 24 V ICHG = 5 A VOC = 30 V VBAT = 24 V EN_CHG = 0 → 1

ISC = 3.5 A
Figure 9-11. Buck-Boost Switching Waveform
Figure 9-12. Max Power Point Tracking (MPPT) Full
Panel Sweep

VBAT = 24 V VAC_REV = 20 V ILOAD = 4 A VBAT = 24 V VAC_REV = 20 V ILOAD = 4 A

Figure 9-13. Reverse Mode Power Up with 4-A Figure 9-14. Reverse Mode Power Down with 4-A
Load Load

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VBAT = 28 V VAC_REV = 5 V ILOAD = 0.5 A → 4.5 A VBAT = 28 V VAC_REV = 28 V ILOAD = 0.5 A → 4.5 A

Figure 9-15. Reverse Mode Buck Transient Figure 9-16. Reverse Mode Buck-Boost Transient
Reponse Reponse

VBAT = 28 V VAC_REV = 48 V ILOAD = 0.5 A → 4.5 A

Figure 9-17. Reverse Mode Boost Transient Reponse

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10 Power Supply Recommendations

The power supply for the device is any DC voltage source within the specified input range. The supply should
also be capable of supplying sufficient current based on the programmed input current limit. The input supply
should be bypassed with a combination of electrolytic and ceramic capacitors to avoid ringing due to the
parasitic impedance of the connecting cables.
When device is operating in the reverse direction, the supply at the OUTPUT should follow the same
recommendations as the input supply mentioned above.

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11 Layout
11.1 Layout Guidelines
Proper layout of the components to minimize high frequency current path loops is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout.
Table 11-1. PCB Layout Guidelines
COMPONENTS FUNCTION IMPACT GUIDELINES

Buck high side FET, Buck input loop High frequency noise, This path forms a high frequency switching loop due
Buck low side FET, input ripple, efficiency to the pulsating current at the input of the buck. Place
capacitors components on the same side of the board. Minimize
loop area to reduce parasitic inductance. Maximize
trace width to reduce parasitic resistance. Place input
ceramic capacitors close to the switching FETs.

Boost low side FET, boost Boost output loop High frequency noise, This path forms a high frequency switching loop due to
high side FET, output ripple, efficiency the pulsating current at the output of the boost. Place
capacitors components on the same side of the board. Minimize
loop area to reduce parasitic inductance. Maximize
trace width to reduce parasitic resistance. Place output
ceramic capacitors close to the switching FETs.

Sense resistors, switching Current path Efficiency The current path from input to output through the
FETs, inductor power stage and sense resistors has low impedance.
Pay attention to via resistance if they are not on the
same side. The number of vias can be estimated as
1- to 2-A per via for a 10-mil via with 1 oz. copper
thickness.

Switching FETs, inductor Power stage Thermal, efficiency The switching FETs and inductor are the components
with highest power loss. Allow enough copper area
for heat dissipation. Multiple thermal vias can be used
to connect more copper layers together and dissipate
more heat.

DRV_SUP, BTST1, BTST2 Switching FET gate drive High frequency noise, The DRV_SUP capacitor is used to supply the power
capacitors parasitic ringing, gate to drive the low side FETs. The BTST capacitors are
drive integrity used to drive the high side FETs. It is recommended to
place the capacitors as close as possible to the IC.

LODRV1, LODRV2 Low side gate drive High frequency noise, LODRV1 and LODRV2 supplies the gate drive current
parasitic ringing, gate to turn on the low side FETs. The return of LODRV1
drive integrity and LODRV2 is PGND. As current take the path of
least impedance, a ground plane close to the low side
gate drive traces is recommended. Minimize gate drive
length and aim for at least 20-mil gate drive trace
width.

HIDRV1, HIDRV2, SW1 High side gate drive High frequency noise, HIDRV1 and HIDRV2 supplies the gate drive current
(pin trace), SW2 (pin parasitic ringing, gate to turn on the high side FETs. The return of HIDRV1
trace) drive integrity and HIDRV2 are SW1 and SW2, respectively. Route
HIDRV1/SW1 and HIDRV2/SW2 pair next to each
other to reduce gate drive parasitic inductance.
Minimize gate drive length and aim for at least 20-mil
gate drive trace width.

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Table 11-1. PCB Layout Guidelines (continued)

COMPONENTS FUNCTION IMPACT GUIDELINES

Current limit resistors, IC programmable settings Regulation accuracy, Pin voltage determines the settings for input current
FSW_SYNC resistor switching integrity limit, output current limit and switching frequency.
Ground noise on these could lead to inacuracy.
Minimize ground return from these resistors to the IC
ground pin.

Input (ACP, ACN) and Current regulation Regulation accuracy Use Kelvin-sensing technique for input and output
output (SRP, SRN) current current sense resistors. Connect the current sense
sense traces to the center of the pads, and run current sense
traces as differential pairs, away from switching nodes.

Input (ACUV), and output Voltage sense and Regulation accuracy ACUV divider sets internal input voltage regulation in
(FB, VO_SNS) voltage regulation forward mode (VACUV_DPM). FB divider sets battery
sensing voltage regulation in forward mode (VFB_ACC). Route
the top of the divider point to the target regulation
location. Avoid routing close to high power switching
nodes.

Bypass capacitors Noise filter Noise immunity Place lowest value capacitors closest to the IC.

11.2 Layout Example

Based on the above layout guidelines, the buck-boost PCB layout example top view is shown below including all
the key power components.

Figure 11-1. PCB Layout Reference Example Top View

For both input and output current sensing resistors, differential sensing and routing method are suggested and
highlighted in figure below. Use wide trace for gate drive traces, minimum 20-mil trace width. Connect all analog
grounds to a dedicated low-impedance copper plane, which is tied to the power ground underneath the IC
exposed pad.

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Figure 11-2. PCB Layout Gate Drive and Current Sensing Signal Layer Routing

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12 Device and Documentation Support

12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Revision History
DATE REVISION NOTES
December 2023 * Initial release

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ25750RRVR ACTIVE VQFN RRV 36 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BQ25750 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25750RRVR VQFN RRV 36 3000 330.0 12.4 5.3 6.3 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ25750RRVR VQFN RRV 36 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RRV 36 VQFN - 1 mm max height
5 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229484/A

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 PACKAGE OUTLINE
RRV0036A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

B 5.1 A
4.9

PIN 1 INDEX AREA

6.1
5.9

1.0 C
0.8
SEATING PLANE
0.08 C
3.7
0.05 3.5
0.00
2X 3.5
(0.1) TYP
11 18
32X 0.5
10
19

2X 37 SYMM
4.7
4.5 4.5

36X 0.3
0.2
0.1 C A B
1 28
0.05 C
PIN 1 ID
(OPTIONAL) 36 29
SYMM
36X 0.5
0.3
4226422/A 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RRV0036A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
(4.8)
(3.6)
36 29

1 28

32X (0.5)

37
SYMM
(5.8) (4.6)

(1.16)

(R 0.05)
TYP
(0.89)

10 19

36X (0.25)

36X (0.6)
11 18
(Ø 0.2) VIA
TYP (0.615) (0.935)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

0.07 MAX 0.07 MIN METAL UNDER

ALL ROUND METAL ALL AROUND SOLDER MASK
EXPOSED METAL

SOLDER MASK SOLDER MASK

EXPOSED METAL OPENING OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4226422/A 11/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RRV0036A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

(4.8)
12X
(1.03)
36 29

1 28

12X (0.96)
32X (0.5)

SYMM 37 (0.58)
(5.8)

(R 0.05) (1.16)
TYP

10 19

36X (0.25)

36X (0.6)
11 18
(Ø 0.2) VIA
TYP (1.23)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
72% PRINTED COVERAGE BY AREA
SCALE: 15X

4226422/A 11/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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