78 Semiconductor Integrated Circult Design (Unit - vij An embedded gate array gives the improved area efficiency and increaseq Performance of a CBIC but with the lower cost and faster turn around of an MGA. One disadvantage of an embedded gate array is that the embedded function is fixed. The space can be utilized properly and hence the cost can be reduced. The space provideg for a function cannot be altered. EZ5" PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are standard-ICs that are available in standarg configuration. PLDs, may be configured or programmed to create a part customized to @ specific application, and so they also belong to the family of ASICs. All PLDs have in common following features, 1) No customized mask layers or logic cells. 2) Design takes less time. 3) A single large block of programmable interconnect. 4) A two or more dimensional array of logic macrocells that usually consists of Programmable array logic. After this PAL, a latch or flip flop is placed. Fig. 7.5.1 shows a Programmable Logic Devices (PLD) die. anon oe Macrocell ODSOSooooR! Programmable Interconnect 5 | Sanaa SOR PLDs have many of the advantages over semi and full-custom ASICs as given below, 1) Reduced Power requirement. 2) Higher densities. 3) Reduced Space requirement, 4) Less Production cost, 5) Design security, Because of the above mentioned advantages, various types of PLDs are available today, The simplest type of programmable IC Is a Read-only Memory (ROM). ROM uses a metal fuse that can be blown permanently (called as a programmable ROM or PROM). An electrically PROM (EPROM), use programmable MOS transistors whose characteristics are changed by applying a high voltage, VISI DESIGN PROFESSIONAL PUBLICATIONS @ scanned with OKEN Scanneri aren Inde graied GUN Deane UR I ss conductor Integrated Cireuit Design [Unit Semi An EPROM data can be erased either by using another high voltage (called as dectrically erasable PROM, EPROM) or by exposing the device to UV light (UV-erasable pROM or UVPROM). We can also create a family of flexible and programmable logic devices in a large array of AND gates and an array of OR gates, called logic arrays. The first produced logic array js Programmable Array Logic (PAL). We could place a logic array as a cell on a custom ASIC. qhe device produced of this type of logic array is called a programmable logic array (PLA). There is a difference between a PAL and PLA : a PLA has a programmable AND logic array, or AND plane, followed by a programmable OR logic array, or OR plane, a PAL has a programmable AND plane and in contrast to a PLA, a fixed OR plane. In PLA and PAL the final output function is same. One prefers a AND logic and the other uses OR logic. [ESE Programmable Logic Arrays (PLAs) & Several types of PLDs are commercially available, The first developed was the programmable logic array (PLA). A Programmable Logic Array (PLA) has programmable AND like a ROM, The arrangement of gates is fixed in PLAs. Hence, they i architecture | PLDs. ps In order to store logic expressions, connections between the MOSFET gates and the vertical lines in the AND array and algo’ connections between the MOSFET gates and the horizontal lines in the OR array are set up by semiconductor manufacturers during fabrication according to’customer specifications, [ERE Architecture of PLA The block diagram of a PLA is depicted in Fig. 7.5.2 Input utters ond Invertors MRCE EN w | wii itl | pee cca) ee VLSI DESIGN : @ scanned with OKEN Scannerconductor 25 laid eHealth THe Aid ca be Pealeg in gum“oF products fm PUA eérripHbGs 'aeoli@ctior> SP AND’ gates THAL feeds a set of OR gates, As shown iy is Fig. 7.5.2, the PLA's inputs x;4.)-..Xq pass-through-a set of buffers (w ich provide tg the ;truevalue:ancicomplementicof each Input) Irito’a circdilt” block’ called ah AND ane OFAND atraYpoubog dent = ESE eh eek 7 wine Wei i fe oes Se? _Py.bach of these term _békdntigared t&implemeht any AND funetion oF x,, inputs toran-OR: plane;\which producés‘the outputs: to,realize anyisum oP; f T 2yevIe : OVA 3 eseigie7 8 3th ts “ely hos 'the'‘Gatieve oF a BLA, Tn Fla. 27 Ro the, ANBUgate, that prddited’pi" shoWa Connectéd’to the inputs x; and x,. Hence P, = XX. Simllary | W (eA. erersabre?Girec REAP HET BASE ase Py = XaX3y Py = X3x9x3 and P, = x{RA-Brdgfattiable”conections also exist for the OR. plane. Qutput, f(s, connected: to-product; terms -Py Pp-and Pz.Ttitherefote! realieee?the Function, Similarly, output, 33 Kgky\orgX ple X_XBRIPPAIROG|A IS 7/5 232d eBleeS eR BIN Programmed jto,implement’ thecfunction described above, by programming’ té"AND Sty OR planes differently, each of the outputs F, and Fy@duld implement Varlbug alaaie® Of x4, X> and x5... or bts 29168 TAIT2OM arid ns arid brs 2915p THI2ZOM ori A pohub es wise 7032 be nod 2noizz91gx9 Jipol S102 OF I9b10 At S116 QUA orld ni 2oril Ieviney KO orld ai esniil Isinosh Visage iomoseua oJ gnibro226 noidesidst OR Plane , fo auuostidatA Li, 2 o8ls bre To foiwepamod oT PROFESSION AT prrerie. @ scanned with OKEN Scannerr Oe - ri sms AoW Ww H - tay sonidneion © Ade w aqiria. npizab-morey ol lovsno2 VISI DESIGN: a @ scanned with OKEN ScannerTemiconductor Integrated Circuit Design Tae Wi 2M 712 ; i d using NOR gates, we apply DeMorgan’, lay oa Mt tain the product terms. For example, abc can be written as errs} obtain the p! @ programmed 3, b, ¢ in the AND 9 an’s law. Hence, W' lane according se betirees use pMOS enhancement devices to pull up row ang Olu (not a, b, €). 5 voltages, EEARH Advantages and Disadvantages of PLAs As the logic is implemente: Advantages 4) There is no need for the time-consuming logic design of random-logic gate atv and even more time-consuming layout., 2)” Design checking is easy and design change is also easy. 3) Layout is far simpler than that for random+logic gate networks and thus is far less time-consuming. 4) When new IC fabrication technology is introduced, we can use previous design information with ease but without change, making adoption of the new technology is quick and easy. 5) Only the connection mask needs to be custom-made. Disadvantages 1) For storing the same functions or tasks, PLAS can be smaller than ROMs, generaly the size difference sharply increases as the number of input variables increases, 2) The small size advantage of PLAs diminishes as the number of terms in a disjunctive form increases. Thus, PLAs cannot store complex functions, +» functions whose disjunctive forms consist of many product terms. 3) PLAS offer enhanced flexibility in the design of complex systems. They are efficient for implementing functions with larger number of product variables in the product terms. For simple functions, however, they waste chip area and effect speed. TZXEM Applications PLAS are used in the control design change and check. Also, code conversions, bus priority logic of microprocessor chips because of the ease of PLAS are employed for microprogram address conversions, Fesolvers and memory overlay, When a manufacturer intends to market custom design Is very time consuming, high performance can be quickly made @ new product, PLA is a choice. Since a fut & number of different custom-design chips with I PLAS are used in the control logic. NSLSESIGN PROFESSIONAL PUBLIGATIONS @ scanned with OKEN Scannertr GAProsrammable Array Logic (PAL) The PAL Is a spe ; al case of the Programmable Logic Device (PLD) in which the AND ray 1s programmable and OR array is fixed, The basic structire’ of the PAL Is shown in fig. 7-5-6. Because only the AND array is programmable, the PAL is less expensive than the more general PLA and the PAL is easier to program. For this reason, logic designers frequently use PALs to replace individual logic gates when several logic functions must be realized, ' 1 ' PLA 1 1 1 Input Lines ‘m Output Lines: WEEE The basic Structure of PAL Seament hh hh i f 1 e) output A+ th alt E (b) Programmed (2) Unprogrammed peMER TI An Unprogrammed and Programmed PAL Segment PROFESSIONAL PUBLICATIONS VLSI DESIGN 5 ih @ scanned with OKEN Scannerrato clreult Daslgi (Un (Semlcondvetor _The symbol! [3— in Fig. 7.5/2arppregents an input:bufferswithenaneinVetted ang i { 5 ND gate inputs, inverted outputs. A buffer is used, since each PAL input must drive many Al a ! Tk) ‘are’ SelectlvAly' Bibl to when.the PAL. is; programmed, the fusible: links (Fj, F2 é : leave the desired, connections to,the)AND_ gate. inputs: Connections tol¢heTAND Gate ifpits a PAL are represented by Xs.as.shown,|n, Fig. 28/8) vino 204 © 2 a Se : : isvonse &? it ners ae gaporg of 1ei269 ei he PAL’ segment-of Fig. 7.5.7, to realize the function 3 nd I’, linés are connected to the first AND ced to the other-gate (see Fig. 7.5.7(b)). pee PALs frave fremit0 to'/20 input id from 't6 10 outputs, ‘As an example-we-will-us LT, +0, ¢ iy fe Xs indicate that gate and thei1',| and 1, lines are} c with 2 to 8 AND] gates ‘driving each OR gate; PALS"are also available that contain D flip- flops with inputs driven from the pr grammable array logic.-Such PALs provide a convenient way or realizing sequential networks. Fig. 7,5.9 shows) a segrient of a sequential PAL. The D flip-flop is driven from 2 OR Gafe, Which is.fed by two! AND gates. The flip-flop output is fed back tb the progfammable|AND. array. through. a-buffer. Thus the AND gate The Xs on the diagram show the realization inputs can be connected to A, Ai, B, B', of the next-state equation. ‘i rid ot = De The flip-flop output, EN = 1. AA BB QQ bommeroarggl (2) Programmable’ AND’ Array! | E @ scanned with OKEN Scannercmiconductor Integrated ch ‘i : reult Deal lon [Unit - vig fl Complex Pr; ograr : ‘grammable Logic b - The PLDs such as PLAs ang evices (CPLDs) 4 PALs, . The » have outputs: These devices, therefore, can sy limited number of inputs, product terms and outputs only. For implementati PPOrt Upto about 32 total number of inputs and cE 715 be used. [ERE CPLD Architecture Fig. 7.5.10 giv . ck yo bl i es the block diagram -of a CPLD. It consists of a number of PALHike blocks, 1/0 blocks and a set of interconnection wires. f PAL-like Block 018 O71 x 8 a 9° 3] PAL-like PAL-like Block Block mRENETY structure of a Complex Programmable Logic Device (CPLD) | 7.5.11 gives a internal structure of PAL-like block with wiring structure 3018 O71 1/0 Block PAL-Like Blocks + Fig- and the connections to it- ple (real CPLDs typically have about 16 5 3 macrocells (' ch consisting of a four-Input OR gate (real CPLDs usually oeach OR gate), The OR-gate ‘output Is connected n ‘OR (XOR) gate, One Input to the XOR he XOR gate The PAL-like block includes macrocells in a PAL-like block), 2 t provide between 5 and od an Exclusive ar type of logic gate aca ae ft 2 be programmably connected t gate in Fig. 7-5-2 if, then the XO 2 or state buffer, complements the 0! e buffer also includes @ flip ee pin to be used elther a5 an ‘output from the GPLD or as.an t a a switch that allows nai eee Vier nesiGN @ scanned with OKEN ScannerSemiconductor Integrated Circuit Design (Unit vay 716 eric ia hit of the CPLD VO Block : The 1/0 block is used to drive signals to the pins of the CPLD device at the @ppropriate voltage levels with the appropriate Current, Usually, a flip-flop is . This is done on outputs so that clocked signals can be output directly to the pins without encountering significant delay. Interconnection Wires : The interconnection wiring contains programmable switches that are used to connect the PAL-like, blocks. Each of the horizontal wires can be connected fo some of the vertical wires that it crosses, but not to all of them, Extensive has been done to decide how many switches should be Provided for connections-be the wires, The number of switches is chosen cells, E2PROM cells or Flash EPROM cells, VLSI DESIGN Fs PROFESSIONAL PUBLICATIONS @ scanned with OKEN ScannerOO pal CPLD Programming x Most CPLDS contains the same s. Programming of the switches : CPLDs may hi 3) barge 'y have more thai ‘i 2 often fragile and easily bent. n 200 pins on the chip package and these pins ar’ 2) A socket is required to hold the chi sockets are very expensive, hen For these reasons, CPLD devices usually support the ISP technique. A small connector is included on the PCB that houses the CPLD and a cable is connected between that connector and a computer system. The CPLD is programmed by transferring the programming information generated by a CAD system through the cable, from the computer into the CPLD. The circuitry on the CPLD that allows this type of programming has been standardized by the IEEE and is usually called a JTAG port. Tt uses four wires to transfer information between the computer and the device being programmed. The term JTAG stands for Joint Test Action Group, Fig. 7.5.12 illustrates the use of a JTAG port for programming two CPLDs on a circuit board. The CPLDs are- connected together so that both can be programmed using the same connection to the computer system. Once @ CPLD is programmed, it retains in the programmed state permanently, even when the power supply for the chip is turned off. This property is called non-volatile. programming. ip in a programming unit. For large CPLD packages, ice they cost more than the CPLD device itself. BEDIRZEEED CPD Programming wate PROFESSIONAL PUBLICATIONS ait @ scanned with OKEN Scanner78 Femiconductor Integrated Clreuit Deslgn (Unit vy Field Programmable Gate Arrays (FPGAs) D is known as field-programmable gate FPGA) is a semiconductor device that can hence the name “field programmabjer than 20,000 gates. FPGAs blocks for implementation One of the most sophisticated types of PL! array (FPGA). A Field-Programmable Gate Array (Fi be configured by the customer after manufacturing, FPGAs can be used to implement a logic circuit with more not contain AND or OR planes, Instead; they provide logic 4 “the required functions. The general structure of an FPGA is shown in Fig. 75.13. 1p three main type of resources, contail 1)” Logic block to implement a variety of logic function. 2) 1/0 blocks for signal conditioning at the chip 1/0 pins. 3) _Interconriection wires and switches, to route the signals between the logic blocks, 1/0 Block. : ott 3 3 e Q eee al et Ir 1/0 Block General Structure of an FPGA _The Jogle blocks are arranged In a two-dimensional array and the interconnection organized as horizontal and vertical routing channels between rows and, wires ai itches columns oflogic blocks. The routing channels contain wires and programmable hat allow the Jogic blocks to be: interconnected in'‘many ways. ae PROFESSIONAL PUBLICATIONS VLSI DESIGN @ scanned with OKEN ScannerFig. 7 WO loc: cent to logle blocks hol Mable switches, the light filled boxes ether Nect the fogic block input and output Programmabl (such a8 a vertical wire to a horizontal © Switches and wires in an FPGA varies in that con "amercially available chips, Fig. 7.5.44 illustrates the essential cha : acteristics of an F ) The mask layers are not customized pH 1) Amultidimensional array of programmable interconnect surrounds the basic logic cells. 3) Programmable 1/0 cells surround the core. 3) Design turn around time is in the order of hours. The cell area Is surrounded by programmable interconnect. This helps in making nterconnects easy. The optimum utilization of area is also possible, Programmable Basic Logic Celf JODOOOooGOOD000aeL ble "erconecr GoeeooooooooCoOUooOno WEEZEEED 4 Fele-Proorammable Gate Array (FPGA) Die HEHE Configurable Logic Blocks (CLBs) typically has a small number of Inputs and one output. Each ef Te veomaibed In such a way that it can implement different _ * h configurable logic block has al and sequential functions. Eact ore Fa meh contains storage cells that are used to Implement a small ; ae a eal is capable of holding elther lagle "0" or logic “t’ value, This stored logic function. Eacl Value is then produced as the output of the cell, A logic block in logic block of an FPGA PROFESSIONAL PUBLICATIONS wee ae Ra ll @ scanned with OKEN Scanner7.20 Semiconductor Integrated Circult Design [Uniy “Vij Fig, 7.5.15 shows the structure of a small LUT. It has two inputs, xeand x2,and ong output, F It is capable of implementing any logic function of two variables. Because two-variable truth table has four rows, this LUT has four storage cells. One cai corresponds to the output value in each row of the truth table. ‘The input variables y. and x, are used as the select inputs of three multiplexers, which, depending on the valuation of x, and x,, select the content of one of the four. storage cells as the output of the LUT. F (output) WGEZEEED Circuit fora twornput Lor Example : To see how a logic function canbe realized in the two-input LUT, consider the truth table in Table 7.5.1. The function F from this table can be stored in the LUT as illustrated in Fig. 7.5.16. The arrangement of multiplexers in the LUT correctly realizes the function F. When x, = x, = 0, the output of the LUT is driven by the top storage cell, which represents the entry in the truth table for x,x, = 00. Similarly, for all valuations of x; and x2, the logic value stored in the storage cell corresponding to the entry in the truth table chosen by the particular valuation appears on the LUT output. Providing access fo the contents of storage cells is only one way in which multiplexers can be used to implement logic functions, ds Ea Truth Table of Logic Function F = %,X, + X,Xy VLSI DESIGN @ scanned with OKEN Scannervy . Oe y . _~coadweter Integrated Creal a ! Destan [Unit = Vij WERASRUN Storaee carconents ne wT [EEE Configurable V/O Blocks nfigurabl A configurable 1/0 block, shown in Fig: 7.5:17 Is used to bring signals onto the chip d an output buffer with and send them back off again, It consists of an Input buffer an there are pull up resistors on the f the output can usually be w rate of the output tri-state and open collector output controls, Typically, outputs and sometimes pull down resistors, The polarity of programmed for active high or active low output and often the sle\ can be programmed for fast or slow rise and fall times. In addition, there is often a flip- flop on outputs so that clocked signals can be output directly to the pins without encountering significant delay. It is done fo lay on inputs so-that there is not much del 2a signal before reaching a flip-flop which would increase the device hold time requirement. Local ~ Bus ‘open Slew gels BOA) Collector’ Rate Express BUS 1° It Pull-up Local Bus xpress BUS Express Bus ‘TTLCMOS: — express BUS Y Local bus FPGA Configurable 1/0 Block PROFESSIONAL PUBLICATIONS @ scanned with OKEN ScannerSemicondvetor Integrated Circuit Design [Unit vy 7.22 [EXE Applications of FPGA 1) FPGAs can be applied to a very wide range of applications including random logic, integrating multiple SPLDs, Device controllers, communication encoding and filtering small to medium sized with SRAM blocks and many more. Prototyping of designs later to be implemented in gate arrays. Prototyping might 2) be possible using only a single large FPGA (which corresponds to a small gate array in terms of capacity). 3) Emulation would entail many FPGAs connected by some sort of interconnect, for emulation of hardware, Quick Turn (and others) have. developed products that comprise many FPGAs and the necessary software to partition and Map circuits. 4) Another promising area for FPGA application is the usage of FPGAs as custom computing machines. This involves using the programmable parts to ‘execute’ software, rather than compiling. the ‘software for execution on a regular, CPU. e E229 Programmable Switching Technologies PLDs use different technologies to allow programming of the dévice. In this séction, we shall discuss the various methods to implement the user-programmable switches that are the key to the user-customization of PLDs. The first type of user-programmable switch developed was the fuse technology used in PLAs. For higher density devices, where CMOS dominates the IC industry, different approaches to implementing programmable switches have been developed. For CPLDs the main switch technologies (in commercial products) are floating gate transistors like those used in EPROM and EEPROM and for EPGAs they are SRAM and antifuse, Each of these is briefly discussed below, 2 1) Fuse Technology : Fuse programmable switch is used ‘In simple PLDs (SPLDs). In fuse technology, all the fuses are initially connected between conductors, which normally exhibits low impedance. Fuse are usually acts as closed circult path as shown in Fig. 7.5.18. By applying pulses of appropriate high voltage and current to the device Inputs, the designer remove selectively undesired fuses in Programming. These devices are one time programmable. VLSI DESIGN PROFESSIONAL PUBLICATIONS ~ @ scanned with OKEN Scannery an [Unit yy 7 “Vi 71.23 yp Fuse Technology 4) Antifuse Technology : In an ant aOR MRE thal eihtths Ge MO etn by a dielectric Tee eRe sone xhibits high impedance, So an antifuse is normally an open it breeks ‘down, curr ion of appropriate programming voltages across the dielectric, Beene aaa ent flows and a permanent, low resistance (200 - 500 9) a je between the conductors. This can be thought of as 2 permanent link (or connection) between two. wire segments In Simple Words, When an antifuse is unprogrammed, the dielectric isolates the top and bottom conductors thus no -connection between ‘conductors. ‘+ When an antifuse is programmed, the dielectric provides a low-resistance link to conductors. WIRE sn uate ta rat [ne DIFFUSION as SILICON SUBSTRATE ‘Antifuse Structure som transistor is used as a programmable hes 1 An EEPROM of EPROM © 2 ae the transistor between two wires In a way that facilitates switch by al ae d-AND or OR functions, This Is Illustrated in Fig: 7,5.20, which Implementation ey might be connected In an ‘AND oF OR plane. as tt EPROM transistors ; shows PROFESSIONAL “PUBLICATIONS ~ f @ scanned with OKEN Scanner Visi DESIGNwire to logic level “0” by, c EPRON transistos, if that ingut is part of the eevoeing pect tres, 8 that are not tnvelved for a product term, the appropriate . trasssten cn wet tured off. A Sagram for an EEPROM based Gey Inout Wire +5V EZGHEDESIGN APPROACH 4 Design fiow defines the sequence of procedures to be followed to obtain the rai chp in an error-free way. ASIC design flow starts with the design entry specification. Fig. 7.8.1 depicts the design approach for 2 VLSI chip. 1) Design Entry : Design is entered into an ASIC design system using Hardware Description Language (HDL) such as VHDL or veiilog or through schematic entry, 2) tesle Synthesis : Logic synthesis provides a link between an HDL (verilog or VHDL) ~ end a netlist. Logic synthesis tools are used to map the design into a gate level Gesign in the cell brary. Logic synthesis ensures that the design is appropriate fer Level Sensitive Scan Design (SSD). 2 _rutm Porttioning : Divides a lage system into ASIC size pieces. The main objective is to, ‘ i) Partitioning a targe system into smaller system. 3) Minimize the number of pins, ‘VLSI DESIGN PROFESSIONAL PUBLICATI @ scanned with OKEN ScannerEs SS Keane TTT Ta RTT : aa in {Uni = ii) Minimize package cost an 738 wy) Minimize the number , mb y) Keep each As; SF OF external connections between the ASIC: IC smaller than a m Cee pre-layout Simulation ¢ ot ee, ’ simulations include togi Verifyin cae tiny of the design. Initia! pretavout ut no int 5) Fleer Planning : Arrange the ii ferconnect delays. of floor-planning are to mini locks of the netlist on the chip. The main objective pienninG WAAOEgnae a mize the chip area and minimize delay. In floor vargbe BOSE the Aes es sizes and set the initial relative locations of the the interconnect delay by z eh, Floor-planning allows the designer to predict planning are to, sstimating interconnect length. The objectives of floor- i) Arrange the blocks on a chip. i) Decide the location of the 1/0 pads. ii) Decide the type of power distribution of power pads: iv) Decide the type of power distribution. v) Decide the location and type of clock distribution. 6) Placement : Defines the location of the logic cells within the flexible blocks and sets aside space for the interconnection to each togic cell. The goals of placement are to, i) Minimize the total estimated interconnect length. i) Meet the timing requirements for critical nets. ii) Minimize power dissipation. 7) Routing : Routing simply means drawing paths from the source to the destination ina layout, In the physical design flow, after the floorplan and placement process, the routing Is done. In this step, the Interconnection lines are drawn for the signal, power, ground and clock nets. Although It seems @ pretty simple process, it is a very hard problem to solve when the number of connections is very large. 8) Extraction : After routing Is completed, the exact length and position of each Is known. The parasitic capacitance and resistance Interconnect for every nel associated with each Interconnect, via and contact can be calculated. The data Is. generated by circult-extraction tool. 9)~-Post-layout Simulation + Verifying the functionality of the design after added loads of the interconnect. ; ‘VLSLBESIGN PROFESSIONAL PUBLICATIONS scall @ scanned with OKEN ScannerPre-layout Simulation ele VHDL/Verilog 2) a . Logic Netlist = poo Post-layout} FUT Chip Simulation | =] a 1. Block Physical Circuit {} Design \ Logic ied Rael eee Design Approach VisipEsign SS _ @ scanned with OKEN Scannera2 ne Teetne Oa ERIM INTRODUCTION To TESTING Once we have designed our logic function, : manufacturer to separate fay ibs tom good ones. VLSI testing deals with the techniques to idéntity the fault in the design or IC. If there Is no fault in the die (chip, it Is then packaged and sold. Fault may be defined as @ manifestation of a manufac device, faults may be caused by mechanism ranging from crystalline dislocation 5 lithograph errors to bad etching of vias. This chapter presents different testing methog, to verify functionality and what types of faults occurred in the design. ERG NEED FOR TESTING The role of testing is to detect whether something went wrong and the role of diagnosis is to determine exactly what went wrong and where the process needs to be altered. Therefore, correctness and effectiveness of testing is most important for quality products. VLSI chip testing is done in several different places by several different types. of people. When a new chip is designed and fabricated for the first time, testing shoulg verify correctness of design and the test. procedure. This often requires the involvement of the design engineer and the testing may even take place in the design laboratory rather than in a factory. Based on the result; both the design and the test procedure may be changed. This is called verification testing. we must develop tests to allow Testing a chip can occur, At the wafer level. At the packaged-chip level. At the system level. ‘At the board-level. © In the field. In the first stage, the die. is tested at the wafer level. A test program is used to test the die, The test program applies a set-of input bit patterns’ which are known as test vectors and checks the test response. Any chip that fails this test is marked as a bad chip. | This test is often called the production test. In the second state, the die is separated out from the wafer and packaged and it is again tested with the same test vectors. This 's called the find test or package level test, The chips that are shipped to the customer must pass the production and final test, At the customer end, the chip is placed in the board and the board is tested. If any chip malfunctions at the board level test, it is sent back to the manufacturer. The manufacturer has a fallure analysis team which looks into the problem to find out the failure mechanisms, In the system level test, the board Is placed in the system and checked if the system works as specified, The last stage of testing is done at the fleld level, when an end-user tests the system while using a system VLSI DESIGN i PROFESSIONAL PUBLICATIONS a @ scanned with OKEN ScannerSa from chip level to board level a 4 ind also fro importance to“detect faults 1M board level to sys rt ror example, the cost to a on i earller level, $0 as to eae saranctng ‘ost. in Table 8.2.1. any for detecting a fault at different levels is as shown | Table 8.2.1 | ty | RAUEEEW Cost of Testing at biverent Levels Level das Wafer level $0.01-$0.10 $0.10-$1 Packaged chip Board level Systemlevel. | $10- $100 Field level - | $100-$ 1000 Hence if faults can be detected at the wafer level, the cost of manufacturing can be kept lower, The tests performed at various levels are categorized as two types, namely, 1) Functionality test. 2) Manufacturing test. ESE Functionality Tests Functionality tests verify the functionality of the device or circuit, i.e., whether the device yield the correct output or not for a particular input vector. Does this adder, add? Does this counter, count? Does this state machine yield the right outputs at the right clock cycles? The functionality tests invol ve providing that the circuit is functionally equivatent to some specifications. The specification can be a hardware description language like verilog, VHDL, ABEL, CUPL, etc: The functionality of the design can be verified using the simulator by forcing some input vectors and observing the expected output. Functional tests cover a very high percentage of modeled (example, stuck type) faults in logic circuits and their generation. Functional vectors are understood: as verification vectors, which are used to verify whether the hardware-actually matches its specification. ations and Test Plan : The device specification document initiates Functional Test Specific the development activity and contains the following information, algorithms to be Implemented. 1/0 signal characteristics eristlc~ ‘etc.), data and control signal behaviour, clock rate. signal levels, cessor, memory, analog etc. Functional charact (timing waveforms, Type of device-logic, micropro ustom stal 6 bnatooy: cust ndard cell, ete. MoS or gate array, = 2 PROFESSIONAL PUBLICATIONS VLSI DESIGN 2] @ scanned with OKEN Scannera4 = on) Environmental characteristics-operating temperature, range, suPPIY, voltage, humidity © ise etc. Reliability acceptal characteristics etc., The test program generation is shown in nce quality level (defective parts per million), failure rate, Fig, 8.2.1. “architecture and |. Logic Design, Verification and Test Generation using HDL ‘and Simulators, If the Functional Tester Data, Test is OK ‘Types of Tests, 2 Timing Spaces” zs. etes Dosh wugquo digit Smif DISIY E2223 Manufacturing Tests , Manufacturing tests. are..used to,.verify, Successful verification, testing, usually, results in; some; goodchips..A successful verification also signals. the beginning of production..Rroduction means-large scale manufacturing Fabricated, chips, are;tested,dn.the, factory; This:istest.istoxdiseover ‘any faults caused di manufacturing defects ion.erronsTypical’defacts Include,’ °' fn siigoitioaga 2li eariadsm ytlsv ithatceverygate operates as. expected. jue to % Layer-to-layer short: “6° rsconeties altegtO29® 2atvob oT nla trot AD sno otteariaint pniwallo’ add enisic 4 Thin-oxide shorts'to substrate or well, ignple OF .botnemaliqmi sd of emedine 7 “Nodes ‘shorted te, power POT RHM Aya (oa ala % | Nodes sorted to each other. ~@ Inputs floating/out fine vroment ¢ isconnected. bushisie” moteus vere si PROFES SSIONAL PUBLICATIONS VLSI_DESIGN @ scanned with OKEN Scanner6 — NOS Testing [Unlr< vin 3 a. Tests are normally carried the verification of ir Gi i . the wafer: levdlito separate the bad die. Apart from following tests, 70 integrity 1s also testéd through completing the YO-level te ) Vl ests (Ley, checking the iheléé'matgin for TTL, ECL or CMOS 1/0 pads). 2) Electrical Parametrig tests, 3) Speed test, 1 4] 1 4) Tppg test. | a ee manufacturing: test generation assumes. that the clrcuit/chip functions correctly and ways of exercising all gate inputs and of monitoring all gate outputs are required. ERIS Test PRINCIPLES It is essential for rats to be detected ia, early as, possible in the manufacture of a system. A critical factor in all LSI and.VLSI-design is the need to incorporate methods of testing circuits. The solution to the problem:of testing. combinational logic is to generate a set of test patterns which will-detect-all-possible fault conditions. Fig. 8.3.1 shows 2 combinational circuit with n-inputs, To cuit completely, we need 2" number of possible input combinations” (oF test vectors). This Is called exhaustive testing and is very effective,, but is, onlynpracticable.when|nisctelatively’small.o! 0° Combinationat Logic EES Combinational Crcuit with-n-inputs In case of sequential circuits, the required test. vectors would. be 2" if there are m number of registers. To understand this better, let us consider an example. For a VLSI chip, if, there, are) 50; inputs, and: 50 registers Inside, it requires 20° («+ °1.27 x 10°) test vectors to, fully, test jt, out, Now, ;if,testing one pattern requires 1ns time;:testing ‘all the test vectors would require 4 x 10?.years.,.This-example. indicates that there must be Innovative ways of testing the chip without applying so many test vectors, but catch all possible defects or most of the defects. tluot EERE rout Models) sviev ( ‘Can’we’enstré that the chips'coming off the manufacturing unit are totally defect free? No; It Is'Impossible.’A'somewhat more reallstic goal \s to choose one or several fault. models, Fault models deals ith the existence of godd or bad parts, The faut ig the: manifestation of manufacturing defects In ‘an Ic, \6 Othe fault models aré used to Identify different types of faults, There a many fault models. A list of fault models Is shown In Table 8.3.1, ne VLSI DESIGN PROFESSIONAL. PUBLICATIONS a @ scanned with OKEN Scanner