Fremont Micro Devices Preliminary FT25H16

FT25H16
16
ASHEE
SHEE
DATASHEET

© 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H16-page1

Fremont Micro Devices Preliminary FT25H16

CONTENTS
1. FEATURES .................................................................................................................................................4

2. GENERAL DESCRIPTION.........................................................................................................................6

3. MEMORY ORGANIZATION .......................................................................................................................8

4. DEVICE OPERATION ................................................................................................................................9

5. DATA PROTECTION ................................................................................................................................10

........
....
6. STATUS REGISTER ................................................................................................................................12

................
.................
....
7. COMM ANDS DESCRIPTION..................................................................................................................14

7.1. W RITE ENABLE (WREN) (06H) ...............................................................................................................

...........................
......................... 18
7.2. W RITE DISABLE (WRDI) (04H) ...............................................................................................................
...........................
............... 18
7.3. READ STATUS REGISTER (RDSR) (05H OR 35H).....................................................................................
...........................
.................... 18
7.4. W RITE STATUS REGISTER (WRSR) (01H) ...............................................................................................
............................
............... 19
7.5. READ DATA BYTES (READ) (03H)...........................................................................................................
.....................
........... ......
.... 19
7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .......................................................................
...........................
.................... 20
7.7. DUAL OUTPUT FAST READ (3BH) ............................................................................................................
............................
..................... 20
7.8. QUAD OUTPUT FAST READ (6BH) ...........................................................................................................
......
... .....................
................. 21
7.9. DUAL I/O FAST READ (BBH) ...................................................................................................................
...........................
................ 22
7.10. QUAD I/O FAST READ (EBH).................................................................................................................
............
... ................
............. 23
7.11. QUAD I/O W ORD FAST READ (E7H).......................................................................................................
...........................
.............. 24
7. 12. PAGE PROGRAM (PP) (02H) ................................................................................................................
........................
............. ... 25
7. 13.QUAD PAGE PROGRAM (QPP) (32H).....................................................................................................
(32H)...................
(32H) ............ 26
7.14. SECTOR ERASE (SE) (20H)) ..................................................................................................................
..........................
.................. 27
7.15. 32KB BLOCK ERASE (BE) (52H)...........................................................................................................
2H)
H).............
............. 28
7.16. 64KB BLOCK ERASE
E (BE) (D8H)
(D ..........................................................................................................
.... 28
7.17. CHIP ERASE (CE)
E) (60/C7H) ....
..................................................................................................................29
7.18. DEEP POWER
R--D
DOWN
WN (DP)
( (B9H)
(B9 .........................................................................................................29
(B9H
7.19. RELEASE M DEEP
E FROM EE POWE
OWER-DOWN AND READ DEVICE ID (RDI) (ABH) ............................................... 30
OW
7.20. READ
D MANUFACTURE ID
ID/ DEVICE ID (REMS) (90H) ..............................................................................31
7.21. READ IDENTIFICATIO
ENTIFICATIO (RDID) (9FH) .....................................................................................................32
DENTIFICATION
7.22. HIGH SPEED
P MO
ODE (HSM) (A3H) .........................................................................................................32
7.23. CONTINUOUS
ONTI READ MODE RESET (CRMR) (FFH) .................................................................................33
7.24. PROGRAM
RA /ERASE SUSPEND (PES) (75H) ............................................................................................. 33
7.25. PROGRAM/ERASE RESUME (PER) (7AH) ..............................................................................................34
7.26. ERASE SECURITY REGISTERS (44H) .....................................................................................................34
7.27. PROGRAM SECURITY REGISTERS (42H) ................................................................................................35
7.28. READ SECURITY REGISTERS (48H) .......................................................................................................36

8. ELECTRICAL CHARACTERISTICS........................................................................................................37

8.1. POWER-ON TIMING .................................................................................................................................37

8.2. INITIAL DELIVERY STATE ........................................................................................................................37
8.3. DATA RETENTION AND ENDURANCE ......................................................................................................... 37

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Fremont Micro Devices Preliminary FT25H16
8.4. LATCH UP CHARACTERISTICS ..................................................................................................................37
8.5. ABSOLUTE MAXIMUM RATINGS ................................................................................................................38
8.6. CAPACITANCE MEASUREMENT CONDITION ...............................................................................................38
8.7. DC CHARACTERISTICS............................................................................................................................39
8.8. AC CHARACTERISTICS ............................................................................................................................40

9. ORDERING INFORMATION ....................................................................................................................42

10. PACKAGE INFORMATION ....................................................................................................................43

10.1.PACKAGE SOP8 150MIL .......................................................................................................................43

10.2. PACKAGE SOP8 208MIL ......................................................................................................................
....... 44
10.3. PACKAGE DIP8 300MIL .......................................................................................................................
..................
.... 45
10.4. PACKAGE VSOP8 208MIL....................................................................................................................
.................
...........................
.......... 46
10.5. PACKAGE TSSOP8 173MIL .................................................................................................................
.........................
..........................
. 47

11. REVISION HISTORY ..............................................................................................................................48

....................
..... .......
...

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Fremont Micro Devices Preliminary FT25H16

1. FEATURES

16M -bit Serial Flash

2048K-byte
256 bytes per programmable page

Standard, Dual, Quad SPI

Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3

High Speed Clock Frequency

120MHz for fast read with 30PF load
Dual I/O Data transfer up to 240Mbits/s
Quad I/O Data transfer up to 480Mbits/s

Program/Erase Speed
Page Program time: 0.4ms typical
Sector Erase time: 120ms typical
Block Erase time: 0.2/0.4s typical
Chip Erase time: 10s typical

Flexible Architecture
Sector of 4K-byte
Block of 32/64k-byte

Low Power Consumption

ption
20mA maximum
um
m active current
curren
curr
5uA maximum
mum
um power down current

Software/Hardware
re/Hardware Write Protection
Write protect all/p
all/portion of memory via software
Enable/Disab
Enable/Disable protection with WP# Pin
Top
p or Bo
Bottom, Sector or Block selection

Advanced security Features

4*256-Byte Security Registers With OTP Lock

Single Power Supply Voltage: Full voltage range:2.7~3.6V

Minimum 100,000 Program/Erase Cycle

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Fremont Micro Devices Preliminary FT25H16
Hardware Features
8-pin SOP8 (150mil)
8-pin SOP8 (208mil)
8-pin DIP8 (300mil)
8-pin VSOP8 (200mil)
8-pin TSSOP8 (173mil)

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Fremont Micro Devices Preliminary FT25H16

2. GENERAL DESCRIPTION

The FT25H16 (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and
supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and
I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output
data is transferred with speed of 480Mbits/s.

CONNECTION DIAGRAM

8 LEAD
D SOP

PIN DESCRIPTION
Pin Name I/O Description
Descrip
CS# I Chip Select Input
C
SO (IO1) I/O Data Output (Data Input Output 1)
WP# (IO2) I/O
O Write Protect Input (Data Input Output 2)
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
HOLD# (IO3)
(IO3 I/O Hold Input (Data Input Output 3)
VCC Power Supply

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Fremont Micro Devices Preliminary FT25H16

BLOCK DIAGRAM
Write
WP#(IO2) Control
Logic

Status
Register

HOLD#(IO3) High Voltage Flash

SPI Generators Memory
Command
SCLK &
Page Address
Control
Latch/Counter
CS# Logic

SI(IO0) ode And

Column Decode d
Buff
f er
256-Byte Page Buffer
SO(IO1)
Byte Address
Latch/Counter

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Fremont Micro Devices Preliminary FT25H16

3. MEMORY ORGANIZATION

FT25H16
Each Device has Each block has Each sector has Each page has
2M 64/32K 4K 256 bytes
8K 256/128 16 - pages
512 16/8 - - sectors
32/64 - - - blocks
b

UNIFORM BLOCK SECTOR ARCHITECTURE

FT25H16 64K Bytes Block Sector Architecture
Block Sector Address
ddress range
ran
rang
511 F000H
H
1FF000H 1FFFFFH
31
496 1F
1F0000H
F0000H
0H 1F0FFFH
495 1EF000H 1EFFFFH
30
480 1E0000H
1 1E0FFFH

47 02F000H 02FFFFH
2
32 020000H 020FFFH
31 01F000H 01FFFFH
1
16 010000H 010FFFH
15 00F000H 00FFFFH
0
0 000000H 000FFFH

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Fremont Micro Devices Preliminary FT25H16

4. DEVICE OPERATION

SPI Mode

Standard SPI
The FT25H16 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input
data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

times the rate of the standard SPI. When using the Dual SPI command
nd the SI and S
SO pins become
bidirectional I/O pins: IO0 and IO1.

Quad SPI

transferred to or from the device at four times the rate

e of the standard
standa SPI. When using the Quad SPI
command the SI and SO pins become bidirectionall I/O pins: IO0 and IO1,
I and WP# and HOLD# pins become
IO2 and IO3. Quad SPI commands require the non-volatile
volatile Quad Enable
E bit (QE) in Status Register to be set.

Hold

operation of write status register, programming,

rogramming,
gramming, o
or e
erasing in progress.
The operation of HOLD, need
nee CS#
S# keep lo
low, and starts on falling edge of the HOLD# signal, with SCLK
low
signal being low (if SCLK is not being
bein low,
be w HOLD
H operation will not start until SCLK being low). The HOLD
condition ends on rising
ng HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
g edge of HOL
H
operation will not end
d until SCLK being
nd bein low).

during HOLD
D operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and
an then CS# must be at low.

Figure1. Hold Condition

CS#

SCLK

HOLD#
HOLD HOLD

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Fremont Micro Devices Preliminary FT25H16

5. DATA PROTECTION

The FT25H16 provide the following data protection methods:

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The
WEL bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits
ts
s define the sectio
section of the
memory array that can be read but not change.
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and
nd SRP bit.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands
ands are ignored except
e the Release
from Deep Power-Down Mode command.

Table1.0 FT25H16 Protected area size (CMP=1)

Status Register Content Memory Content
C
BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion
X X 0 0 0 0 to 31 000000H-1FFFFFH
000000H--1FFF
000000H 2M ALL
0 0 0 0 1 0 to 30 000000H-1EFFFFH
000000H--1
000000H 1984KB Lower 31/32
0 0 0 1 0 0 to 29
9 000000H-1DFFFFH
00000
000000 1920KB Lower 15/16
0 0 0 1 1 0 to 27 000000H-1BFFFFH
00
000 1792KB Lower 7/8
0 0 1 0 0 0 to 23
3 000000H-17FFFFH 1536KB Lower 3/4
0 0 1 0 1 0 to 15 000000H-0FFFFFH 1M Lower 1/2
0 1 0 0 1 1 tto 31 010000H-1FFFFFH 1984KB Upper 31/32
0 1 0 1 0 2 to 31 000000H-01FFFFH 1920KB Upper 15/16
0 1 0 1 1 4 to 31 000000H-03FFFFH 1792KB Upper 7/8
0 1 1 0 0 8 to 31 000000H-07FFFFH 1536KB Upper 3/4
0 1 1 0 1 16 to 31 000000H-0FFFFFH 1M Upper 1/2
X X 1 1 X NONE 000000H-1FFFFFH NONE NONE
1 0 0 0 1 31 1FF000H-1FFFFFH 4KB Top Block
1 0 0 1 0 31 1FE000H-1FFFFFH 8KB Top Block
1 0 0 1 1 31 1FC000H-1FFFFFH 16KB Top Block
1 0 1 0 X 31 1F8000H-1FFFFFH 32KB Top Block
1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block
1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block
1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block
1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block

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Fremont Micro Devices Preliminary FT25H16
Table1.1 FT25H16 Protected area size (CMP=1)
Status Register Content Memory Content
BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion
X X 0 0 0 0 to 31 000000H-1FFFFFH 2M ALL
0 0 0 0 1 0 to 30 000000H-1EFFFFH 1984KB Lower 31/32
0 0 0 1 0 0 to 29 000000H-1DFFFFH 1920KB Lower 15/16
0 0 0 1 1 0 to 27 000000H-1BFFFFH 1792KB Lower 7/8
0 0 1 0 0 0 to 23 000000H-17FFFFH 1536KB Lower 3/4
0 0 1 0 1 0 to15 000000H-0FFFFFH 1M Lower 1/2
0 1 0 0 1 1 to 31 010000H-1FFFFFH 1984KB
B Upper
Uppe 31/32
0 1 0 1 0 2 to 31 020000H-1FFFFFH 1920KB
20KB
0K Upper 15/16
0 1 0 1 1 4 to 31 040000H-1FFFFFH 1792KB
792KB Upper
U 7/8
0 1 1 0 0 8 to 31 080000H-1FFFFFH 1536KB Upper 3/4
0 1 1 0 1 16 to 31 100000H-1FFFFFH
FH 1M Upper 1/2
X X 1 1 X NONE NONE NONE
NO
NON NONE
1 0 0 0 1 0 to 31 000000H-1FEFFFH
1FEFFFH
FEFFFH 2044KB
20 Lower 511/512
1 0 0 1 0 0 to 31 000000H-1FDFFFH
00 -1FDFFFH
00H FDFFFH 2040KB Lower 255/256
1 0 0 1 1 0 to 31 000000H-1FBFFFH
00000H
0000H--1FBFFFH 2032KB Lower 127/128
1 0 1 0 X 0 to 31 000000H-1F7FFFH
000000H
000H-1F7FF
F7F 2016KB Lower 63/64
1 1 0 0 1 0 to 31 001000H-1FFFFFH
001000H-1F
001000H 1F 2044KB Upper 511/512
1 1 0 1 0 0 to 31 002000H-1FFFFFH
0020
002000 2040KB Upper 255/256
1 1 0 1 1 0 to 31 004000H-1FFFFFH
00
004 2032KB Upper 127/128
1 1 1 0 X 0 to 31 008000H-1FFFFFH 2016KB Upper 63/64

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Fremont Micro Devices Preliminary FT25H16

6. STATUS REGISTER

S15 S14 S13 S12 S11 S10 S9 S8

SUS CMP Reserved Reserved Reserved LB QE Reserved

S7 S6 S5 S4 S3 S2 S1 S0
SRP BP4 BP3 BP2 BP1 BP0 WEL WIP

The status and control bits of the Status Register are as follows:

WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy program/erase/write status
usy in program/eras
program/era
register progress. When WIP bit sets to 1, means the device is busy in program/erase/write
n program/erase/wr
gram/erase/w status register
progress, when WIP bit sets 0, means the device is not in program/erase/write
te status register
rase/write re progress.

WEL bit.
The Write Enable Latch (WEL) bit indicates the statuss of the internal Wr
Write Enable Latch. When set to 1
the internal Write Enable Latch is set, when set to 0 the
e internal Write Enable
E Latch is reset and no Write
Status Register, Program or Erase command is accepted.
cepted.

BP4, BP3, BP2, BP1, BP0 bits.

The Block Protect (BP4, BP3, BP2,, BP1, BP0) bits are
ar non-volatile. They define the size of the area to
a
be software protected against Program commands. These bits are written with the Write Status
am and Erase com
Register (WRSR) command. When
en the Block Protect
P
Prot (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined
fine in Table1).be
Table1).becomes protected against Page Program (PP), Sector Erase
(SE) and Block Erase (BE)
E) commands.
comma The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written
provided that the Hardware
are Protected mode
ware m has not been set. The Chip Erase (CE) command is executed, if
the Block Protect (BP2,
P2, BP1, BP0) bits
BP2, bi and CMP are all 0 or all 1.

SRP bit.
The Status Register P
Protect (SRP) bit is non-volatile Read/Write bits in the status register. The SRP bit
controls the method of w
write protection: software protection, hardware protection, power supply lock-down or
one time programmable
ogram
ogramma protection.

SRP WP# Status Register Description

The Status Register can be written to after a Write
0 X Software Protected
Enable command, WEL=1.(Default)
WP#=0,the Status Register locked and can not be
1 0 Hardware Protected
written to.
WP#=1,the Status Register is unlocked and can be
1 1 Hardware Unprotected
written to after a Write Enable command, WEL=1.

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Fremont Micro Devices Preliminary FT25H16
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is
set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or
Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground)

LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write
protect control
and status to the Security Registers. The default state of LB is 0, the security registerss are unlocked. LB
ca
to 1, the Security Registers will become read-only permanently.

CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14).
). It is used in conjunction the
BP4-BP0 bits to provide more flexibility for the array protection. Please
ease see the Status
Statu
Sta registers Memory
Protection table for details. The default setting is CMP=0.

SUS bit.
The SUS bit is a read only bit in the status register (S15
5 ) that is set to 1 after executing an Erase/Program
Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Progra
Erase/Program Resume (7AH) command as well as
a power-down, power-up cycle.

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 Fremont Micro Devices Preliminary FT25H16

7. COMMANDS DESCRIPTION

All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must
be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the
command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven
high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read,
Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in
fted- command
shifted-
sequence is followed by a data-out sequence. CS# can be driven high after any bit off the data-out sequence
s
is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase,
e, Write Status Register,
Re
Reg Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven
n high exactly at a byte boundary,
otherwise the command is rejected, and is not executed. That is CS# must driven high when
w the number of
clock pulses after CS# being driven low is an exact multiple of eight.
ht. For
or Page Program,
Progr if at any time the
input byte is not a full byte, nothing will happen and WEL will not be reset.
reset
Table2. Commands
nds

Command Name Byte1 Byte2 Byte3 Byte4 Byte5

Byte Byte6 n-Bytes
Write Enable 06H

Write Disable 04H

Read Status Register 05H (S7-S0) (continuous)

Read Status Register-1 35H (S15-S8) (continuous)

Write Status Register 01H (S7-S0)

S0)
0) (S15-S8)
(S15
5-S8) (continuous)

Read Data 03H A23-A16

A16 A15-A8
A15
5-A8 A7-A0 (D7-D0) (Next byte) (continuous)

Fast Read 0BH A23-A16

A A15-A8
A15 A7-A0 dummy (D7-D0) (continuous)
(1)
Dual Output Fast Read 3BH A23-A16
A23--A
A23 A15-A8 A7-A0 dummy (D7-D0) (continuous)

A7-A0
Dual I/O Fast Read BBH A (2)
A23-A8
A23
3-A8 (D7-D0)(1) (continuous)
M7-M0(2)

Quad Output Fast Read 6BH

BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(3) (continuous)

A23-A0
Quad I/O Fast
st Re
Read EBH
E Dummy(5) (D7-D0)(3) (continuous)
M7-M0(4)
Quad I/O Word Fast
Fas A23-A0
E7H Dummy(6) (D7-D0)(3) (continuous)
Read M7-M0(4)

Continuous Read Reset FFH

Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte)

(3)
Quad Page Program 32H A23-A16 A15-A8 A7-A0 (D7-D0)

Sector Erase 20H A23-A16 A15-A8 A7-A0

Block Erase(32KB) 52H A23-A16 A15-A8 A7-A0

Block Erase(64KB) D8H A23-A16 A15-A8 A7-A0

Chip Erase C7/60H

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 Fremont Micro Devices Preliminary FT25H16
Program/Erase
75H
Suspend
Program/Erase
7AH
Resume
Deep Power-Down B9H

Release From Deep

Power-Down, And ABH dummy dummy dummy (DID7-DID0) (continuous)

Read Device ID
Release From Deep
ABH
Power-Down

Manufacturer/Device ID 90H dummy dummy 00H (MID7-MID0) (DID7-DID0)

D7-DID0) (continuous)

High Speed Mode A3H dummy dummy dummy

(MID7-MID (JDID15-J (JDID7-JDI

Read Identification 9FH (continuous)
0) DID8) D0)
Erase Security
44H A23-A16 A15-A8 A7-A0
Register(8)
Program Security
42H A23-A16 A15-A8 A7-A0 (D7-D0)
(D7
D7-D0)
D0) (Next byte)
Register(8)
Read Security
48H A23-A16 A15-A8 A7-A0
A7--A0
A7 dummy
dumm
umm (D7-D0)
Register(8)

NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16,
6, A14, A12 A10, A8,A6, A4, A2, A0, M6, M4, M2, M0
A12, A
IO1 = A23, A21, A19
A19, A17, A13, A11, A9,A7, A5, A3, A1, M7, M5, M3, M1
7, A15, A13
3. Quad Output Data

IO3 = (D7, D3
D3,
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A
A21, A17, A13, A9, A5, A1, M5, M1
IO2
2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Quad I/O Fast Read Data

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Fremont Micro Devices Preliminary FT25H16
6. Quad I/O Word Fast Read Data
IO0 = (x,

7. Quad I/O Word Fast Read Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address;
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.

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Fremont Micro Devices Preliminary FT25H16

Table of ID Definitions:
FT25H16
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH 0E 40 15
90H 0E 14
ABH 14

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Fremont Micro Devices Preliminary FT25H16

7.1. Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence:
CS# goes low Sending the Write Enable command CS# goes high.
Figure2. Write Enable Sequence Diagram

CS#
0 1 2 3 4 5 6 7
SCLK

Command
SI 06H

High-Z
SO

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable
nable Latch (WEL)
(W bit. The Write Disable
command sequence: CS# goes low Sending the Write Disable
sable command CS# goes high. The WEL bit is
C
reset by following condition: Power-up and upon completion
letion of the Write Status Register, Page Program,
pletion
Sector Erase, Block Erase and Chip Erase commands.
ds.
Figure3. Write Disable
ble Sequence Diagram

CS#
0 1 2 3 4 5 6 7
SCLK

Command
SI 04H

High-Z
SO

7.3. Read Status Register

Regis (RDSR) (05H or 35H)
The Read Status Register
Reg (RDSR) command is for reading the Status Register. The Status Register
may be read at any time,
time even while a Program, Erase or Write Status Register cycle is in progress. When
tim
one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
se cy
a new command
nd tto the device. It is also possible to read the Status Register continuously. For command code

Register bits S15~S8.

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Fremont Micro Devices Preliminary FT25H16
Figure4. Read Status Register Sequence Diagram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI 05H or 35H

S7~S0 or S15~S8 out S7~S0 or S15~S8 out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

7.4. Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written
n to the Status R
Register.
ave
ve been executed.
Before it can be accepted, a Write Enable (WREN) command must previously have executed After the
Write Enable (WREN) command has been decoded and executed, the device
ice sets the Write Enable Latch
(WEL).
The Write Status Register (WRSR) command has no effect on S15, S1 of the Status Register.
1 and S0 o
CS# must be driven high after the eighth or sixteen bit of the data e has been latched
a byte la
latc in. If not, the Write
Status Register (WRSR) command is not executed. If CS# is driven
ven high after eighth
eig
e bit of the data byte, the
CMP and QE bit will be cleared to 0. As soon as CS# is driven
en high, the self-timed
ven self-tim Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status
uss Register cycle is
i in progress, the Status Register
may still be read to check the value of the Write In Progress bit.
bi The Write In Progress (WIP) bit is 1
ress (WIP) bit
during the self-timed Write Status Register cycle,, and is 0 when it is completed. When the cycle is completed,
the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command
mand allows the
th user to change the values of the Block Protect
(BP4, BP3, BP2, BP1, BP0) bits, to define
efine the size of the
th area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR)
WRSR) command also allows the user to set or reset the Status Register
Protect (SRP) bit in accordance with
h the Write Protect
P (WP#) signal. The Status Register Protect (SRP) bit
and Write Protect (WP#) signal allow the
gnal all
allo e device
devic to be put in the Hardware Protected Mode. The Write Status
Register (WRSR) command executed once the Hardware Protected Mode is entered.
and is not ex
exec
Figure5. Write
W Status Register Sequence Diagram

CS#
C

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
CLK

Command Status Register in

SI 01H 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
MSB MSB
High-Z
SO

7.5. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency f R, during the falling edge of SCLK. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ)

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Fremont Micro Devices Preliminary FT25H16
command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure6. Read Data Bytes Sequence Diagram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCLK

Command 24-bit address(A23:A0)

SI 03H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB Data Out1 Data Out2

High-Z
SO MSB
7 6 5 4 3 2 1 0

7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)

H))
The Read Data Bytes at Higher Speed (Fast Read) command is forr quickly
ckly reading data
d out. It is
followed by a 3-byte address (A23-A0) and a dummy byte, each bit being
g latched-in
hed-in during the
t rising edge of
SCLK. Then the memory content, at that address, is shifted out on SO, ch bit being shifted
O, each s out, at a Max
frequency fC, during the falling edge of SCLK. The first byte addressed
ssed can be at any
an location. The address is
automatically incremented to the next higher address after each
h byte of data is sh
shifted
s out.
Figure7. Read Data Bytes at Higherr Speed Sequence Diagram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI 0BH 23
3 22
2 21 20 19 7 6 5 4 3 2 1 0
MSB

High-Z
SO
CS#

3 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
32 33 34
SCLK

Dummy Byte
Dum
SI 7 6 5 4 3 2 1 0

Data Out1 Data Out2 Data Out3

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

7.7. Duall Output

Out
Ou Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock
cycle from SI and SO. The command sequence is shown in followed Figure8. The first byte addressed can be
at any location. The address is automatically incremented to the next higher address after each byte of data is
shifted out.

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Fremont Micro Devices Preliminary FT25H16
Figure8. Dual Output Fast Read Sequence Diagram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI 3BH 23 22 21 20 19 7 6 5 4 3 2 1 0
MSB

High-Z
SO
CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Dummy Byte
SI 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

Data Out1 Data Out2 Data Out3 Data Out4

SO 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB MSB MSB MSB

7.8. Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0)
(A2 and a dummy byte, each
bit being latched in during the rising edge of SCLK, then
n the memory contents
cont are shifted out 4-bit per clock
cycle from IO3, IO2, IO1 and IO0. The command sequence shown in followed Figure9. The first byte
uence is show
addressed can be at any location. The address is
s automatically
omatically incremented
inc to the next higher address after
each byte of data is shifted out.
Figure9. Quad
d Output Re Sequence Diagram
put Fast Read

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI(IO0)) 6BH 23 22 21 20 19 7 6 5 4 3 2 1 0
MSB

High-Z
O1)
SO(IO1)
High-Z
WP#(IO2)
WP# O2
High-Z
HOLD#(IO3)
HO D#(IO3

CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Dummy Byte

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8

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Fremont Micro Devices Preliminary FT25H16

7.9. Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the
capability to input the 3-byte address (A23- -bit per clock by SI and
SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit
per clock cycle from SI and SO. The command sequence is shown in followed Figure10. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out. To ensure optimum performance the High Speed mode (HSM) command
(A3H) must be executed once, prior to the Dual I/O Fast Read command.

The Dual I/O Fast Read command can further reduce command overhead through
gh setting
s the
- 0) after the input 3-byte address (A23-
bits (M5- 4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised
ised
sed and then lowe
lowered) does
not require the BBH command code. The command sequence is shown
wn in
n followed Figure11.
Fig If the
5- 4) do not equal (1, 0), the next command
and requires
equires the first
firs BBH command
ad Mode Resett command can
c be used to reset
(M5- 4) before issuing normal command.
Figure10. Dual I/O Fast Read Sequence
e Diagram (M5-4 (1, 0))

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12
2 13 14
4 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

A23-16 A15-8 A7-0 M7-0

CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
23 2
SCLK

SI(IO0)
O0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO O1)
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4 Byte5 Byte6

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Fremont Micro Devices Preliminary FT25H16
Figure11. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

A23-16 A15-8 A7-0 M7-0

CS#

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4

7.10. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the
e Dual I/O Fast Rea
Read command but with the capability
to input the 3-byte address (A23- -dummy clock 4-bit per clock by
IO0, IO1, IO3, IO4, each bit being latched in during
ring the
he rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO0, IO1, IO2, The command sequence is shown in followed
O2, IO3. T
Figure12. The first byte addressed can be
e at any location.
location The
T address is automatically incremented to the
next higher address after each byte off data is shifted out.
o The Quad Enable bit (QE) of Status Register (S9)
out
must be set to enable for the Quad I/O
O Fast read command.
com To ensure optimum performance the High Speed
mode (HSM) command (A3H) must be
e executed once,
o prior to the Quad I/O Fast Read command.

The Quad I/O Fast

ast Read com
command
co can further reduce command overhead through setting the
-0) a
after the input 3-byte address (A23-
bits (M5- 4) =(1, 0), then
en the next Quad
Q I/O Fast Read command (after CS# is raised and then lowered) does
he
e EBH comma
not require the comman
command code. The command sequence is shown in followed Figure13. If the
((M5- 4) do not equal (1, 0), the next command requires the first EBH command
(M
cod
(M5- 4) before
fore issuing
i normal command.

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Fremont Micro Devices Preliminary FT25H16
Figure12. Quad I/O Fast Read Sequence Diagram (M5-4 (1, 0))

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) EBH 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2
2

Figure13. Quad I/O Fast Read Sequence Diagram (M5-4=

5-4= (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7
A7-0 M7-0 Dummy Byte1 Byte2

7.11. Quad I/O Word

d Fa
Fast Read ((E
(E7H)
The Quad I/O Word
d Fast Read co
command is similar to the Quad I/O Fast Read command except that the
A0) must equal 0 and
lowest address bit (A0) a only 2-dummy clock. The command sequence is shown in followed
Figure14. The first te addressed can be at any location. The address is automatically incremented to the
st byte
ddress
dress after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9)
next higher address
must be set
et to enable for the
th Quad I/O Word Fast read command. To ensure optimum performance the High
Speed mode (HSM) command
co (A3H) must be executed once, prior to the Quad I/O Word Fast Read
command.
Quad I/O Wor
The Quad I/O Word Fast Read command can further reduce command overhead through setting the
-0) after the input 3-byte address (A23-
bits (M5- 4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered)
does not require the E7H command code. The command sequence is shown in followed Figure15. If the
(M5- 4) do not equal (1, 0), the next command requires the first E7H command

(M7-0) before issuing normal command.

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Fremont Micro Devices Preliminary FT25H16
Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-4 (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) E7H 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Figure15. Quad I/O Word Fast Read Sequence Diagram (M5-4=

(M5-4
-4== (1,, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A7-0 M7-0 Dummy Byte1 Byte1 Byte2
A23-16 A15-8 A7

7. 12. Page Program

m (P
(PP) (02H)
The Page Program
m (PP) command
comman is for programming the memory. A Write Enable (WREN) command
comm
ve
e been executed
must previously have execute to set the Write Enable Latch (WEL) bit before sending the Page
Program command.
nd.
e Program (PP) command
The Page co
c is entered by driving CS# Low, followed by the command code, three
address bytes
ytes and at least o
one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted
mitted data that goes
g beyond the end of the current page are programmed from the start address of
the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low
for the entire dura
duration of the sequence. The Page Program command sequence: CS# goes low
dur sending
Page Program command 3-byte address on SI at least 1 byte data on SI CS# goes high. The command
sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If
less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of
the last data byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated.
While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0

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Fremont Micro Devices Preliminary FT25H16
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) is not executed.
Figure16. Page Program Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address(A23:A0) Data Byte1

SI 02H 23 22 21 20 19 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK

Data Byte2 Data Byte3 Data Byte4 Data

D ta Byte256
By 256
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB MSB

7. 13.Quad Page Program (QPP) (32H)

The Quad Page Program command is for programming
mming
ming the memory using four pins: IO0, IO1, IO2, and
IO3. To use Quad Page Program the Quad enable in
n status Bit9 must be set (QE=1). A Write Enable
us register Bit
B
(WREN) command must previously have been executed
cuted to set tthe Write Enable Latch (WEL) bit before
sending the Page Program command. The Quad Page Progr
Program
Progra command is entered by driving CS# Low,
followed by the command code (32H), three
ee address
ddress bytes and
a at least one data byte on IO pins.
The command sequence is shown more than 256 bytes are sent to the device, previously
wn in Figure17. If m
mo
latched data are discarded and the last
ast 256 data bytes
byte are guaranteed to be programmed correctly within the
same page. If less than 256 data bytes
es are sent to device, they are correctly programmed at the requested
ytes
addresses without having any effects on the other
ny effe
effec o
ot bytes of the same page. CS# must be driven high after the
eighth bit of the last data been latched in; otherwise the Quad Page Program command is not
ata byte has b
executed.
As soon as CS#
# is driven high,
hig the self-timed Quad Page Program cycle (whose duration is t PP) is
initiated. While
e the Quad Page Program cycle is in progress, the Status Register may be read to check the
value of the
he Write In Progress
Progres (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page
Progre
Program
m cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable
ble Latch
La (WEL)
(W bit is reset.
A Quad Pag
Page Program command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) is not executed.

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Fremont Micro Devices Preliminary FT25H16

Figure17.Quad Page Program Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address(A23:A0)

SI 32H 23 22 21 20 19 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0
MSB

SO(IO1) 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3
Byte1 Byte2 Byte3
Byte Byte4
yte4

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
SO(IO1)

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
Byte5 Byte6 Byte7 Byte8
8 Byte9 Byte10
B 0 Byte11
Byt Byte12
yte12 Byte13 Byte14 Byte15 Byte16 Byte253 Byte254Byte255Byte256

7.14. Sector Erase (SE)

SE (20H)
20H)
The Sector Erase (SE)
E) command
comma
comman is for
or erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously
ously have bee executed to set the Write Enable Latch (WEL) bit. The Sector Erase
been e
(SE) command is entered
tered by driving C
CS# low, followed by the command code, and 3-address byte on SI. Any
address inside the sector is a vali
valid address for the Sector Erase (SE) command. CS# must be driven low for
the entire duration
uration of the sequ
sequence.
The
e Sector Erase command
c sequence: CS# goes low sending Sector Erase command 3-byte
address on SI CS# goes
go high. The command sequence is shown in Figure18. CS# must be driven high after
the eighth bitt of tthe last address byte has been latched in; otherwise the Sector Erase (SE) command is not
executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is t SE) is initiated.
While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4,
BP3, BP2, BP1, BP0) bit (see Table1.0&1.1) is not executed.

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Fremont Micro Devices Preliminary FT25H16
Figure18. Sector Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI 20H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB

7.15. 32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write
W Enable
(WREN) command must previously have been executed to set the Write Enable Latch
atch (WEL)
WEL) bit. The
Th 32KB
and code, and three
Block Erase (BE) command is entered by driving CS# low, followed by the command thre address
bytes on SI. Any address inside the block is a valid address for the 32KB Block
ock Erase (BE) co
command. CS#
must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending
ending 32KB Block
Bloc Erase command
3-byte address on SI CS# goes high. The command sequence is shown
own in Figure19.
Figure
Figu CS# must be driven
high after the eighth bit of the last address byte has been latched
ed in; otherwise the
ched t 32KB Block Erase (BE)
command is not executed. As soon as CS# is driven high, the
he self-timed Block Erase cycle (whose duration is
tBE) is initiated. While the Block Erase cycle is in progress,
s, the Status Regis
Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
ress (WIP) during the self-timed Block Erase cycle,
WIP) bit is 1 d
and is 0 when it is completed. At some unspecified
ed time
me before the cycle
c is completed, the Write Enable Latch
(WEL) bit is reset. A 32KB Block Erase (BE)
E) command
mand applied
appli to a block which is protected by the Block
applie
Protect (BP4, BP3, BP2, BP1, BP0) bits (see
see Table1.0&1.1)
Table1.0&1.1 is not executed.
Figure19. Erase Sequence Diagram
9. 32KB Block Er
Eras

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI 52H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB

7.16. 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable
(WREN) command
man must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB
Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address
bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS#
must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command
3-byte address on SI CS# goes high. The command sequence is shown in Figure20. CS# must be driven
high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE)
command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is
tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle,

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Fremont Micro Devices Preliminary FT25H16
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block
Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.0&1.1) is not executed.
Figure20. 64KB Block Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI D8H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB

7.17. Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is for erasing the all data of the chip. A Write
e Enable (WREN)
(WRE command
must previously have been executed to set the Write Enable Latch (WEL) bit .The
The Chip Erase
Eras (CE) command
is entered by driving CS# Low, followed by the command code on Serial
rial Data
ta Input (SI).
(SI CS# must be driven
Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending
nding
ing Chip Erase command
c CS# goes high.
The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command
code has been latched in, otherwise the Chip Erase command
mmand executed.
mand is not execu
execut As soon as CS# is driven high,
the self-timed Chip Erase cycle (whose duration is t CE) is initiated. Wh
Whi
While the Chip Erase cycle is in progress,
the Status Register may be read to check the value
lue off the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Chip Erase
e cycle,
e, and is 0 when
wh
w it is completed. At some unspecified time
before the cycle is completed, the Write Enable
le Latch (WEL)
(WE bit is reset. The Chip Erase (CE) command is
(WEL
executed if the Block Protect (BP2, BP1,
P1, BP0) bits and CMP
C are all 0 or all 1. The Chip Erase (CE) command
is ignored if one or more sectors are
re protected.
Figure21.
ure21. Erase Sequence Diagram
re21. Chip E

CS#
0 1 2 3 4 5 6 7
SC
SCLK

Command
SI 60H or C7H

7.18. Deep Pow

Power-Down (DP) (B9H)
Executing
g the
th Deep Power-Down (DP) command is the only way to put the device in the lowest
consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program
and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if
there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep
Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device
has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release
from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be
output on SO.

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Fremont Micro Devices Preliminary FT25H16
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command
CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of
the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As
soon as CS# is driven high, it requires a delay of t DP before the supply current is reduced to I CC2 and the Deep
Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure22. Deep Power-Down Sequence Diagram

CS#
tDP
0 1 2 3 4 5 6 7
SCLK

Command Stand-by mode Deep Power-down mode

SI B9H

7.19. Release from Deep Power-Down And

nd Read Device
Devi
Devic ID (RDI) (ABH)
The Release from Power-Down and Read/Device ID
D command is a multi-purpose command. It can be
used to release the device from the Power-Down state or obtain the
th devices electronic identification (ID)
number.
To release the device from the Power-Down
Down state, the com
ccommand is issued by driving the CS# pin low,
-Down will
take the time duration of t RES1 (See AC
C Characteristics)
Characteristics before the device will resume normal operation and
other command are accepted. The CS# remain high during the tRES1 time duration.
S# pin must rem
When used only to obtain the Device
evice ID while
whil not in the Power-Down state, the command is initiated by
wh
d by 3-dummy byte. The Device ID bits
are then shifted out on the edge of SCLK with most significant bit (MSB) first as shown in Figure23. The
he falling edg
Device ID value for the listed in Manufacturer and Device Identification table. The Device ID can
he FT25H16 is lilist
be read continuously.
usly. The command
comman is completed by driving CS# high.
When used
ed to release the device from the Power-Down state and obtain the Device ID, the command is
sed
the same as previously described,
desc
des and shown in Figure23, except that after CS# is driven high it must remain
high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume
normal operation
eration and other command will be accepted. If the Release from Power-Down/Device ID command
eratio
is issued while
e an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored
and will not have any effects on the current cycle.

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Fremont Micro Devices Preliminary FT25H16
Figure23. Release Power-Down Sequence Diagram

CS#
tRES1
0 1 2 3 4 5 6 7
SCLK

Command
SI ABH

Deep Power-down mode Stand-by mode

Figure24. Release Power-Down/Read Device ID Sequence Diagram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCLK

Command 3 Dummy Bytes tRES2

SI ABH 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB Device ID
High-Z
SO MSB
7 6 5 4 3 2 1 0

Deep power-down
po r Mode Stand-by Mode

7.20. Read Manufacture ID/ Device ID (REMS) (90H

(90H)
The Read Manufacturer/Device ID command is an alternative
lternative to the
th
t Release from Power-Down / Device
ID command that provides both the JEDEC assigned
gned Manufacturer ID and the specific Device ID.

24-bit address (A23-A0) of 000000H. After

er which,
ich, the Manu
Manufacturer
Man ID and the Device ID are shifted out on
the falling edge of SCLK with most significant
gnificant bit (MSB)
ignificant (MSB first as shown in Figure25. If the 24-bit address is
initially set to 000001H, the Device ID
D will be read firs
first.
Figure25. Read
d Manufacture
Manufactu ID/ Device ID Sequence Diagram
Manufact
CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCL
SCLK

Command 24-bit address(A23:A0)

SI 90H 23 22 21 20 19 7 6 5 4 3 2 1 0
MSB

High-Z
SO
CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

SI

Manufacturer ID Device ID Manufacturer ID

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

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7.21. Read Identification (RDID) (9FH)

The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed
by two bytes of device identification. The device identification indicates the memory type in the first byte, and
the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an
Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The
Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is
shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial
Data Output, each bit being shifted out during the falling edge of Serial Clock. The command
man sequence is
shown in Figure26. The Read Identification (RDID) command is terminated by driving CS#
S# to high at any time
during data output. When CS# is driven high, the device is put in the Standby Mode.
de. Once in the Standby
S
Mode, the device waits to be selected, so that it can receive, decode and execute
e commands.
Figure26. Read Identification ID Sequence Diagram
gram
m

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 49 50 51 52 53 54 55
SCLK

Command
SI 9FH
Memory Type
Me
Manufacturer
ufactur ID JJDID15-JDID8
High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
B
CS#

16 17 34 35 36 37 38 39 40
0 41
4 42 43 44 45
5 46
4 47 48 49 50 51 52 53 54 55
SCLK

SI
Capacity Memory Type
Manufacturer ID JDID15-JDID8
JDID7-JDID0
JDID
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

7.22. High Speed Mode (HSM) (A3H)

The High Speed Mode (HSM) command must be executed prior to Dual or Quad I/O commands when
operating frequencies (see f R and fC1 in AC Electrical Characteristics). This command allows
ng at high frequ
pre-charging
ng of internal
intern charge pumps so the voltages required for accessing the flash memory array are
ble. The command sequence: CS# goes low
readily available. Sending A3H command Sending 3-dummy
byte CS# goes high. See Figure27. After the HSM command is executed, the device will maintain a slightly
higher standby current (ICC8) than standard SPI operation. The Release from Power-Down or HSM
command (ABH) can be used to return to standard SPI standby current (ICC1). In addition, Write Enable
command (06H) and Power-Down command (B9H) will also release the device from HSM mode back to
standard SPI standby state.

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Fremont Micro Devices Preliminary FT25H16
Figure27. High Speed mode Sequence Diagram
CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 3 Dummy Bytes tHSM

SI A3H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB
High Speed Mode
SO

7.23. Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read -0)) are implemented
imple
mple to
further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad
uad I/O Fast
ual/Quad Fas Read
operations do not require the BBH/EBH/E7H command code.
Because the FT25H16 has no hardware r
FT25H16 will not recognize any standard SPI commands. So Continuous
us Read
ead Mode Reset
Res command will
gnized.
The command sequence is show in Figure28.
Figure28. Continuous Read Mode Reset
sett Sequence Diagram
Di
Diag
Mode Bit Reset for Quad/Dual
d/D I/O

CS#

0 1 2 3 4 5 6 7
SCLK

SI(IO0) 06H

SO(IO1)

WP#(IO2)

HOLD#(IO3)
HOLD#(

7.24. Program/Erase
m/Erase
/Erase Suspend
Sus (PES) (75H)
rogram or
sector/block
ck erase operation
operatio and then read data from any other sector or block. The Write Status Register
command Erase Security Registers (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H)
nd (01H) and Era
and Page Prog
Program ccommand are not allowed during Program/Erase suspend. Program/Erase Suspend is
SUS

Characteristics) is required to suspend the program/erase operation.

The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is
on-going. If the SUS bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device.
SUS

Program/Erase Suspend. A power-off during the suspend period will reset the device and release the
suspend state. The command sequence is show in Figure29.

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Fremont Micro Devices Preliminary FT25H16
Figure29. Program/Erase Suspend Sequence Diagram

CS#
tSUS
0 1 2 3 4 5 6 7
SCLK

Command
SI 75H

SO
Accept read command

7.25. Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program
ogram or sector/block
sector/blo erase
sector/bl
operation after a Program/Erase Suspend command. The Program/Erase command
and will be accepted
ommand acc by the
device only if the SUS bit equal to 1 and the WIP bit equal to 0. After issued
ed the
he SUS bit in the
th status register
will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to
o 1 within
hin 200ns and
a the Sector or Block
will complete the erase operation or the page will complete the
e program
ogram operation.
operatio
opera The Program/Erase
Resume command will be ignored unless a Program/Erase Suspend active. The
spend is active T command sequence is
show in Figure30.
Figure30. Program/Erase Resume
sume Sequence Diagram
esume D

CS#

0 1 2 3 4 5 6 7
SCLK

om
Command
SI 7AH

SO
Resume Erase/Program

7.26. Erase Security

curity Registers
Regis
Reg (44H)
The FT25H16
H16 provides four
fou 256-byte Security Registers which can be erased and programmed
individually. These
hese registers m
ma be used by the system manufacturers to store security and other important
may
information
on separately from the main memory array.
The
he Erase Secur
Security Registers command is similar to Sector/Block Erase command. A Write Enable
Securit
(WREN) command
ommand m
omm must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase
se Security Registers command sequence: CS# goes low sending Erase Security Registers
command CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the
eighth bit of the command code has been latched in, otherwise the Erase Security Registers command is not
executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is t SE)
is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase
Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers
will be permanently locked; the Erase Security Registers command will be ignored.

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Fremont Micro Devices Preliminary FT25H16
Address A23-A16 A15-A10 A9-A0
Security Registers 00000000 000000 Don t Care
Figure31. Erase Security Registers command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 24-bit address(A23:A0)

SI 44H 23 22 21 20 19 7 6 5 4 3 2 1 0

MSB

7.27. Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. It allows
allow from 1 to
256 bytes Security Registers data to be programmed. A Write Enable (WREN) must previously
REN) command m
have been executed to set the Write Enable Latch (WEL) bit before sending
ding the Program Security
S Registers
command. The Program Security Registers command is entered by driving
ving CS# Low,
L followed by the
command code (42H), three address bytes and at least one data byte on SI. As so
soon as CS# is driven high,
soo
the self-timed Program Security Registers cycle (whose duration
on is t PP) is in
uration initiated. While the Program
Security Registers cycle is in progress, the Status Register
er may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is self-timed Program Security Registers
s 1 during the self
cycle, and is 0 when it is completed. At some unspecified the cycle is completed, the Write Enable
ecified time before th
Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB)
B) is set to 1, the Security
S Registers will be permanently locked.
Program Security Registers command will be ignored.
gnored.
Address A23-A16
A23-- A16
A23 A15-A8 A7-A0
Security Registers 0 00H
00 00H Byte Address
Security Registers 1 00H
00 01H Byte Address
Security Registers
ers 2 00H 02H Byte Address
Security Registers
egisters 3 00H 03H Byte Address
Figure32.
ure32. Progra
Progr
Program Security Registers command Sequence Diagram

CS#
C #
0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address(A23:A0) Data Byte1

SI 42H 23 22 21 20 19 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK

Data Byte2 Data Byte3 Data Byte4 Data Byte256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB MSB

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Fremont Micro Devices Preliminary FT25H16

7.28. Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address
reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving
CS# high.
Address A23-A16 A15-A10 A9-A0
A9
Security Registers 00000000 000000 Address
Addres
dres
Figure33. Read Security Registers command Sequence Diagram
agram

CS#

0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31
SCLK

Command 23:A0)
24-bit address(A23:A0)
SI 48H 23 22 21 20 19 7 6 5 4 3 2 1 0
MSB

High-Z
SO
CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45
4 46
6 47 4
48 49
9 50
5 51 52 53 54 55
SCLK

Dummy Byte
SI 7 6 5 4 3 2 1 0

Data Out1 Data Out2 Data Out3

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

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Fremont Micro Devices Preliminary FT25H16

8. ELECTRICAL CHARACTERISTICS

8.1. Power-on Timing

Vcc(max)
Program,Erase and Write command are ignored
Chip Selection is not allowed
Vcc(min)
Reset
State tVSL Read command Device is fully
is allowed accessiblele
VWI
tPUW

Time

Table3. Power-Up Timing and Write Inhibit

hibit Threshold
Symbol Parameter Min Max Unit
tVSL VCC(min) To CS# Low 10 us
tPUW Time Delay Before Write Instruction
ction 1 10 ms
VWI Write Inhibit Voltage 1 2.5 V

8.2. Initial Delivery State

The device is delivered with the

he
e memory arra
a
array erased: all bits are set to 1(each byte contains FFH).The
Status Register contains 00H
H (all Status Register bits are 0).
s Regist

8.3. Data Retention

ention
ntion and Endurance
En
E

Parameter Test Condition Min Unit

150 10 Years
Minimum
nimum Pattern Data
D Retention Time
125 20 Years
Erase/Program
ase/
ase/P Endurance -40 to 85 100K Cycles

8.4. Latch up Characteristics

Parameter Min Max

Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V
VCC Current -100mA 100mA

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Fremont Micro Devices Preliminary FT25H16

8.5. Absolute Maximum Ratings

Parameter Value Unit

Ambient Operating Temperature -40 to 85
Storage Temperature -65 to 150
Output Short Circuit Current 200 mA
Applied Input/Output Voltage -0.5 to 4.0 V
VCC -0.5 to 4.0 V

Input timing reference level Output timing reference

eference level
0.8VCC 0.7VCC
AC Measurement level 0.5 CC
0.5VCC
0.1VCC 0.2VCC
Note:Input pulse rise and fall time are<5ns

8.6. Capacitance Measurement Condition

Symbol Parameter Min Typ Max

Ma Unit Conditions
CIN Input Capacitance 6 pF VIN=0V
COUT Output Capacitance 8 pF VOUT=0V
CL Load Capacitance 30 pF
Input Rise And Fall time 5 ns
Input Pulse Voltage 0.1VCC to 0.8VCC V
Input Timing Reference Voltage
Volt 0.2VCC to 0.7VCC V
Output Timing Referen
Refere
Reference Voltage
oltage 0.5VCC V

Figure34.. Input
Figure
Figure34 In
Inp Test Waveform and Measurement Level
Maximum Negative Waveform
tive Overshoot W

20ns 20ns
VSS

VSS-2.0V
20ns

Maximum Positive Overshoot Waveform

20ns
VCC+2.0V

VCC
20ns 20ns

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Fremont Micro Devices Preliminary FT25H16

8.7. DC Characteristics

(T=-40 ~85 ,VCC=2.7~3.6V)

Symbol Parameter Test Condition Min. Typ Max. Unit
ILI Input Leakage Current ±2
ILO Output Leakage Current ±2
CS#=VCC
ICC1 Standby Current 1 5
VIN=VCC or VSS
CS#=VCC
ICC2 Deep Power-Down Current 1 5
VIN=VCC or VSS
CLK=0.1VCC/0.9VCC at
15 20 mA
120MHz, Q=Open(*1 I/O)
ICC3 Operating Current(Read) CLK=0.1VCC/0.9VCC at
80MHz, Q=Open(*1,*2,*4 13
1 18 mA
I/O)
ICC4 Operating Current(PP) CS#=VCC 10 mA
ICC5 Operating Current(WRSR) CS#=VCC 10 mA
ICC6 Operating Current(SE) CS#=VCC 10 mA
ICC7 Operating Current(BE) CS#=VCC 10 mA
ICC8 High Speed Current 600 800
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL=1.6mA
=1.6mA 0.4 V
VOH Output High Voltage IOH=-100uA
=- VCC-0.2 V

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8.8. AC Characteristics

(T=-40 ~85 ,VCC=2.7~3.6V CL=30pf)

Symbol Parameter Min. Typ Max. Unit
Serial Clock Frequency For:Fast Read(0BH),
fC DC 120 MHz
Dual Output(3BH)
Serial Clock Frequency For:Dual I/O(BBH),
fC1 Quad I/O(EBH),Quad Output(6BH) (Dual I/O & DC 80 120 MHz
Quad I/O With High Speed mode)
Serial Clock Frequency For:Dual I/O(BBH),
fC2 Quad I/O(EBH) (Dual I/O & Quad I/O Without DC 40
0 MHz
High Speed mode)
fR Serial Clock Frequency For:Read(03H) DC 80
8 MHz
tCLH Serial Clock High Time 4 ns
tCLL Serial Clock Low Time 4 ns
tCLCH Serial Clock Rise Time(Slew Rate) 0.2
2 V/ns
tCHCL Serial Clock Fall Time(Slew Rate) 0.2 V/ns
tSLCH CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL CS# High Time (read/write) 20 ns
tSHQZ Output Disable Time 6 ns
tCLQX Output Hold Time 1 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time
me 2 ns
tHLCH Hold# Low Setup Time(relative
Time to Clock) 5 ns
tHHCH Hold# High Setup Time(relative
Time to Clock) 5 ns
tCHHL Hold# High
igh Hold Time
Time(relative to Clock) 5 ns
tCHHH Hold# Low Hold Time(relative
T to Clock) 5 ns
tHLQZ Hold# Low To High-Z Output 6 ns
tHHQX Hold# Low To Low-Z Output 6 ns
tCLQV Clock Low To Output Valid
Cl 6.5 ns
tWHSL Write Protect Setup Time Before CS# Low
Writ 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 0.1 us
CS# High To Standby Mode Without Electronic
tRES1 0.1 us
Signature Read
CS# High To Standby Mode With Electronic
tRES2 0.1 us
Signature Read
tHSM CS# High To High Speed mode 0.1 us
tSUS CS# High To Next Command After Suspend 2 us

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Fremont Micro Devices Preliminary FT25H16
tW Write Status Register Cycle Time 100 200 ms
tPP Page Programming Time 0.4 2.4 ms
tSE Sector Erase Time 120 300 ms
tBE Block Erase Time(32K Bytes/64K Bytes) 0.2/0.4 0.5/0.6 s
tCE Chip Erase Time 10 25 s

Figure35. Serial Input Timing

tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SH

SCLK
tDVCH tCLCH tCHCL
CL
tCHDX
SI MSB LSB

High-Z
SO

Figure36. Output Timing

iming
ng

CS#
tCLH tSHQZ
SCLK
tCLQV tCLQV tCLL
tCLQX tCLQX
SO LSB

SI
Least significant
fica addresss bit (LIB)
(LIB in

Figure37. Hold Timing

Figur
Figure

CS#
tCHHL tHLCH tHHCH
SCLK
LK
tCHHH
tHLQZ tHHQX
SO

OLD
HOLD#
SI do not care during HOLD operation

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Fremont Micro Devices Preliminary FT25H16

9. ORDERING INFORMATION

FT 25 H 16 X X X - X X

PACKING TYPE:
B: Tube
T: Tape & Reel

ION:
OPTION:
s
R: Rohs
G: Green
Gree
en

TEMPERATURE
T EMPERAT RANGE:
D efaullt: Industrail (-40 to +85
Default: )

PACKAGE:
S: SOP8 150mil
W: SOP8 208mil
D: DIP8 300mil
V: VSOP8 208mil
T: TSSOP8 173mil

VERSION:
Default: A Version
B: B Version

DENSITY:
16: 16M

TYPE:
H: 3V
L: 1.8V

DEVICE:
25: Serial Falsh

NOTE:
1. Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.),
please advise in advance.

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Fremont Micro Devices Preliminary FT25H16

10.PACKAGE INFORMATION

10.1.Package SOP8 150MIL

Dimensions In Millimeters
Dimension
Dimensio Dimensions In Inches
Symbol
ol
Min Max Min Max
A 1.350
1
1. 1.750 0.053 0.069
A1 0.100 0.250 0.004 0.010
A
A2 1.350 1.550 0.053 0.061
b 0.330 0.510 0.013 0.020
c 0.170 0.250 0.006 0.010
D 4.700 5.100 0.185 0.200
E 3.800 4.000 0.150 0.157
E1 5.800 6.200 0.228 0.244
e 1.270 (BSC) 0.050 (BSC)
L 0.400 1.270 0.016 0.050
0° 8° 0° 8°

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Fremont Micro Devices Preliminary FT25H16

10.2. Package SOP8 208MIL

Dimension
Dimensio
Dimensions In Millimeters Dimensions In Inches
Symbol
ol
Min Max Min Max
A -- 2.150 -- 0.085
A1 0.050 0.250 0.002 0.010
A2 1.700 1.900 0.067 0.075
b 0.350 0.500 0.014 0.020
c 0.100 0.250 0.004 0.010
D 5.130 5.330 0.202 0.210
E 7.700 8.100 0.303 0.319
E1 5.180 5.380 0.204 0.212
e 1.270 (BSC) 0.050 (BSC)
L 0.500 0.850 0.020 0.033
0° 8° 0° 8°

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Fremont Micro Devices Preliminary FT25H16

10.3. Package DIP8 300MIL

meters
rs
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 3.710 4.310
10 0.146 0.170
A1 0.510 0.020
A2 3.200 3.600
3.6 0.126 0.142
B 0.380
0.38 0.570 0.015 0.022
B1 1
1.
1.524 BSC
B 0.060 BSC
C 0.204
4 0.360 0.008 0.014
D 9.000 9.400 0.354 0.370
E 6.200
6.2 6.600 0.244 0.260
E1
1 7.320 7.920 0.288 0.312
e 2.540 (BSC) 0.100 BSC
L 3.000 3.600 0.118 0.142
E2 8.400 9.000 0.331 0.354

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Fremont Micro Devices Preliminary FT25H16

10.4. Package VSOP8 208MIL

Dimensions In Millimeters
ters Dimensions In Inches
Symbol
Min Max
ax Min Max
A -- 1.000 -- 0.039
A1 0.050
0 0.150
0.1 0.002 0.006
A2 0.75
0.750 0.850 0.030 0.033
b 0.350 0.480 0.014 0.019
c 0
0.12
0.127 (REF) 0.005 (REF)
D 5.180 5.380 0.204 0.212
E 7.700
7.70 8.100 0.303 0.319
E1
1 5.180 5.380 0.204 0.212
e -- -- -- --
L 0.500 0.800 0.020 0.031
y -- 0.100 -- 0.004
0° 8° 0° 8°

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Fremont Micro Devices Preliminary FT25H16

10.5. Package TSSOP8 173MIL

Dimens
Dimen
Dimensions IIn M
Millimeters Dimensions In Inches
Symbol
Min Max Min Max
D 2.900 3.100 0.114 0.122
E 4.300
4.30
.30 4.500 0.169 0.177
b 0.190
0 0.300 0.007 0.012
c 0.090 0.200 0.004 0.008
E
E1 6.250 6.550 0.246 0.258
A 1.200 0.047
A2 0.800 1.000 0.031 0.039
A1 0.050 0.150 0.002 0.006
e 0.65 (BSC) 0.026 (BSC)
L 0.500 0.700 0.020 0.028
H 0.25 (TYP) 0.01 (TYP)
1° 7° 1° 7°

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Fremont Micro Devices Preliminary FT25H16

11.REVISION HISTORY

Version No Description Date

Preliminary 1.0 7.14.2014
Modify AC CHARACTERISTICS: f C2 80MHz max change to 40MHz max
Modify AC CHARACTERISTICS: tW 10ms typ change to 100ms typ, tW
Preliminary 1.1 20ms max change to 200ms max 10.29.2014
Modify AC CHARACTERISTICS: tSE 80ms typ change to 120ms typ
Add Package TSSOP8 173mil

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Fremont Micro Devices Preliminary FT25H16
Fremont Micro Devices (SZ) Limited

#5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen, Guangdong 518057
Tel: (86 755) 86117811
Fax: (86 755) 86117810

Fremont Micro Devices (Hong Kong) Limited

g Kong
#16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Ko
Tel: (852) 27811186
Fax: (852) 27811144

Fremont Micro Devices (USA), Inc.

42982 Osgood Road Fremont, CA 94539

Tel: (1-510) 668-1321
Fax: (1-510) 226-9918

Web Site: http://www.fremontmicro.com/

* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated
(BVI) assumes no responsibility for the consequences of use of such information or for any infringement of
patents of other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in
this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical
components in life support devices or systems without express written approval of Fremont Micro Devices,
Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All
other names are the property of their respective own.

© 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H16-page49