Product Sample & Technical Tools & Support & Reference

Folder Buy Documents Software Community Design

UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016

UCC25710 LLC Half-Bridge Controller For Multi-String LED Lighting

1 Features 3 Description
•
1 Closed-Loop LED String Current Control The UCC25710 device is an LLC half-bridge
controller for accurate control of multi-string LED
• PWM Dimming Input backlight applications. It is optimized for multi-
• Adjustable FMIN (3% accuracy), and FMAX (7.5% transformer, multi-string LED architectures. Superior
Accuracy) LED current matching in multiple strings can be
• LLC and Series LED Switch Control for Dimming achieved with this controller and architecture.
Compared to existing LED backlight solutions, the
• Programmable Dimming LLC ON/OFF Ramp for
multi-transformer architecture provides the highest
Elimination of Audible Noise overall efficiency from AC input to LED load.
• Closed-Loop Current Control at Low Dimming
The LLC controller function includes a Voltage
Duty Cycles
Controlled Oscillator (VCO) with programmable FMIN
• Programmable Soft Start and FMAX, half-bridge gate drivers with a fixed dead
• Accurate VREF for Tight Output Regulation time of 500 ns and a GM current amplifier. The LLC
• Overvoltage, Undervoltage and Input Overcurrent power delivery is modulated by the controller’s VCO
Protection With Auto-Restart Response frequency. The VCO has an accurate and
programmable frequency range. At very low power
• Second Overcurrent Threshold With Latch-Off levels the VCO frequency goes from FMAX to zero to
Response maximize efficiency at low LED currents.
• 400-mA/-800-mA Gate Drive Current
• Low Start-Up and Operating Currents Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Lead (Pb)-Free, 20-Pin, SOIC Package
UCC25710 SOIC (20) 12.80 mm × 7.50 mm

2 Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• LED Backlight for LCD TV and Monitors
• LED General Lighting
SPACE
Simplified Application Diagram
Efficiency and Linearity Results (Dual 45-W
Strings)
LED String 1
T1 ± +
VIN
100 4

LED String 2
T2 ± + Efficiency
95 2

Linearity Error - %
Efficiency - %

LED String N
TN ± +

20 V to 9.5 V 90 0
UCC25710
1 VCC DTY 7 Linearity
ON/OFF 10 BLON DADJ 8

2 GD1 FMIN 20

3 GD2 FMAX 19 85 -2
4 GND SS 18

13 CL ICOMP 17

15 CREF CS 16

5 VREF LEDSW 6

14 DSR OV 12 80 -4
9 DIM UV 11
0 10 100
DIM PWM Output
Dimming Duty Cycle -%
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 15
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 19
3 Description ............................................................. 1 9 Application and Implementation ........................ 20
4 Revision History..................................................... 2 9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 31
7 Specifications......................................................... 6 11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
7.1 Absolute Maximum Ratings ...................................... 6
11.2 Layout Example .................................................... 32
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6 12 Device and Documentation Support ................. 33
7.4 Thermal Information .................................................. 7 12.1 Receiving Notification of Documentation Updates 33
7.5 Electrical Characteristics........................................... 7 12.2 Community Resource............................................ 33
7.6 Typical Characteristics ............................................ 10 12.3 Trademarks ........................................................... 33
12.4 Electrostatic Discharge Caution ............................ 33
8 Detailed Description ............................................ 13
12.5 Glossary ................................................................ 33
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14 13 Mechanical, Packaging, and Orderable
Information ........................................................... 33

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2011) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

2 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

5 Description (continued)
The LED current loop reference is set by a divider off the VREF 5-V output. The reference can be varied over a
0.5-V to 2.6-V range, allowing analog dimming to be combined with PWM dimming.
PWM dimming is used to control an external LED series switch and also to gate on and off the LLC power stage.
The LEDSW output along with a simple drive circuit is used to switch on and off the LED string current. This
output responds directly to the input signal at the dimming input, DIM. The LLC is also ramped on and off with
the dimming PWM input. The on and off LLC dimming edges are ramped at programmable slew rates to control
audible noise. The dimming function includes duty-cycle compensation to allow optimization of overall efficiency
and dimming linearity over a maximum range.
The control voltage to the VCO is set by ICOMP (current amplifier output) during LED ON-times. During start-up
the soft-start pin, SS, controls the VCO response until it exceeds ICOMP. During dimming the rise and fall rates
of the VCO input are controlled by the voltage at the dimming slew rate, DSR, pin while the pedestal of VCO
control level continues to be controlled by ICOMP. The current amplifier output is connected to ICOMP only
during the commanded dimming LED ON-time. The LLC on-time is extended beyond the LED current ON-time at
low dimming duty-cycles to maintain closed-loop control of the LED current.
Protection thresholds for LED string overvoltage and undervoltage conditions are set with external resistive
dividers and accurate internal thresholds. Input current to the converter is monitored with both a restart and latch-
off response depending on the overcurrent level. The controller also includes thermal shutdown protection.
The auto restart response to any fault includes a 10-ms reset period followed by a soft start. In the case of a
severe input overcurrent, restart is disabled until the input supply is cycled through its UVLO threshold.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

6 Pin Configuration and Functions

DW Package
20-Pin SOIC
Top View

VCC 1 20 FMIN

GD1 2 19 FMAX

GD2 3 18 SS

GND 4 17 ICOMP

VREF 5 16 CS

LEDSW 6 15 CREF

DTY 7 14 DSR

DADJ 8 13 CL

DIM 9 12 OV

BLON 10 11 UV

Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
Connect a DC power voltage to VCC. Bypass VCC to GND with a 0.47-µF or larger ceramic
capacitor using short PC-board traces. VCC directly supplies power to the gate drivers and
1 VCC P
VREF which biases all circuit blocks in the UCC25710. Undervoltage lockout (UVLO)
comparator prevents operation until VCC rises above VVCCON.
Gate drive outputs operate 180° out of phase with a fixed 500 ns of dead time. They typically
2, 3 GD1&2 O drive either primary end of a gate drive transformer. At start-up or during a fault recovery,
initiating the LLC converter begins with GD2 turning on first.
The ground pin is both the reference pin for the controller and the low-side return for the gate
4 GND P drive signals. Take special care to return all AC decoupling as close as possible to this pin
and avoid any common trace length with analog signal return paths.
The internal 5-V supply and reference rail is brought out to this pin. A small decoupling
5 VREF O capacitor to ground of 1 µF is required. VREF can support up to 10-mA current external to
the device. VREF is enabled when VCC is above VVCCON and BLON is above VBLON.
The LED switch output is a control signal to a series LED switch. This output is low during a
low level at the DIM input and whenever the LLC converter is disabled. PWM dimming is
6 LEDSW O
disabled during soft start, and the LEDSW output is high independent of the DIM input. A
simple gate drive circuit is generally required at this output to drive the external FET.
The duty-cycle pin is averaged with a capacitor to ground to form a 1-D proportional voltage
7 DTY I/O that is compared to the DADJ saw tooth voltage. The average voltage at this pin is 2.5 V(1-
D)+0.1 V, where D is the dimming PWM duty-cycle the DIM input.
A capacitor to ground at the duty-cycle adjust input sets the positive slope of a saw tooth
waveform that is compared to a voltage proportional to 1-D where D is the dimming PWM
8 DADJ I/O
duty-cycle of the DIM input. At the falling edge of the DIM input this comparison is used to
extend the LLC ON-time beyond the ON-time of the LED series switch.
A PWM input signal at the dimming pin controls the average load current by cycling on and
off both an external series LED switch and the gate drives to the LLC converter. A high on
9 DIM I
this pin corresponds to an ON condition. The controller ignores a low condition at this input
during start-up or fault recovery until after the completion of a soft-start sequence.
Backlight ON is an enable signal for the control device. The signal is active high with a
10 BLON I threshold of approx 1.2 V. The 5-V reference (VREF) is enabled with BLON which is the bias
supply for many of the internal blocks of the device.

4 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Pin Functions (continued)

PIN
TYPE DESCRIPTION
NO. NAME
This pin is used to monitor for an undervoltage condition on the load. A level below VUVTH on
this pin causes the converter to disable the gate drive outputs as well as the LEDSW output.
11 UV I Immediately, a TRSTDLY (10 ms) reset delay and soft-start sequence is initiated. The reset
delay and soft-start sequence is repeated as long at the UV pin is low at the end of the
sequence.
This pin is used to monitor for an overvoltage condition on an LED string. A level above
VOVTH on this pin causes the converter to disable the gate drive outputs as well as the
12 OV I
LEDSW output. If the OV input falls below its trip threshold the converter responds with a
TRSTDLY (10 ms) reset delay and soft start.
Current limit input connects to a signal that represents the power converter’s input current.
13 CL I
Dual thresholds provide a shutdown retry or latch-off response.
The dimming slew rate pin is used to limit the rate of the VCO frequency change at the LLC
on or off edges of a dimming PWM cycle. A capacitor to ground at this pin programs the
14 DSR I/O
maximum positive and negative slew rates that appear at the control input to the VCO.
Pulling this pin below about 0.8 V disables the GD outputs.
Current Reference is used to set the regulating voltage for the LED current feedback signal
at the CS input. This voltage input is set using a resistor divider from VREF. A nominal level
of around 0.7 V is recommended although a range of 0.6 V to 2.7 V is accommodated.
15 CREF I Internal reference levels of 0.5 V and 2.8 V replace the CREF input voltage at the current
amplifier when the CREF pin voltage is respectively below or above these levels. The 0.5-V
internal reference can be achieved by shorting CREF to ground, the internal 2.8-V reference
can be achieved by shorting CREF to VREF.
Current sense input monitors the LED current. This signal is compared to VCREF by the
16 CS I
current amplifier to regulate the total LED current.
This output pin is used to compensate the current regulating loop. A capacitor, or capacitor
resistor series combination is typically used. During current regulation the voltage into the
VCO is slaved to this pin. Pulling this pin below about 0.8 V disables the GD outputs. During
17 ICOMP O
PWM dimming OFF-time this pin is tri-stated and the compensation network is meant to hold
the proper LLC control voltage until the LLC converter is turned back on. To optimize this
operation any DC loading on this pin must be avoided.
The soft-start pin is used to control the rate of change of the VCO frequency during start-up.
At start-up a low value pullup current source, ISS, is applied to this pin. A soft-start sequence
18 SS I/O
is initiated at start-up and during any fault recovery. The SS pin must charge to 4.2 V before
the controller allows PWM dimming to take place.
The maximum frequency of the LLC converter is set by a resistor to ground at this pin. It is
19 FMAX I/O actually the difference between the maximum and minimum frequency that is set by this
resistor.
20 FMIN I/O The minimum frequency of the LLC converter is set by a resistor to ground at this pin.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VCC 20 V
LEDSW output current ILEDSW ±2
VREF output current IVREF –20 mA
Gate drive RMS current continuous GD1, GD2 IGD1, IDG2 25
Gate drive voltage, GD1 GD2 VGD1, VGD2 –0.5 VCC + 0.5
CS, CL, OV, UV, BLON, V
Voltage –0.5 7
DIM, CREF
Lead temperature 1.60 mm (1/16 inch) from case for 10 s 260
Operating junction temperature, TJ –55 150 °C
Storage temperature, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

all voltages are with respect to GND; currents are positive into and negative out of the specified terminal. -40°C < TJ = TA <
125°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Operating input voltage 11 18 V
CVCC VCC bypass capacitor 0.47 µF
Operating junction temperature –40 125 °C
Switching frequency at gate drive outputs 25 350 kHz
VCREF Input voltage (linear range) 0.6 1.65 2.7
V
VCREF Input voltage (using internal clamps) 0 VVREF
CVREF VREF bypass capacitor 0.22 1 2.2 µF
CSS SS capacitor 10 250
nF
CICOMP ICOMP capacitor 0.5 47
CDTY DTY capacitor 0.22 6.8 µF
CDSR DSR capacitor 0 2500 pF

6 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

7.4 Thermal Information

UCC25710
THERMAL METRIC (1) DW (SOIC) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 79 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W
RθJB Junction-to-board thermal resistance 44 °C/W
ψJT Junction-to-top characterization parameter 16 °C/W
ψJB Junction-to-board characterization parameter 44 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY INPUT
VVCCMAX VCC operating voltage 18 V
IOFF Supply current, off VVCC = 8 V 160 250 µA
ION Supply current, on Switching frequency = FMIN (30 KHz) 1.4 2.1 mA
IDISABLE Supply current, disabled VVCC = 12 V, VBLON = 0 V 240 350
µA
ILATCHOFF Supply current, latched off Fault latch set 600 900
UNDERVOLTAGE LOCKOUT
VVCCON VCC turnon threshold VVCC low-to-high 8.6 9.3 10.1
VVCCOFF VCC turnoff threshold VVCC high-to-low 8.3 9 9.6 V
VVCCHYS Hysteresis 0.2 0.35 0.5
5-V REFERENCE OUTPUT
VVREF 5-V Reference IVREF = 0 to 10 mA, TJ = 25°C 4.95 5 5.05
V
VVREF 5-V Reference IVREF = 0 to 10 mA, TJ = –40°C to 125°C 4.85 5 5.15
CURRENT AMPLIFIER
VICOMPIOS Input offset voltage VCREF = 1.65 V, ICOMP tied to CS –15 15 mV
ICS Input bias current at CS input VCREF = 1.65 V, VCS = 1.65 V –0.25 0.25
Input bias current at CREF µA
ICR VCREF = 1.65 V, VCS = 1.65 V –0.25 0.25
input
VICOMPHI ICOMP high VCS = 0 V, VCREF = 1.65 V, IICOMP = 50 µA 4.6 4.85
V
VICOMPLO ICOMP low VCS = 3 V, VCREF = 1.65 V, IICOMP = –50 µA 0.35 0.65
GMICOMP ICOMP transconductance ICOMP tied to CS, IICOMP = –100 µA to 100 µA 440 510 600 µs
IICOMPSRC Source current ICOMP VCS = 0.65 V, VCREF = 1.65 V, VICOMP = 2.5 V 120 150 180
IICOMPSNK Sink current ICOMP VCS = 2.65 V, VCREF = 1.65 V, VICOMP = 2.5 V 195 245 295
µA
LED off leakage current at
IICOMPLGK VDIM = 0 V, VICOMP = 2.5 V, TJ = –40°C to 85°C –0.1 0.1
ICOMP
VCREF = 0 V, ICOMP tied to CS, regulating voltage
VCREFCLO CREF low Clamp 0.475 0.5 0.535
at ICOMP
V
VCREF = 3 V, ICOMP tied to CS, regulating voltage
VCREFCHI CREF high Clamp 2.65 2.8 2.95
at ICOMP

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

Electrical Characteristics (continued)

TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT START
ISS Soft-start charging current VSS = 2.25 V 2 2.5 3 µA
Soft-start discharge
RSSDC VSS = 1 V 3.4 5 kΩ
resistance
VSSTH Soft-start threshold SS clamp released 3.95 4.15 4.4 V
TRSTDLY Reset delay From UVLO turnon to start of soft start 7 10 13 ms
VOLTAGE CONTROLLED OSCILLATOR
FMIN FMIN GD1, GD2 RMIN = 100 kΩ, VICOMP = 5 V 29.5 30.5 31.5
kHz
FMAX FMAX GD1, GD2 RMIN = 100 kΩ, RMAX = 4.99 kΩ, VICOMP = 0.95 V 275 300 320
TDT Dead-time GD1, GD2 RMIN = 100 kΩ, VICOMP = 3 V 400 500 600
ns
TMATCH ON-time mismatching RMIN = 100 kΩ, VICOMP = 3 V –50 50
VVCOTHLO VICOMP VCO Threshold Low Disable GD1, GD2, VICOMP high to low 0.8 0.9 0.95
V
VVCOMAX VICOMP for FMIN Frequency reaches FMIN 3.8 4 4.2
GATE DRIVERS
VGDHI GD1, GD2 VOUT high IGD1, IGD2 = –20 mA, below VCC 1.8 3 V
GD1, GD2 ON-resistance
RGDHSRES IGD1, IGD2 = –20 mA 14 30 Ω
high
VGDLO GD1, GD2 VOUT low IGD1, IGD2 = 20 mA 0.08 0.2 V
RGDLSRES GD1, GD2 ON-resistance low IGD1, IGD2 = 20 mA 4 10 Ω
TGDRISE GD1, GD2 output rise time CGD = 1 nF, 1 V to 9 V 25 35
ns
TGDFALL GD1, GD2 output fall time CGD = 1 nF, 9 V to 1 V 20 30
UNDERVOLTAGE PROTECTION
VUVTH Undervoltage threshold High-to-low on UV input 2.27 2.4 2.53 V
Undervoltage threshold
VUVHY 190 240 300 mV
hysteresis
IUV UV input bias current VUV = 2.7 V –0.25 0.25 µA
OVERVOLTAGE PROTECTION
VOVTH Overvoltage threshold Low-to-high on OV input 2.46 2.6 2.74 V
Overvoltage threshold
VOVHY 190 240 300 mV
hysteresis
IOV OV input bias current VOV = 2.3 V –0.25 0.25 µA
CURRENT LIMIT PROTECTION
VCLTH Current limit threshold Low-to-high on CL input 0.9 0.95 1 V
Current limit threshold
VCLHY 375 475 525 mV
hysteresis
Current limit latching
VCLLTH Low-to-high on CL input 1.75 1.9 2.05 V
threshold
ICL CL input bias current VCL = 2.2 V –0.25 0.25 µA
THERMAL SHUTDOWN
Junction temperature at
tTSD Temperature rising 135 160 185
thermal shutdown °C
tHYS Thermal hysteresis 25 45
BACKLIGHT ON INPUT
RBLON RBLON pulldown resistance Pull down to GND 100 200 350 kΩ
VBLON Enable threshold 0.8 1.2 1.6 V

8 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Electrical Characteristics (continued)

TA = –40°C to 125°C, TA = TJ, VVCC = 12 V, VBLON = 3 V, VUV = 3 V, VOV = 2 , VCL = 0 V, RMIN = 100 kΩ, RMAX = 4.99 kΩ,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM DIMMING
VDIM Dimming input threshold 1.2 1.5 1.8 V
RDIM DIM pullup resistance Pullup resistance to VREF, VDIM = 0 V – 4.5 V 140 180 240 kΩ
VLEDSWHI High-level at LEDSW output ILEDSW = –100 µA, below VCC, VDIM = 3 V 0.4 1
V
VLEDSWLO Low-level at LEDSW output ILEDSW = 100 µA, VDIM = 0 V 0.2 0.5
RLEDSWHI High-level output resistance ILEDSW = –500 µA – 0 µA, VDIM = 3 V 4 6
RLEDSWLO Low-level output resistance ILEDSW = 500 µA – 0 µA, VDIM = 0 V 2 3 kΩ
RDTY DTY output resistance VDTY = 0 V – 2.5 V , VDIM = 0 V 30 40 50
VDTYH DTY max level VDIM = 0 V 2.45 2.6 2.7
V
VDTYL DTY min level VDIM = 3 V 0.05 0.1 0.15
IDADJCH DADJ charging current VDADJ = 2.5 V, VDIM = 0 V 16 20 25 µA
RDADJDC DADJ discharge resistance VDADJ = 0.5 V, VDIM = 3 V 1 1.5 kΩ
CADJ = 2.2 nF, VDTY = 2.6 V, delay from DIM high-
TDADJ DADJ delay 225 275 330 µs
to-low to DSR discharge
IDSRCH DSR slew rate charge current VDSR = 2.5 V, VICOMP = 4 V, VDIM = 3 V 38 44 50
DSR slew rate discharge µA
IDSRDC VDSR = 2.5 V, VICOMP = 4 V, VDIM = 0 V 38 44 50
current
VDSRCL DSR clamp above ICOMP VICOMP = 2 V, level above VICOMP 0.45 0.7 0.95 V

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

7.6 Typical Characteristics

1.6 9.5
Switching Frequency = FMIN
No Gate Drive Load 9.4
1.4
Rising - V VCCON
9.3

VVCCON and VVCCOFF Threshold (V)

1.2
VCC Supply Current (mA)

9.2
1.0
9.1

0.8 Turn On
9.0

0.6 8.9
Turn Off
Falling - VVCCOFF
8.8
0.4
8.7
0.2
8.6
0 8.5
0 2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100 120 140
VCC Supply Voltage (V) Temperature (°C)

Figure 1. Supply Current vs Dimming Duty Cycle Figure 2. VVCCON and VVCOFF Threshold vs Temperature
2.0 400
Switching Frequency = FMIN
1.9 No Gate Drive Load
350

IDISABLE and IOFF Supply Current (mA)

1.8
ION Supply Current (mA)

1.7 VVCC = 18 V IDISABLE

300
VVCC = 12 V
1.6 VBLON = 0 V

1.5 250

1.4
VVCC = 12 V
200
1.3

1.2 IOFF
150 VVCC = 8 V
1.2

1.0 100
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Figure 3. Supply Current vs Temperature Figure 4. IDISABLE and IOFF Supply Current vs
Temperature
5.10 400
VCREF = 0 V
300 VCREF = 1 V
V CREF = 1.5 V
5.05
VVREF Reference Voltage (V)

Output Current at ICOMP (mA)

200
VCREF = 5.0 V

100
5.00
V CREF = 2.0 V
0

-100 Sinking Current

4.95

-200
Sourcing Current

4.90 -300
-40 -20 0 20 40 60 80 100 120 140 0 1.0 2.0 3.0 4.0 5.0
Temperature (°C) Input Voltage at CS(V)

Figure 5. Reference Voltage vs Temperature Figure 6. Output Current (ICOMP) vs Input Voltage (CS)

10 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Typical Characteristics (continued)

5% 31.5

GMICOMP Change From Value at 25oC (%) 4% 31.3

3% 31.1

FMIN Switching Frequency (kHz)

2% 30.9

1% 30.7

0 30.5

-1% 30.3

-2% 30.1

-3% 29.9

-4% 29.7

-5% 29.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Figure 7. GMICOMP vs Temperature Figure 8. Minimum Switching Frequency vs Temperature

320 600

580
315
560
FMAX Switching Frequency (kHz)

TDT Gate Drive Dead Time (ns)

310
540
305
520

300 500

480
295
460
290
440
285
420

280 400
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Figure 9. Maximum Switching Frequency vs Temperature Figure 10. Gate Drive Dead Time vs Temperature
12 1.8 12 1.8
CLOAD = 4.7 nF CLOAD = 4.7 nF
RLOAD = 2.5 kW RLOAD = 2.5 kW
10 1.5 10 1.5
Gate Drive Source Current (A)

Gate Drive Sinking Current (A)

Gate Drive Voltage (V)

Gate Drive Voltage (V)

8 1.2 8 1.2
TA = 25oC TA = 25oC

6 0.9 6 0.9

4 TA = 125oC 0.6 4 0.6

TA = 125oC

2 0.3 2 0.3

0 0 0 0
-100 0 100 200 300 -100 0 100 200 300
Time (ns) Time (ns)

Figure 11. Gate Driver Outputs (Rising Edge) vs Time Figure 12. Gate Driver Outputs (Falling Edge) vs Time

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

Typical Characteristics (continued)

2% 450
CDTY = 2.2 mF
400 Dimming Frequency= 300 Hz
IIDSRCH, IIDSRDC Change From Value at 25oC (%) 1.5%

350
1%

TDADJ On-Time Extension (ms)

Discharge Current
300 CDADJ 3.3 nF
0.5%
250
0
Charge Current
200
-0.5%
150
-1%
100 CDADJ 1.0 nF

-1.5% CDADJ 330 pF

50

-2% 0
-40 -20 0 20 40 60 80 100 120 140 0 20 40 60 80 100
Temperature (°C) Dimming PWM Duty Cycle (%)

Figure 13. DSR Currents vs Temperature Figure 14. LLC ON-Time Extension vs Dimming Duty Cycle
330 14
CDADJ = 2.2 nF CLOAD = 100 pF
TA = -40oC
320 VDTY = 2.6 V LEDSW Output
12
310
TDADJ On-Time Extension (ms)

300 10 TA = 125oC

LEDSW Voltage (V)

290
8
280 TA = 25oC
6
270
DIM Input
260 4

250
2
240

230 0
-40 -20 0 20 40 60 80 100 120 140 -1 0 1 2 3 4 5 6 7 8 9
Temperature (°C) Time (ms)

Figure 15. LLC ON-Time Extension vs Temperature Figure 16. LEDSW Rise and Fall vs Time

12 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

8 Detailed Description

8.1 Overview
The UCC25710 is a highly integrated LLC controller designed specifically for multi-string LED lighting
applications. The half-bridge LLC control is combined with independent PWM dimming or non-dimming of the
LED current for control of the light output.
The UCC25710 is designed to provide power from a high voltage DC bus, such as the output from a PFC stage.
Input over current-sensing protects the system in the event of a fault and gate drive outputs provide the drive
signals to the LLC stage. Output overvoltage and undervoltage provide additional protection. LED current is
sensed with a resistor in series with the LED’s. The UCC25710 has separate enable and dimming inputs.
This arrangement of a multi-transformer architecture, as shown in Figure 25, results in a highly efficient power
supply.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

8.2 Functional Block Diagram

UVLO
VVREF
VCC 1 + RST Gen
VVCCON/VCCOFF * 2.5 mA
S Q RESET
9.3 V/9.0 V
H L
ENBL FAULT R Q
ENBL
delay
5V
VREF 5
REF TRSTDLY
10 ms 7 DTY
VVREF
~4 V
BLON 10 IDADJCH
20 mA
200 kW
SS-END + 8 DADJ

VVREF
GD Enable
GD2 3 200 kW
LLC-OFF
Dead Time

OFF 9 DIM
ON
H
Edge Sync Dimming PWM 80 kW
GD1 2
D Q
2*F

GND 4 Q 80 kW
CLR
SS-END
FSW
VCO GD Toggle
FMIN 20 FMAX
RESET
D Q
LED-ON
FMIN Q
VVCO CLR
FMAX 19 6 LEDSW
1V 4V
0.9V

Zero Frequency Command

VVCO
Latch-Off VCLLTH
LATCH -OFF Q S 1.9 V
VCLREFCLO, 0.5 V Low ICC
VCLREFCHI, 2.8 V
LED-ON FAULT Q R UVLO
CREF 15 Current delay
+ Amplifier 2.4 ms
+
+ VVREF
H
CS 16 GMICOMP TSD
DIM ON/OFF + 13 CL
510 mS CLAMP VCLTH
+ VVREF
ICOMP 17 0.95 V/0.475 V
Dimming Slew IDSRCH
Control
ICOMP 44 mA
GND + 12 OV
LLC-OFF
4 kW L VOVTH
DSR 14 2.6 V/2.4 V
VVREF H
ISS SS Clamp
IDSRDC
2.5 mA + 44 mA
VUVTH
SS-END + 2.4 V/2.6 V
D
isa

11 UV
b
le

SS 18 Soft Start

VSSTH S Q
4.2 V
*
UCC25710
R Q

RESET

14 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

8.3 Feature Description

Signal names and pin functions are depicted in Functional Block Diagram.

8.3.1 Multi-transformer Architecture

The multi-transformer LED driver architecture is a very attractive solution for driving multiple LED strings at the
same current using a single power train and control device. Excellent LED string current matching from string to
string (<1%) excellent LED current linearity from 1% to 100% dimming (<2%), and high efficiency can be
achieved (>94%). Because this architecture is intended to use the 400-V output of the PFC stage, there is a
significant cost advantage over typical LED backlight implementations because a power stage can be eliminated.
The architecture and UCC25710 control device are based on the LLC resonant half-bridge topology. The
controller feedback loop is configured to regulate the total LED current typically with a current-sense resistor. The
arrangement of the transformers with the primaries in series provides excellent LED string current matching.
Because the primaries are in series, the current in each transformer primary is the same. The secondary current
is the primary current times the turns ratio. The net primary magnetizing current is circulated in the primary side
of the half bridge and does not affect the current transferred to the outputs. In each transformer, differences in
magnetizing current caused by different magnetizing inductance or winding voltage will cause a difference in
current transferred to the LED outputs, although the difference in transferred current is minimal with typical
transformer tolerances and following the guidance in the Determining Transformer and Resonant Circuit
Parameters below.
The UCC25710 includes all of the functions necessary to implement a total LED backlight driver including GM
current amplifier, VCO, reference regulator, soft start, dimming duty cycle compensation and protection for OV,
UV, current limit, and thermal shutdown. There are additional features to minimize audible noise during dimming
and provide fast LED current rise and fall times.

8.3.2 Start-Up and Non-Dimming Operation

The UCC27510 is enabled when VCC exceeds the VVCCON threshold and BLON is high. At this time the soft-start
cycle is initiated following a 10-ms reset delay. A 2.5-µA current source charges the capacitor connected to the
SS pin to generate the soft-start ramp. During the soft-start cycle the current amplifier output (ICOMP) is clamped
to be equal to or less than SS voltage. The voltage on ICOMP controls the VCO. VICOMP achieves the steady
state operating point to regulate the total LED current during the soft-start rise time. The DIM input and the UV
input are disabled during soft start to allow the output capacitors to charge to the steady-state operating voltage.
When the SS pin reaches the VSSTH threshold the SS-END signal transitions high indicating the end of the soft-
start cycle. At this time the UV comparator and DIM input are enabled. See Figure 17 for the timing relationship
during soft start.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

Feature Description (continued)

9.3 V 9.0 V
Controller Enabled
VCC
VREF
UVLO
10 ms
Dimming
Enabled

RESET
Soft-Start
Over
Soft-Start
SS
ICOMP
DSR

Operation
Disabled

GD1,2

LEDSW

DIM
UDG-11095

Figure 17. Start-Up Timing Diagram

8.3.3 Dimming Operation

Once the soft-start cycle is complete, the LEDSW output and control of the VCO depend on the DIM input. The
dimming input signal controls the LEDSW output maintaining an accurate ON-time relationship between the DIM
pulse width and LED current pulse width; the internal control signal is LED-ON. The LED-ON signal also controls
a switch between the GM current amplifier output and the ICOMP pin. On the DIM rising edge the switch from
the amplifier to the ICOMP pin is turned on after a 2.4-µs delay. The small delay time allows time to turn on the
LED switch MOSFET. On the DIM falling edge the switch between the GM amplifier is turned off. During the DIM
OFF-time the compensation capacitor at the ICOMP pin holds the correct steady-state operating voltage for the
current loop. It is important that any DC loading of this pin is kept to an absolute minimum or current errors
results as the dimming duty-cycle is reduced.
The LLC power stage is gated on and off during dimming with the dimming input signal. The UCC25710 allows
control of the slew rate of the LLC power delivery at the rising and falling edges of a dim cycle allowing
potentially audible electro-mechanically induced noise to be minimized. In addition, the falling, or turnoff, edge of
a dimming cycle can be delayed, allowing the current loop to maintain control at low dimming duty-cycles even
when the ramp rates have been slowed. See Figure 18.

16 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Feature Description (continued)

LEDSW
DIM
DTY = 0.1V + 2.5V*(1-D)
DADJ

DTY

Added
LLC On-Time

ICOMP

DSR
LLC On/Off
Slew Rate

IPri

UDG-11096

50% Dimming 10% Dimming

Figure 18. Dimming Timing Diagram

The power through the LLC converter is inversely proportional to the frequency of the VCO. The VCO frequency,
in turn, is inversely proportional to the VCO control signal. See Figure 19 for details of this relationship. The
dimming input generates an LLC-OFF signal that is used to select either a charging or discharging state for a
capacitor applied to the DSR pin. The ±44 µA of current and associated capacitor set a ramp rate for the rise and
fall of the DSR voltage. The control voltage to the VCO is dominated by the DSR voltage when the DSR voltage
is less than the ICOMP pin – allowing the falling ramp on the DSR pin to softly turnoff the LLC power stage and
softly return it to the same operating state as it rises.
FSW

FMAX
VCO Frequency

both low
GD1&2

FMIN
VVCO

1V 4V
VCO Control Voltage
0.9 V UDG-11097

Figure 19. VCO Characteristics

The LLC-OFF signal is an inverted version of the dimming input signal. The falling edge of LLC-OFF is
synchronized with the rising edge of the DIM signal. At a negative DIM edge the DADJ and DTY signals are
combined to delay the rising edge of LLC-OFF providing a duty-cycle compensation time that is a function of the
dimming duty cycle.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

Feature Description (continued)

Averaged by a capacitor at the DTY pin, the voltage on DTY is inversely proportional to the dimming duty cycle;
the voltage is
0.1 V + 2.5 V × (1-D)
where
• D is the dimming PWM duty-cycle (1)
The DTY voltage range is 100 mV at 100% DIM duty-cycle, or LED current continuously on, to 2.6 V at 0% DIM
duty cycle, or LED current continuously off. The DADJ pin 20-µA current source is allowed to charge the pin
capacitor after a DIM falling edge. The LLC-OFF signal transitions high when the capacitor on DADJ charges to
the voltage on DTY. See Figure 18 for the timing relationship during dimming. The scope plots in Figure 20 and
Figure 21 below show an example LED driver at 10% and 50% DIM duty cycle.

Figure 20. DIM 10% at 300 Hz Figure 21. DIM 50% at 300 Hz

8.3.4 Fault Condition Operation

The UCC25710 has a similar response to overvoltage, thermal shutdown and current limit faults. Figure 22
shows the fault response. The OV input has a 2.6-V threshold and 240 mV of hysteresis. When OV is above 2.6
V the internal FAULT signal is active which results in the RESET signal going high. With RESET high the gate
drivers are disabled, the SS pin is discharged to ground, and the LEDSW output is turned off. When OV is below
2.36 V the FAULT signal is inactive which starts the 10-ms SS clamp timer.

OV, CL,
TSD Fault
10 ms
SS

RESET

GD1,2
UDG-11100

Figure 22. OV, CL(1 V) and TSD Fault Timing Diagram

18 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Feature Description (continued)

RESET is extended 10 ms beyond FAULT going low. After the 10-ms soft-start timer the normal soft-start
sequence begins. Thermal shutdown generates the same internal FAULT signal when the internal temperature
reaches 160°C and a restart sequence begins after the junction temperature drops by the 25°C of threshold
hysteresis.
The current limit comparator has two thresholds. The lower threshold of 0.95 V results in a shutdown and restart
as described for OVP, the OC pin has 0.475 V of hysteresis. The second current limit threshold of 1.9 V results
in a latch-off fault. VCC must be recycled below the VCCOFF threshold to reset the latched OC fault.
The undervoltage fault has a different response to allow the converter to charge the output capacitors in a normal
start-up condition. Because UV is disabled during soft start, a sustained UV fault results in a 10-ms soft-start
clamp time plus the time required for the SS pin to charge to VSSTH which is 4.15 V. See Figure 23 for UV fault
condition timing diagrams.

UV Fault

SS

RESET

LEDSW

GD1, 2
UDG-11101

Figure 23. UV Fault Timing Diagram

8.4 Device Functional Modes

The device has two functional modes: non-dimming and dimming.
In the non-dimming mode the DIM input pin is held high (above 1.5 V typically)
In the dimming mode the DIM pin is switched between high and low levels.
The dimming slew rate controls the rate of change between the high and low LED currents.
This is set with a capacitor on the DSR input pin.
Additionally, a capacitor on the DADJ input pin extends the falling edges of the dimming cycle.
This allows for control at very low dimming ratios.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC25710 offers a highly integrated solution for LLC control of LED lighting. To the part easier to use, TI
has prepared an extensive set of materials to demonstrate the features of the device. The UCC25710 offers a
highly integrated feature-set and excellent accuracy to control the LED current in highly efficient LLC type power
supplies with dimming or without dimming requirements.

9.2 Typical Application

To take advantage of all the benefits integrated in this controller, the following procedure simplifies the setup to
avoid unnecessary iterations in the design procedure. See Figure 24 setup for component names.

20 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Copyright © 2016, Texas Instruments Incorporated

Note parts with no value are populated

Figure 24. UCC25710 Controller Setup

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

9.2.1 Design Requirements

Table 1 lists the design parameters of this example.

Table 1. Design Parameters

PARAMETER MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage 370 390 410 V
IIN Input current 0.275 A
OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT 4 CHARACTERISTICS
VLED1, VLED2,
Output voltage set by LED load 96 98 100 V
VLED3, VLED4
ILED1, ILED2,
Output current ripple 0.0125 AP-P
ILED3, ILED4
ILED1, ILED2,
Output current 0.245 0.25 0.255
ILED3, ILED4
ILED1, ILED2,
Line regulation 0.245 0.25 0.255 A
ILED3, ILED4
ILED1, ILED2,
Load regulation 0.245 0.25 0.255
ILED3, ILED4
VOVP Single output OVP 136
V
VUV Single output undervoltage 43
Dimming range 1% 100%
Dimming frequency 270 300 330 Hz
Current matching between strings (10% to 100% dimming) –2% 2%
Output power single output 24.5
W
Full output power
SYSTEM CHARACTERISTICS
FSW 84 156 kHz
η 91% 93%

9.2.2 Detailed Design Procedure

9.2.2.1 Determining Transformer and Resonant Circuit Parameters

The muti-transformer architecture is similar to conventional LLC converter design with a few exceptions that are
described in this section. Typical LLC voltage output converters are designed to operate nominally close to
resonance and have the minimum switching frequency below resonance and maximum frequency above
resonance. TI recommends operating above resonance at the nominal input voltage range of the converter to
achieve good transient response during dimming and improved LED current matching. The transformer turns
ratio equation shown is to target operation above resonance.
Use Equation 2 to calculate the turns ratio of the transformers in the multi-transformer architecture.
N VIN
N= P =
NS 2 ´ NT ´ VLED

where
• N is the primary to secondary turns ratio
• NP is the primary turns
• NS is the secondary turns
• VIN is the input voltage to the LLC converter, typically the output of the PFC boost converter
• NT is the number of transformers
• VLED is the LED string voltage (2)

22 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

Another important consideration for the multi-transformer LED driver is to set the total magnetizing inductance of
the transformers as high as possible to minimize the primary magnetizing current and it’s effect on LED current
matching. TI recommends targeting the total magnetizing inductance of the transformers to a value just low
enough to achieve ZVS operation during nominal frequency operation. Equation 3 and Equation 4 determine the
magnetizing inductance target. Reduce the calculated LM to accommodate LM and COSS tolerances.
2 ´ COSS ´ VIN
IMPk =
400ns (3)
æ ö
VIN ´ çç 0.5 -500ns ÷÷
è FSW ø
Lm =
4 ´ IMPk ´ NT

where
• IMPk is the peak magnetizing current
• COSS is the MOSFET equivalent time related drain to source capacitance
• VIN is the nominal input voltage to the half bridge, normally the PFC output voltage
• FSW is the switching frequency at the regulation operating point
• LM is the magnetizing inductance of each transformer
• NT is the number of transformers with the primaries in series (4)
To use standard LLC converter design process and available tools such as SLUC253 design calculator available
on the TI website, the multiple transformers and reflected loads can be combined into one equivalent transformer
and load as shown in Figure 25. Once Lr and Lm are determined based on a single transformer circuit, simply
divide by the number of transformers for each transformer specification target.
Multi-Transformer Single Transformer Equivalent

Lr Lr ’
T1 T1
Lm NP NS – + Lm’ NP’ NS – +
½ Cr
RL=VLED
ILED RL’=RL
NT
T2
½ Cr ½ Cr
– +

Primary turns (NP), leakage

½ Cr inductance (Lr), and magnetizing Secondary is combined as
TN inductance (Lm) are combined as parallel equivalent:
a series equivalent: RL’=RL/NT
– +
Lr’=Lr x NT Ns is unchanged
NP’=NP x NT
Lm’=Lm x NT
NT is the number of transformers
UDG-11102

Figure 25. Multiple Transformers Combined With Reflected Loads

9.2.2.2 CS (Output Current Sense)

The CS pin is connected to the output current-sense resistor and is the feedback signal for the current amplifier.
The regulation range is limited by the 0.5-V to 2.8-V internal current amplifier reference clamp. The LED current
sense resistor value is determined by Equation 5.
V
RCS = CREF
ILEDTotal

where

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

• VCREF is voltage on CREF pin determined by divider from VREF ILEDTotal.

• ILEDTOTAL is the total LED string current during the DIM on time. (5)

9.2.2.3 ICOMP (Current Amplifier Compensation)

Connect a capacitor or series resistor capacitor combination to ground to compensate the 510-µS GM current
amplifier control loop. The current amplifier is designed to maintain the steady-state operating voltage point of the
current amplifier during dimming operation. This is accomplished by switching on and off the GM current amplifier
to the ICOMP pin with the same control signal that controls the LEDSW output. The GM amplifier is disconnected
from the ICOMP pin during the DIM OFF-time, and connected during the DIM ON-time. This feature is
compromised if there is a leakage path on the ICOMP pin, such as resistance to ground. The re-connection of
the ICOMP pin to the current amplifier output is delayed by about 2.4 µs to allow time for the external LED switch
to be turned on prior to allowing the ICOMP pin voltage to be driven.
The optimum ICOMP capacitor value is determined based on desired LED current and primary current response
during dimming. Because the LLC converter has a highly nonlinear transfer function, a gain phase analyzer is
recommended to optimize the component values on ICOMP. The recommended bandwidth target is from 800 Hz
to 5 kHz. The trade-off of too low bandwidth is increased line frequency ripple on the LED string current. The
trade-off of high bandwidth is voltage variation on ICOMP during the DSR rise time which can result in primary
current peaking during the start of the DIM period, this may result in audible noise if excessive. Either an
integrator (capacitor to ground) or type II compensation (capacitor in parallel with resistor and series capacitor) is
recommended.

9.2.2.4 SS (Soft Start)

Connect a capacitor to ground to program the desired soft-start time. When VCC exceeds the VCCON threshold
and BLON is high, a 2.5-µA current source charges the soft-start capacitor after a 10-ms delay. The voltage on
SS dominates the VCO control voltage when lower than VICOMP or VDSR. The device is in a soft-start condition
until VSS reaches the 4.2-V soft start over threshold. During the soft-start cycle DIM is disabled and the UV
protection is disabled. The soft-start cycle is initiated by UVLO, BLON, OV fault clear, or UV fault clear after the
soft-start cycle.
2.5 mA ´ TSS
CSS =
VICOMP _ REG - 0.9 V

where
• TSS is the target SS time.
• VICOMP_REG is the ICOMP voltage at the regulation point, which can be derived based on LLC switching
frequency. (6)

9.2.2.5 FMAX (Maximum VCO Frequency)

Terminate FMAX to ground with a resistor to program the frequency delta from desired maximum to minimum
operating frequency range. The recommended resistor value range is 4.22 kΩ to 53.6 kΩ. VICOMP which is the
VCO control signal determines the voltage on FMAX; the programming resistor determines the voltage to current
conversion ratio that programs the oscillator frequency at a given VICOMP voltage level. The device is designed to
accommodate a maximum frequency of 350 kHz and a minimum frequency delta of 25 kHz. To provide
controlled rise and fall time of the primary current during dimming, a maximum frequency of 2 to 3 times the
nominal switching frequency is recommended as an initial value. The resistor value can be determined by
Equation 7.
0.0664
RMAX =
49.2pF ´ FSW (Delta)

where
• FSW(Delta) = FSW(max)-FSW(min) (7)

9.2.2.6 FMIN (Minimum VCO Frequency)

Terminate FMIN to ground with a resistor to program the desired minimum operating frequency. The
recommended resistor range is 9.53 kΩ to 102 kΩ. The device is designed to accommodate a minimum
frequency of 30 KHz. The resistor value can be determined by Equation 8.

24 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

0.15
RMIN =
49.2pF ´ FSW(min)
(8)
Use Equation 9 to determine FSW for given VICOMP, RFMAX, and RFMIN values.
0.15 (4 V - VICOMP )
+
RMIN RMAX ´ 45.2 V
FSW =
49.2pF
where from Equation 7 to Equation 9
• FSW is in Hz, R is in Ω
• VICOMP is in V (9)

9.2.2.7 GD1 and GD2 (Gate Drive 1 and 2)

Connect the primary of the gate-drive transformer to GD1 and GD2 through a small series resistance. The high-
side driver resistance is 12 Ω and low-side driver resistance is 4 Ω typical. The drivers are limited to 25-mA RMS
maximum current, so there is a magnetizing current limitation of the gate-drive transformer shown in the
Equation 10. If the magnetizing current exceeds 25 mA with the specified gate-drive transformer and nominal
operating frequency, a simple NPN-PNP buffer on GD1 and GD2 may be required. The minimum gate drive
transformer inductance can be determined from Equation 10.
VCC
LGD =
2 ´ FSW ´ 87mA

where
• LGD is the gate drive transformer LPRI
• FSW is the nominal switching frequency
• VCC is the VCC supply voltage (10)

9.2.2.8 LEDSW (LED Switch Drive)

The LEDSW is the output to control the LED switch MOSFET in series with the LED string returns. The LEDSW
is controlled by the DIM input during normal operation to provide LED string current pulse widths that
corresponds to the DIM signal. During soft start, the LEDSW signal is high regardless of the DIM signal to allow
the output capacitors to charge. The LEDSW is low during an OV, UV or CL fault to provide additional protection
to the LED’s. This output is 0 V to VCC but has limited drive current ability, a simple NPN or PNP buffer is
required to drive the LED switch MOSFET. The LEDSW high resistance is 4 kΩ and low side is 2 kΩ, so avoid
any DC load on this pin.
The turnon and turnoff delay of the LED switch MOSFET relative to DIM rising and falling edge must be well
matched to achieve excellent LED current linearity especially at low DIM duty-cycles. As an example, consider a
1% dimming duty-cycle at dimming PWM frequency of 300 Hz where a delay mismatch of 667 ns represents a
2% linearity error. A gate-drive resistor and parallel resistor diode combination to drive the LED switch MOSFET
can be used to match edge delays. Refer to Figure 26 for a recommended LED switch MOSFET drive circuit.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

LED Strings
Common Return
VCC 1

LEDSW 6

UDG-11091

Figure 26. Recommended LED Switch MOSFET Drive Circuit

9.2.2.9 DSR (Dimming Slew Rate)

The DSR pin is used to control the rise and fall time of the VCO control voltage. The DSR capacitor value can be
determined by Equation 11. The effective rise time of the LLC primary current is when VDSR is between the 0.9-
V gate-drive enable voltage and the VICOMP operating point.
44 mA ´ TSLEW
CDSR =
VICOMP _ REG - 0.9 V

where
• TSLEW is the desired LLC current rise and fall time
• VICOMP_REG is the ICOMP voltage regulation point (11)
Because the DSR voltage starts at 0 V and the LLC gate-drive enable is typically 0.9 V, there is a delay from the
DIM rising edge and LEDSW rising edge until the LLC gate drivers are enabled. An easy solution to eliminate a
majority of the delay is to use a resistor in series with CDSR. Because DSR is clamped at a Vbe above VICOMP,
the recommended resistance is 15 kΩ to 17 kΩ to provide a 640-mV to 720-mV initial voltage delta.

9.2.2.10 DTY (Dimming Duty-Cycle Average)

The DTY pin generates a voltage inversely proportional to the DIM duty-cycle with a 100-mV offset. The voltage
range is 100 mV to 2.6 V corresponding to 100% dimming and 0% dimming. This voltage is compared to the
DADJ rising ramp to determine the dimming duty-cycle compensation delay time.
The capacitor value is selected to provide low ripple voltage at the DIM frequency. A good guideline is to target
100 V or less peak-to-peak ripple voltage. There is a trade-off of DTY capacitor value and response to DIM duty-
cycle transients. For faster response time to significant changes in DIM duty-cycle select a lower value
capacitance. Equation 12 can be used to select a DTY capacitor based on maximum ripple voltage and DIM
frequency.
15.65 mA
CDTY =
VDTY(pp) ´ FDIM

where
• FDIM is the dimming frequency
• VDTY(pp) is the maximum peak to peak ripple voltage. (12)
Equation 13 can be used to determine the average of VDTY at any given DIM duty-cycle.
VDTY = éë(1 - DDIM )´ 2.5 V ùû + 0.1V

where DDIM is the DIM duty-cycle. (13)

26 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

9.2.2.11 DADJ (Dimming Duty-Cycle Adjust)

The DADJ pin is a 20-µA current source enabled at the DIM falling edge. The capacitor connected to this pin
determines the slope of VDADJ. LLC-OFF is the internal signal that controls the turnon and turnoff of the LLC
power stage. The rising edge of LLC-OFF corresponds to a falling edge at the DIM input. The falling edge of the
LLC-OFF signal is delayed until the rising edge of the DADJ voltage crosses the voltage on DTY. See Dimming
Operation discussion for more details.
An initial value DADJ capacitor can be determined by Equation 14. The dimming performance at lowest DIM on
time must be evaluated as described in the following paragraph.
æ DIMDMIN ´ TRISE DIMDMIN ö
20 mA ´ ç - ÷
ç FDIM FDIM ÷ø
CDADJ = è
éë(1 - DIMDMIN )´ 2.5 V ùû + 0.1V

where
• DIMDMIN is the minimum dimming duty cycle
• FDIM is the dimming frequency
• TRISE is the effective DSR rise time (14)
To ensure consistent LED current regulation during DIM duty-cycle transients, it is important to confirm that
ICOMP achieves the steady-state operating voltage at the lowest DIM duty-cycle. Because DSR is clamped a
VBE (approximately 0.7 V) above ICOMP, this signal can be inspected to confirm a steady-state operating point is
achieved after the programmed DSR rise time. Confirm that the DSR signal achieves a relatively flat voltage
during the lowest DIM duty-cycle condition. Figure 27 and Figure 28 below are scope plots of 1% DIM duty-cycle
where DSR reaches the steady-state operating point, and 0.5% DIM where DSR is still rising and ICOMP is open
loop. If DSR is still rising during the lowest DIM duty cycle, increase the DADJ capacitor value until DSR
achieves a relatively flat response as shown in Figure 27, the 1% DIM duty-cycle scope plot below.

Figure 27. 1% DIM duty-cycle Figure 28. 0.5% DIM duty-cycle

9.2.2.12 OV (Output Overvoltage)

The OV pin is connected to an output-voltage sense resistor divider with oring diodes to all of the LED outputs.
The OV threshold is 2.6 V with 240-mV hysteresis. During an OV fault the GD1 and GD2 gate drivers are
disabled and the LEDSW goes low (off). When the OV fault clears, the soft-start cycle is initiated.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

A configuration is shown in Figure 29 below that allows for summing of multiple LED string outputs into common
UV and OV dividers. Consider the total resistance of the divider networks because the divider bias current is
provided by the highest voltage LED string. Equation 15 and Equation 16 can be used to determine total divider
resistance and each component values.
2 ´ VOUT ´ 1.5
ROV1 =
IOUT ´ DMIN ´ IMATCH

where
• VOUT is LED string voltage
• IOUT is LED DC output current
• DMIN is minimum dimming duty-cycle
• IMATCH is LED current matching target
• OV and UV dividers are approximately equal resistance (15)
ROV1 ´ 2.6 V
ROV2 =
VOVLO - 2.6 V - VD

where
• VOVLO is the OVP threshold
• VD is the summing diode voltage drop (16)
IBIAS
LED1

LED2 RPU

RUV1 ROV1

LED3 UV OV

CUV RUV2 COV ROV2

LED4
UDG-11103

Figure 29. Application of Overvoltage and Undervoltage

9.2.2.13 UV (Output Undervoltage)

UV is connected to an output-voltage sample of the converter. The UV threshold is 2.4 V with 240-mV hysteresis.
UV below 2.4 V is considered an undervoltage fault which disables the GD1 and GD2 gate drivers, LEDSW
output goes low, the 10-ms soft-start clamp and soft-start cycle are initiated. The UV comparator is disabled until
SS voltage is 4.2 V to allow the output capacitors to charge to the normal operating voltage during start-up of the
converter.
See the OV and UV divider diagram above for a typical configuration that allows for summing of multiple LED
string outputs into common UV and OV dividers. Consider the value of RPU to avoid a current path from the
highest voltage LED string to the lowest voltage LED string. Equation 17, Equation 18, and Equation 19 assume
a 2× VOUT delta as the maximum UVLO voltage.
R
RPU = OV1
5
where
• LED voltage total tolerance is ±5%

28 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

• OV and UV dividers are approximately equal resistance (17)

RUV1 = ROV1 - RPU (18)

RUV2 =
(RUV1 + RPU )´ 2.4 V
VUVLO - 2.4 V - VD

where
• VUVLO is the UVP threshold
• VD is the summing diode voltage drop (19)

9.2.2.14 CL (Current Limit)

The CL pin is typically connected to the rectified and filtered output of a primary current sense transformer. There
are two levels of current limit protection: restart and latching. When CL exceeds 0.95 V the gate drivers are
disabled and LEDSW goes low, when the CL voltage reduces to 475 mV the soft-start cycle is initiated. If CL
exceeds a 1.9-V threshold, the gate drivers are disabled and LEDSW goes low, this condition is latched until
VCC is recycled below the UVLO threshold.

9.2.3 Application Curves

Gate Drive Transition After Switch Node Achieving ZVS

98-W EFFICIENCY WITH PWM DIMMING
CH4 = Primary Transformer Current
CH3 = Current Sense = V@R13

95

94

93

92
Efficiency - %

91

90

89

88
CH2 = Switch Node = Q2d CH1 = Switch Node = Q2g
87 Efficiency 390 V

86 Efficiency 370 V
Efficiency 410 V
85
10 25 40 55 70 85 100

Dimming - %
Figure 30. Efficiency 10% to 100% PWM Dimming Figure 31. VIN = 390 V, Outputs Loaded With 32, Cree
XLamp CR-E , LEDs

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

CH1 = V@R13
CH1 = V@R13

CH4 = (LED4 +) Current

CH4 = (LED2 +) Current

CH3 = (LED1 +) Current CH3 = (LED3 +) Current

Figure 32. Current LED1 (CH3) and LED2 (CH4) Figure 33. Current LED3 (CH3) and LED4 (CH4)

CH1 = V@R13 CH1 = V@R13

CH4 = (LED2 +) Current CH4 = (LED4 +) Current

CH3 = (LED1 +) Current CH3 = (LED3 +) Current

Figure 34. Current LED1 (CH3) and LED2 (CH4) Figure 35. Current LED3 (CH3) and LED4 (CH4)

CH1 = V@R13 CH1 = V@R13

CH4 = (LED2 +) Current CH4 = (LED4 +) Current

CH3 = (LED1 +) Current

CH3 = (LED3 +) Current

Figure 36. Current LED1 (CH3) and LED2 (CH4) Figure 37. Current LED3 (CH3) and LED4 (CH4)

30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

10 Power Supply Recommendations

The UCC25710 is designed to operate from an external bias supply connected to the VCC input. It has an
operating voltage range between 11 V and 18 V with an absolute maximum input voltage rating of 18 V.
In most applications, the high voltage input range of the LLC controller is normally set at about 370 V to 410 V
with 390-V nominal. This narrow range of DC input voltage is a constraint of the LLC topology. Setting the
maximum and minimum switching frequencies limits the regulation range to these input voltages.

11 Layout

11.1 Layout Guidelines

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the
integrity of the ground signal. Separating the high di/dt induced noise on the power ground from the low current
quiet signal ground is required for adequate noise immunity. As shown Figure 38, the bypass capacitors on VCC
and VREF have one end located in close proximity to their associated pins and the other ends are returned
directly to the GND pin or to the portion of the ground plane associated with the low level GND signal and not to
the high current power return. Low-ESR type ceramic capacitors are recommended as bypass capacitors.
The gate-drive output signals (GD1 and GD2) can cause interference on the low-level inputs (CL and CS) and for
this reason must be routed as far as possible away from them and have short direct paths to the gate-drive
transformer. In general any slow-changing analog signals must be routed away from high-speed digital signals.
Timing resistors FMIN and FMAX must be placed as close as possible to the pins on the UCC25710.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Links: UCC25710
UCC25710
SLUSAD7B – APRIL 2011 – REVISED JULY 2016 www.ti.com

11.2 Layout Example

GND

20 1 VCC

GND
CS VREF

CL
11 10

Figure 38. Layout Example for UCC25710

32 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: UCC25710

 UCC25710
www.ti.com SLUSAD7B – APRIL 2011 – REVISED JULY 2016

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 33

Product Folder Links: UCC25710
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Feb-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UCC25710DW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 UCC25710
& no Sb/Br)
UCC25710DWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 UCC25710
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Feb-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC25710DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Feb-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC25710DWR SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated