SRI RAMAKRISHNA ENGINEERING COLLEGE
[Educational Service: SNR Sons Charitable Trust]
[Autonomous Institution, Reaccredited by NAAC with ‘A+’ Grade]
[Approved by AICTE and Permanently Affiliated to Anna University, Chennai]
[ISO 9001:2015 Certified and all eligible programmes Accredited by NBA]
VATTAMALAIPALAYAM, N.G.G.O. COLONY POST, COIMBATORE – 641 022.
Department of Electronics and Communication Engineering
Internal Test – I-Answer Key
Date 25.02.2025 Department ECE
Semester IV Class/section B.E. - IT /A / B
Duration 2:00 Hours Maximum marks 50
Course Code &Title:20EC223 DIGITAL CIRCUITS AND MICROCONTROLLERS
Course Outcomes Addressed:
CO1: Simplify the Boolean expressions.
CO2: Design the combinational and sequential logic circuits.
CO3:Summarize the concepts of data converters and semiconductor memories
Questions Cognitive
PART – A (Answer All Questions) (10*1 =10 Marks) Level/CO
1. Select the Boolean function(s) equivalent to x + yz, where x, y, and z are Boolean U/ CO1
variables, and + denotes logical OR operation.
a) x + z + xy b) (x + y) (x + z) c) x + xy + yz d) x + xz+ xy
2. Select the correct absorption law. R/CO1
a) A+ AB = A b) AB + AA’ = A c) A + AB = B d) A+ B = B
3. How many bits are needed to store one BCD digit? R/ CO1
a) 2 b) 4 c) 3 d) 1
4. Recall which of these sets of logic gates are known as universal gates. R/CO1
a) OR, NAND, b) XOR, NOT c) NOR,XNOR d) NOR, NAND
5. How many binary bits are necessary to represent 748 different numbers? R/ CO1
a) 9 b) 7 c) 10 d) 8
6. Indicate one of the following, which can be used as parallel to series converter? U/ CO2
a) Decoder b) Digital c) Multiplexer d) Demultiplexer
Counter
7. Identify which digital output corresponds to an analog input of 6.6 Volts on a 4-bit U/CO3
counting ADC with a resolution of 0.5 Volts.
a) 0110 b) 1101 c) 1110 d) 1111
8. State 00 is used as a memory in the SR latch using NOR gates. R/CO2
9. In a DRAM, information is stored in a capacitor. R/CO2
10. A PLA can be used to realize a combinational logic circuit by providing a configurable R/CO2
set of logic gates and connections.
PART – B (Answer All Questions) (5*2 =10 Marks) Cognitive
Level/CO
11. Interpret the correct simplified form of the following Boolean expression. The U/CO1
______________________
___ ___ ___
Boolean expression is ( X +Y )( X + Y )+(( X Y )+ X ) .
12. Convert Y = AB + ACD into standard SOP form. U/CO1
13. Outline about the DRAM U/ CO3
Definition: DRAM (Dynamic Random-Access Memory) is a type of volatile memory
that stores data using capacitors and requires periodic refreshing to maintain the stored
information.
Working: Each memory cell consists of a transistor and a capacitor; the capacitor holds
the data in the form of charge, which leaks over time, requiring frequent refresh cycles.
Types: Includes SDRAM (Synchronous DRAM), DDR (Double Data Rate) SDRAM,
EDO DRAM, and RDRAM (Rambus DRAM).
Advantages: High storage capacity, cost-effective, widely used in main memory for
computers and mobile devices.
Disadvantages: Requires continuous refreshing, consumes more power than SRAM,
and has slower access speed.
Applications: Used in computers, laptops, gaming consoles, servers, and mobile devices
as primary memory.
14. Determine the equivalent binary and octalvalues for decimal (451)10. Ap/CO1
15. Summarize the need for a sample and hold circuit. U/CO3
Analog-to-Digital Conversion (ADC) Stability – Ensures a stable input voltage during
ADC conversion, preventing errors due to signal fluctuations.
Signal Processing – Captures fast-changing analog signals and holds them momentarily
for processing in digital systems.
Precision and Accuracy – Maintains signal integrity by reducing noise and distortion,
essential for accurate measurements in control systems and communication.
PART – C (3*10 = 30 Marks)
16. Compulsory Question: Ap/CO1
Apply Quine McCluskey / Tabulation method for
∑
F (a, b, c, d) = m ( 1,2,3,7,8,9,10,11,14,15 ) and obtain simplified SOP.
(Binary Representation: 2 Marks, Group: 2 marks, Cell combination: 3 mark, Prime
table : 2 mark, Equation :1 mark)
Table 1: Binary Representation of minterms
Table 2: Group of minterms for different number of 1’s
Table 3: 2-Cell Combinations
Table 4: 4-Cell Combinations
Table 5: Prime Implicants Table
SOP = B’D + B’C + AB’ + CD + AC
Any Two Questions
17. Construct a digital control system for an automated assembly line, using logic gates Ap/CO2
to ensure the encoder's 4-bit output, which uniquely changes only one bit between
consecutive values, is effectively decoded by the robotic arm controllers for precise
operational accuracy.
(Explanation:1, Truth Table: 3 Marks, K-Map & Expression: 3 Marks, Logic
Diagram: 3 Marks)
A Gray to Binary code converter is a circuit that converts a Gray code input into its
equivalent binary code. The conversion follows these steps:
1. The MSB (Most Significant Bit) remains the same as in Gray code.
2. Each subsequent binary bit (B) is obtained by XOR-ing the previous binary
bit with the corresponding Gray code bit.
Truth Table
K-Map Simplification
Logic Diagram
18. Design a control system for a digital clock using logic gates, specifically Ap/CO2
implementing a module that cycles through a sequence from 0 to 4 before resetting,
using JK Flip-flops for synchronization.
(Step 1-3:2 marks, Excitation table with counter: 4 mark, step 6&7 2 mark)
Step 1: N = 5 (goes through states 0 to 4)
Step 2: Number of flip-flops required 2n ≥ N
When n = 3, 23 ≥ 5. So, n = 3
Step 3: Type of flip-flop - JK Flip-flop
Step 4: Excitation table for JK Flip-flop
Present State Next State FF Inputs
Qn Qn + 1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Step 5: Excitation Table for Counter
Cloc
Present State Next State Flip-flop inputs
k
QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 0 1 0 x 0 x 1 x
1 0 0 1 0 1 0 0 x 1 x x 1
2 0 1 0 0 1 1 0 x x 0 1 x
3 0 1 1 1 0 0 1 x x 1 x 1
4 1 0 0 0 0 0 x 1 0 x 0 x
5 1 0 1 x x x x x x x x x
6 1 1 0 x x x x x x x x x
Step 6: K-Map Simplification
Step 6: Logic Diagram
19 Examine the Programmable Logic Array (PLA) implementation for the multiple Ap/CO2
functions F1 through F6 as defined for the variables A, B, and C.
(Explanation: 2 mark, steps:2 mark, logic Diagram 6 mark)
A Programmable Logic Array (PLA) is a type of digital circuit used to implement
combinational logic functions. It consists of:
1. AND Plane: Generates product terms by AND the input variables and their
complements.
2. OR Plane: Combines the generated product terms using OR gates to implement
the desired Boolean functions.
PLAs are flexible and can be programmed to realize multiple logic functions within the
same circuit.
Step 1:Identify Inputs and Outputs
Inputs: A,B,C
Outputs: F1,F2,F3,F4,F5,
Step 2: Generate Required Literals
Each input variable has its complemented form using NOT gates:
Step 3: Implement AND Array
Construct AND gates to generate the required product terms for each function.
Step 4: Implement OR/XOR Array
Use OR gates to sum the required minterms.
Logic Diagram of PLA structure:
Course Instructor Programme Assessment Committee HOD/ECE
Dr.P.Sridhar, AP (Sl.G) Dr.B.Nataraj, Asso.Prof
Mr.K.Rajeswaran, AP(Sr.G)
