Module-2 ( Part-2)

Shift Register
Shift - Registers are capable of shifting their binary information in one or both directions. The
logical configuration of a Shift - Register consists of a series of flip-flops, with the output of
one flip-flop connected to the input of the next flip-flop.
Following are the four types of shift registers based on applying inputs and accessing of
outputs.

• Serial In − Serial Out shift register

• Serial In − Parallel Out shift register
• Parallel In − Serial Out shift register
• Parallel In − Parallel Out shift register

Serial In − Serial Out (SISO Shift Register)

The shift register, which allows serial input and produces serial output is known as Serial In
– Serial Out (SISO) shift register. It is one of the simplest of all the shift registers. The SISO
shift register is constructed with four flip-flops. It has one input, one output and a clock pulse
input. The block diagram is shown below.

Here, the data is inserted at the input bit by bit. For each clock pulse, the data bit is shifted from
one flip-flop to the next flip-flop. At the output side, the inserted data will be received bit by
bit for each clock pulse.
Since the inserted data and the received data are done in a bit by bit fashion, this register is
known as Serial-in Serial-out(SISO) shift register.
The above table summarizes the operation of SISO register, where the shift is done from left
to right. Initially, the output of all the flip-flops is assumed to be logic 0. Consider the data at
the input terminal DIN be 1.
During the first clock pulse, the logic 1 at the input DIN is shifted to the output of the first flip-
flop QA. Similarly, the data input at other flip-flops is also shifted by one position. It is shown
in the third row of the above table.

During the second clock pulse, the logic 1 at the inputs of the first and second flip-flop are
shifted by one position. The logic 0 input at the other inputs of the flip-flop is also shifted by
one position, which is shown in the fourth row of the above table.
This shifting operation continues for each clock pulse. At the end of the fourth clock pulse, the
inserted data bit ‘1’ will be received at the output terminal DOUT.
It is also possible to shift the data from right to left by following the same procedure.

Serial In - Parallel Out (SIPO Shift Register)

The shift register, which allows serial input ad produces parallel output is known as Serial In
– Parallel Out (SIPO shift register). In the Serial-in Parallel-out shift register, the data is
inserted bit by bit serially. The data input at all the flip-flops is shifted by one position for
every clock pulse. The output at each flip-flop can be taken out in a parallel fashion, as shown
in the figure below.
During the clock pulse, the D input of each flip-flop is shifted to the Q output. The Q outputs
of all the flip-flops are tapped separately. Thus the parallel output data(QAQBQCQD) will have

the bit from each individual registers.

This circuit consists of four D flip-flops, which are cascaded. That means, output of one D
flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with
each other since, the same clock signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence,
this input is also called as serial input. For every positive edge triggering of clock signal, the
data shifts from one stage to the next. In this case, we can access the outputs of each D flip-
flop in parallel. So, we will get parallel outputs from this shift register.

Parallel In − Serial Out (PISO Shift Register)

The shift register, which allows parallel input and produces serial output is known as Parallel
In − Serial Out PISO shift register. In this, the data is inserted or loaded into each register
parallelly and the inserted data is received serially at the output.
Here the data is to be loaded at the input of each flip-flop. At the same time, while applying
the clock pulse, the data at the output of each flip-flop will be moved to the input of the next
flip-flop.
So to avoid conflicts between the loaded data and the shifted data at the inputs, the control
input is added in this shift register. It is shown in the below diagram.
This circuit consists of four D flip-flops, which are cascaded. That means, output of one D
flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with
each other since, the same clock signal is applied to each one.
If the control input is 0, the AND gates 1, 3, 5 will be disabled and gates 2, 4, 6 will be enabled.
It will make the parallel data at the inputs(DADBDCDD) to get stored in the respective flip-flops.
For loading the parallel input data, a clock pulse is not required.
When the control input is 1, it will enable the AND gates 1, 3, 5 and the gates 2, 4, 6 will get
disabled. During this time, when a clock pulse is applied, the data bit at the input of each flip-
flop is shifted to its output.
Thus the data is loaded parallelly into the individual registers and upon the application of each
clock pulse, the data is shifted serially. The serial output is obtained from the Q output of the
last flip-flop.

Parallel In - Parallel Out (PIPO Shift Register)

The shift register, which allows parallel input and produces parallel output is known as Parallel
In − Parallel Out (PIPO shift register). In Parallel-in Parallel-out(PIPO) shift register, the input
data is loaded parallelly into each individual registers and the output is received from each flip-
flop output.
It is used for the temporary storage of data or time delay device. The block diagram of PIPO
shift register is shown below.
The four-bit data is loaded at the input of four flip-flops. When a clock pulse is applied, the
loaded data is shifted to the output of the flip-flop, which is tapped for measurements. A single
clock pulse will load the data and unload the data.

Counters

A special type of sequential circuit used to count the pulse is known as a counter, or a collection
of flip flops where the clock signal is applied is known as counters.

The counter is one of the widest applications of the flip flop. Based on the clock pulse, the
output of the counter contains a predefined state. The number of the pulse can be counted using
the output of the counter.

There are the following types of counters:

o Asynchronous Counters
o Synchronous Counters

Asynchronous or ripple counters

The Asynchronous counter is also known as the ripple counter. Below is a diagram of the 2-
bit Asynchronous counter in which we used two T flip-flops. Apart from the T flip flop, we
can also use the JK flip flop by setting both of the inputs to 1 permanently. The external clock
pass to the clock input of the first flip flop, i.e., FF-A and its output, i.e., is passed to clock
input of the next flip flop, i.e., FF-B.
Block Diagram

Signal Diagram

Operation
1. Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will change
from 0 to 1. The output of this flip flop will be taken by the clock input of the next flip
flop. This output will be taken as a positive edge clock by the second flip flop. This
input will not change the second flip flop's output state because it is the negative edge
triggered flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 0 and QB = 1.
 4. Condition 4: When the third negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 0 to 1. This output will be taken as a positive edge clock by the second
flip flop. This input will not change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 1 and QB = 1
5. Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the output state of the second flip flop.
So, QA = 0 and QB = 0

Asynchronous Counters

If the flip-flops do not receive the same clock signal, then that counter is called
as Asynchronous counter. The output of system clock is applied as clock signal only to first
flip-flop. The remaining flip-flops receive the clock signal from output of its previous stage
flip-flop. Hence, the outputs of all flip-flops do not change at the same time.

• Asynchronous up counter
• Asynchronous down counter

Asynchronous Up Counter
An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to
2� − 1. The block diagram of 3-bit Asynchronous binary up counter is shown in the following
figure.
The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-input of all
the flip-flops are connected to ‘1’. All these flip-flops are negative edge triggered but the
outputs change asynchronously. The clock signal is directly applied to the first T flip-flop. So,
the output of first T flip-flop toggles for every negative edge of clock signal.

No of negative edge of Q2MSB Q1 Q0LSB

Clock

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

The output of first T flip-flop is applied as clock signal for second T flip-flop. So, the output
of second T flip-flop toggles for every negative edge of output of first T flip-flop. Similarly,
the output of third T flip-flop toggles for every negative edge of output of second T flip-flop,
since the output of second T flip-flop acts as the clock signal for third T flip-flop.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=000. Here,
Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary counter from the following table.

Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that goes
from 1 to 0, otherwise remained in the previous state. Similarly,Q2 toggled for everyQ1 that
goes from 1 to 0, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0=000. This is
incremented by one for every negative edge of clock signal and reached to maximum value at
7th negative edge of clock signal. This pattern repeats when further negative edges of clock
signal are applied.

Asynchronous Down Counter

An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts from 2� −
1 to 0. The block diagram of 3-bit Asynchronous binary down counter is shown in the
following figure.

The block diagram of 3-bit Asynchronous binary down counter is similar to the block diagram
of 3-bit Asynchronous binary up counter. But, the only difference is that instead of connecting
the normal outputs of one stage flip-flop as clock signal for next stage flip-flop, connect
the complemented outputs of one stage flip-flop as clock signal for next stage flip-flop.
Complemented output goes from 1 to 0 is same as the normal output goes from 0 to 1.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary down counter from the following table.
 No of negative edge of Q2 MSB Q1 Q0LSB
Clock

0 0 0 0

1 1 1 1

2 1 1 0

3 1 0 1

4 1 0 0

5 0 1 1

6 0 1 0

7 0 0 1

Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that goes
from 0 to 1, otherwise remained in the previous state. Similarly, Q2 toggled for every Q1 that
goes from 0 to 1, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0=000. This is
decremented by one for every negative edge of clock signal and reaches to the same value at
8th negative edge of clock signal. This pattern repeats when further negative edges of clock
signal are applied.

Synchronous Counters

If all the flip-flops receive the same clock signal, then that counter is called as Synchronous
counter. Hence, the outputs of all flip-flops change affect at the same time.
The following two counters one by one.
 • Synchronous up counter
• Synchronous down counter

Synchronous Up Counter
An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to 2� −
1. The block diagram of 3-bit Synchronous binary up counter is shown in the following
figure.

The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND gate.
All these flip-flops are negative edge triggered and the outputs of flip-flops change
affect synchronously. The T inputs of first, second and third flip-flops are
1, Q0 & Q1Q0 respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output of
second T flip-flop toggles for every negative edge of clock signal if Q0 is 1. The output of
third T flip-flop toggles for every negative edge of clock signal if both Q0 & Q1 are 1.

Synchronous Down Counter

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-flops. It counts from 2� −
1 to 0. The block diagram of 3-bit Synchronous binary down counter is shown in the
following figure.
The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops
change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0′ &
Q1′ Q0′ respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output of
second T flip-flop toggles for every negative edge of clock signal if Q0′ is 1. The output of
third T flip-flop toggles for every negative edge of clock signal if both Q1′ & Q0′ are 1.

Synchronous counters

In the Asynchronous counter, the present counter's output passes to the input of the next
counter. So, the counters are connected like a chain. The drawback of this system is that it
creates the counting delay, and the propagation delay also occurs during the counting stage.
The synchronous counter is designed to remove this drawback.

In the synchronous counter, the same clock pulse is passed to the clock input of all the flip
flops. The clock signals produced by all the flip flops are the same as each other. Below is the
diagram of a 2-bit synchronous counter in which the inputs of the first flip flop, i.e., FF-A, are
set to 1. So, the first flip flop will work as a toggle flip-flop. The output of the first flip flop is
passed to both the inputs of the next JK flip flop.

Logical Diagram
Signal Diagram

Operation
1. Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
So, QA = 0 and QB = 0
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will be toggled, and the output of this flip flop will be
changed from 0 to 1. When the first negative clock edge is passed, the output of the first
flip flop will be 0. The clock input of the first flip flop and both of its inputs will set to
0. In this way, the state of the second flip flop will remain the same.
So, QA = 1 and QB = 0
3. Condition 2: When the second negative clock edge is passed.
Operation: The first flip flop will be toggled again, and the output of this flip flop will
be changed from 1 to 0. When the second negative clock edge is passed, the output of
the first flip flop will be 1. The clock input of the first flip flop and both of its inputs
will set to 1. In this way, the state of the second flip flop will change from 0 to 1.
So, QA = 0 and QB = 1
4. Condition 2: When the third negative clock edge passes.
Operation: The first flip flop will toggle from 0 to 1, but at this instance, both the
inputs and the clock input set to 0. Hence, the outputs will remain the same as before.
So, QA = 1 and QB = 1
5. Condition 2: When the fourth negative clock edge passes.
Operation: The first flip flop will toggle from 1 to 0. At this instance, the inputs and
the clock input of the second flip flop set to 1. Hence, the outputs will change from 1
to 0.
So, QA = 0 and QB = 0
 Ring Counter

A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The
only difference between the shift register and the ring counter is that the last flip flop outcome
is taken as the output in the shift register. But in the ring counter, this outcome is passed to the
first flip flop as an input. All of the remaining things in the ring counter are the same as the
shift register.

In the Ring counter

No. of states in Ring counter = No. of flip-flop used

Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The same
clock pulse is passed to the clock input of all the flip flops as a synchronous counter.
The Overriding input(ORI) is used to design this circuit.

The Overriding input is used as clear and pre-set.

The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0. Both PR and
CLR always work in value 0 because they are active low signals.

1. PR = 0, Q = 1
2. CLR = 0, Q = 0

These two values(always fixed) are independent with the input D and the Clock pulse (CLK).

Working
 The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed to
the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3. The pre-set input
set to 0 for the first flip flop. So, the output of the first flip flop is one, and the outputs of the
remaining flip flops are 0. The output of the first flip flop is used to form the ring in the ring
counter and referred to as Pre-set 1.

Johnson Counter

The Johnson counter is similar to the Ring counter. The only difference between
the Johnson counter and the ring counter is that the outcome of the last flip flop is passed to
the first flip flop as an input. But in Johnson counter, the inverted outcome Q' of the last flip
flop is passed as an input. The remaining work of the Johnson counter is the same as a ring
counter. The Johnson counter is also referred to as the Creeping counter.

In Johnson counter

1. No. of states in Johnson counter = No. of flip-flop used

2. Number of used states=2n
3. Number of unused states=2n - 2*n

Below is the diagram of the 4-bit Johnson counter. Like Ring counter, four D flip flops are
used in the 4-bit Johnson counter, and the same clock pulse is passed to all the input of the flip
flops.

Truth Table
CP Q1 Q2 Q3 Q4
 0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 1 1 1

Advantages
o The number of flip flops in the Johnson counter is equal to the number of flip flops in
the ring counter, and the Johnson counter counts twice the number of states the ring
counter can count.
o The Johnson counter can also be designed by using D or JK flip flop.
o The data is count in a continuous loop in the Johnson ring counter.
o The circuit of the Johnson counter is self-decoding.

Disadvantages
o The Johnson counter is not able to count the states in a binary sequence.
o In the Johnson counter, the unutilized states are greater than the states being utilized.
o The number of flip flops is equal to one half of the number of timing signals.
o It is possible to design the Johnson counter for any number of timing sequences.

Decade Counter

A decade counter requires resetting to zero when the output count reaches the decimal value of
10, ie. when Q3Q2Q1Q0= 1010 and to do this we need to feed this condition back to the reset
input. A counter with a count sequence from binary “0000” (BCD = “0”) through to “1001”
(BCD = “9”) is generally referred to as a BCD binary-coded-decimal counter because its ten
state sequence is that of a BCD code but binary decade counters are more common.

Decade Counter Truth Table

Output bit Pattern

Clock Decimal
Count Value

Q3 Q2 Q1 Q0

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3
5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram

Mod-N counter

Design for Mod-N counter :

The steps for the design are –

Step 1 : Decision for number of flip-flops –

Example : If we are designing mod N counter and n number of flip-flops are
required then n can be found out by this equation.

N <= 2n

Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip

flops(n) required is
For n =3, 10<=8, which is false.
For n= 4,10<=16, which is true.
Therefore number of FF required is 4 for Mod-10 counter.

Step 2 : Write excitation table of Flip flops –

Here T FF is used
 Excitation table of T FF.

Step 3 : Draw state diagram and circuit excitation table –

Counting Sequence of Decade counter

A decade counter is called as mod -10 or divide by 10 counter. It counts from 0 to 9 and
again reset to 0. It counts in natural binary sequence. Here 4 T Flip flops are used. It resets
after Q3 Q2 Q1 Q0 = 1001.

Circuit excitation table –

Here Q3 Q2 Q1 Q0 are present states of four flip-flops and Q*3 Q*2 Q*1 Q*0 are next counting
state of 4 Flip flops. If there is a transition in current state i.e if Q3 value changes from 0 to 1
or 1 to 0 then there’s corresponding T(toggle) bit is written as 1 otherwise 0.
 Circuit excitation table.

Step 4 : Create Karnaugh map for each FF input in terms of flip-flop

outputs as the input variable –
Simplify the K map –

K map for finding minimal expressions.

Step 5 : Create circuit diagram –

Here negative edge triggered clock is used for toggling purpose.
• The clock is provided to every Flip flop at same instant of time.
• The toggle(T) input is provided to every Flip flop according to the simplified equation of
K map.
 Circuit diagram

Timing diagram : Here toggling is used.

Characteristic table of T FF.

The state of a FF will change only when toggle input(T) of a FF is 1.

 Timing diagram of synchronous Decade counter

Explanation :
• Initially Q3 Q2 Q1 Q0 are 0 0 0 0.
• The sequence of counter can be verified from the timing diagram. At every falling edge of
the clock output Q0 toggles because T0 is connected to logic 1.
• T1 becomes 1 only when expression T1 = Q’3Q0 becomes 1 also if clock falling edge
occurs(because there is negative edge triggering) then the output state of T1 i.e Q1 will
change.
• T2 becomes 1 only when expression T2 = Q1Q0 becomes 1 also if clock falling edge
occurs then the output state Q2 will change.
• T3 becomes 1 only when expression T1 = Q3Q0 + Q2Q1Q0 resultant becomes 1 also if
clock falling edge occurs(because there is negative edge triggering) then the state of Q3
will change.
• We get Output as Q3(MSB) Q2 Q1 Q0(LSB).
• After 10th falling edge the output state of all the FFs again becomes 0 0 0 0.