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USN: 22ECt602
Dr. Ambedkar Institute of Technology
Sixth Semester B. E. Degree (Autonomous) Semester End Examination (SEE), July 2025
Model Question Paper
CMOS VLSI Design
Time: 3 Hours Maximum Marks: 100
Instructions to the Candidates
1. Answer FIVE FULL Questions
Marks CO RBT
level
1. a. Mention the various factors that influence the level of Drain Current IDS 04 M CO1 L2
flowing between Source and Drain.
b. Calculate the native threshold voltage for an n-transistor at 300K for a 04 M CO1 L3
process with Silicon substrate with NA = 1.80 x 1016, a SiO2 gate oxide with
thickness 200Ao. Assume φms = -0.9V , Qfc = 0;
c. Illustrate Voltage Transfer Characteristics of CMOS Inverter by specifying 12 M CO1 L3
different regions of operation. Explain the states of pMOS and nMOS in
each region.
OR
2. a. Describe the effect of scaling on 08 M CO1 L2
i) Gate Area Ag
ii) Gate Capacitance Cg
iii) Current Density J
iv) Maximum Operating Frequency fo
b. Explain the following Second Order Effects 08 M CO1 L2
i) Threshold Voltage – body Effect
ii) Channel Length Modulation
c. Compare nMOS Pass Transistor and pMOS Pass Transistor. 04 M CO1 L2
3. a. Draw the stick diagram of 4:1 NMOS inverter and p-well CMOS Inverter. 08 M CO2 L3
b. Briefly explain design rules for wires (nMOS and CMOS) 08 M CO2 L2
c Draw the stick diagram for n-well based BiCMOS inverter. 04 M CO2 L3
OR
4. a. Define Sheet Resistance. Using uniform slab of conduction material derive 08 M CO2 L1,2
its expression. Mention Rs value for Metal, n-transistor channel for 5um
technology.
b. Derive the expression for Rise time and Fall time for CMOS Inverter Delay. 08 M CO2 L4
Dr. Ambedkar Institute of Technology, Bangalore – 560056
(An Autonomous Institution Affiliated to Visvesvaraya Technological University, Belgaum)
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c. For 2um MOS circuits, obtain the standard value of Capacitance Cg. Given, 04 M CO2 L3
Gate capacitance value = 8 x 10-4 pF/um2
5. a. Draw the schematic diagram for the given Boolean expression using CMOS 10 M CO3 L3
Logic and analyze working for any one combination of input.
i) Y = A + (B C)
ii) Y = A (B + C) + (D E)
b. Sketch the schematic diagram of 4:1 mux using Pass Transistor Logic. Also 10 M CO3 L3
draw its truth table and logical expression.
OR
6. a. Draw the schematic diagram for the given Boolean expression using 10 M CO3 L3
dynamic CMOS Logic and analyze working for any one combination of
input.
i) Y = (A + B)
ii) Y = A.B
b. Describe Cascade Voltage Switch Logic (CVSL). Also Draw schematic 10 M CO3 L2
diagram for the given Boolean expression
Y = X (Y + Z)
7. a. With expressions and truth table, sketch the schematic diagram of CMOS 10 M CO4 L3
full adder using 28 transistors.
b. Describe Carry skip adder with neat block diagram and mention the delay 10 M CO4 L2
associated with it.
OR
8. a. Given two signed numbers A = 110101 and B = 011011, perform 10 M CO4 L3
multiplication using Booths Algorithm.
b. Describe 4 x 4 Array Multiplier for unsigned numbers using an array of 10 M CO4 L2
Carry Save Adders.
9. a Draw the schematic diagram of CMOS SR latch circuit based on NOR2 Gates and 10 M CO5 L3
explain the working principle.
b. Using NAND2 Gates, sketch the schematic diagram of CMOS SR latch and explain 10 M CO5 L3
the working principle.
OR
10. a. Describe with neat diagram and waveforms CMOS negative edge-triggered 10 M CO5 L2
master slave D flip flop
b. Describe CMOS implementation of D-latch with neat diagram and 10 M CO5 L2
waveforms.
Dr. Ambedkar Institute of Technology, Bangalore – 560056
(An Autonomous Institution Affiliated to Visvesvaraya Technological University, Belgaum)
