PHYSICAL DESIGN AND VERIFICATION

INDUSTRY INTERNSHIP REPORT

Submitted to

Visvesvaraya Technological University

Belagavi-590018

By
Akash A
4SU21EC003

Under the guidance of

Dr. Avinash S
Associate Professor

in partial fulfillment of the requirements for the award of the degree of

Bachelor of Engineering

Department of Electronics & Communication Engineering

SDM INSTITUTE OF TECHNOLOGY

UJIRE-574240
2024-2025
 `

SDMINSTITUTE OF TECHNOLOGY
(Affiliated to Visvesvaraya Technological University, Belagavi)
UJIRE – 574 240

Department of Electronics and Communication Engineering

CERTIFICATE

Certified that the Internship Report titled ‘Physical Design and

Verification’ is carried out by Mr. Akash A, USN: 4SU21EC003, a bona-
fide student of SDM Institute of Technology, Ujire, at Teloquence Pvt. Ltd,
Manipal in partial fulfillment for the award of the degree of Bachelor of
Engineering in Electronics and Communication Engineering of
Visvesvaraya Technological University, Belagavi during the year 2024-
2025. It is certified that all the corrections/ suggestions indicated for Internal
Assessment have been incorporated in the report deposited in the
departmental library. The report has been approved as it satisfies the
academic requirements in respect of Internship prescribed for the said
Degree.

Dr. Avinash S Dr. Madhusudhana K Dr. Ashok Kumar T

Faculty Advisor Head of the Department Principal

External Viva

Name of the Examiners: Signature with Date

1.

2.
 Acknowledgement

I express my deepest gratitude to my guide Mr. Praveen Gore, Director of Teloquence Private
Limited, Manipal, for his valuable guidance and encouragement while doing my internship. I
also extend my heartfelt thanks to Mr. Anand Yaligar, Director and CEO for having given me
the opportunity of carrying out internship at Teloquence Private Limited, Manipal.

We are indebted to Dr. Madusudhana K, Head of the Department, Internship Co-ordinators

Mr. Ramachandra Asst. Prof. and Mr. Mahesh D S, Asst. Prof. for their advice and
suggestions at various stages of the work.

I am grateful to Dr. Avinash S, Assoc. Prof, Dept. of ECE for correcting the internship report.

I am also grateful to the cooperation and help rendered by the teaching and non-teaching staff
of the department.

Akash A
USN:4SU21EC003

i
 Table of Contents
Page No.
Acknowledgement i
Table of Contents ii
List of Figures iii
List of Tables iv
List of Acronyms and Abbreviations v
1 Executive Summary 1
2 Company Profile 2
3 Problem Statement and Objectives 3
3.1 Problem Statement
3.2 Objectives
4 Weekly Overview of The Internship 4
5 Training Outline 7
5.1 Introduction 7
5.2 Complementary Metal-Oxide-Semiconductor (CMOS) 8
5.3 ASIC design flow 9
5.4 UNIX and TCL commands 11
5.5 Physical Design Overview 12
5.6 RISC V 5- Stage Pipeline 14
5.7 FIFO Design and Verification 16
6 Testing and Result Analysis 18
6.1 Test result
7 Discussion 24
7.1 Common faults observed 24
7.2 Causes and remedies 24
8 Conclusion 25
8.1 Outcome of the internship 25
8.2 Scope of the future work 25
9 SWOT analysis 26
Bibliography 27
Appendix

ii
 List of Figures

Page No.

Figure 5.1 CMOS structure 8

Figure 5.2 ASIC flow diagram 9
Figure 5.3 Physical design flow 12

Figure 5.4 Logic diagram of Memory access 15

Figure 5.5 Logic diagram of Writeback stage 16
Figure 6.1 Simulation waveform of Memory access 18
Figure 6.2 Simulation waveform of Writeback stage 18
Figure 6.3 Area report of Writeback stage 19

Figure 6.4 Timing report of Writeback stage 19

Figure 6.5 Gate-level netlist 20

Figure 6.6 Complete PnR of Writeback stage 22
Figure 6.7 Complete PnR of Memory access 22
Figure 6.8 Result of design verification 23

iii
 List of Tables

Page No.
Table 4.1 Weekly overview of internship 4
Table 5.1 Basic commands in Linux 11
Table 6.1 Area of each block 20

iv
 List of Acronyms and Abbreviations

VLSI Very Large-Scale Integration

IC Integrated circuit
SSI Small Scale Integration
MSI Medium Scale Integration
LSI Large Scale Integration
USLI Ultra Large-Scale Integration
SRAM Static Random Access Memory
CMOS Complementary Metal–Oxide–Semiconductor
MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor
TTL Transistor–Transistor Logic
RTL Register Transfer Level
GDS Graphic Data Stream
LEC Logic Equivalence Check
SDC Synopsys Design Constraint
DFT Design For Testability
MMMC Multi-mode multi corner
VR Virtual Route
PVT Process Voltage Temperature
RC Resistance Capacitance

v
 Chapter 1
Executive Summary
The 15-week internship conducted from March 17 2025 to May 31 2025, provided
comprehensive exposure to the complete ASIC design and verification flow, with a focus
on both front-end and back-end VLSI processes. The training encompassed key areas
including RTL design using SystemVerilog, functional verification, logic synthesis, static
timing analysis, and physical implementation. A major component of the internship was
the end-to-end design and physical realization of a 5-stage pipelined RISC-V processor,
leveraging Cadence’s industry-standard digital design tool suite Genus for RTL synthesis,
Innovus for physical design stages (floorplanning, placement, CTS, and routing), and
Tempus for static timing analysis.

The design flow commenced with RTL development and module-level simulation of the
processor pipeline stages, followed by synthesis into a gate-level netlist with optimization
for area, timing, and power. Floorplanning activities included defining the die area, power
grid creation, IO pin assignment, and macro placement. Power planning was performed
using multi- voltage domains and power stripes to ensure efficient power delivery and IR
drop minimization. Placement involved standard cell positioning while addressing
congestion and timing critical paths. Clock Tree Synthesis (CTS) was executed to
construct an optimized clock distribution network with minimal skew and latency,
followed by global and detailed routing with metal layer optimization and Design Rule
Check (DRC) validation.

Static Timing Analysis (STA) was conducted post-synthesis and post-routing to analyze
setup, hold, and clock uncertainty issues using Tempus, and appropriate Engineering
Change Orders (ECOs) were applied where needed. The design was constrained using
SDC (Synopsys Design Constraints) files to define clock, input/output delays, and
multicycle paths. Detailed timing and power reports were analyzed to ensure that the final
design met the performance requirements. This internship provided hands-on experience
with the RTL- to-GDSII flow, bridging the gap between theoretical knowledge and
industrial practice, and enabled the application of advanced physical design concepts such
as floorplan optimization, congestion mitigation, timing closure strategies, and sign-off
checks, contributing to the design of high-performance, silicon-ready.

1
 Chapter 2
Company Profile
Company Name: Teloquence Private Limited, Manipal

Teloquence Private Limited is a boot-strapped semiconductor services organization

founded by Anand Yaligar and Sunitha Tirlapur Karnataka, India. The roots of
Teloquence were sown in 2018 when the two founders, who come with rich experience
working with companies such as Texas Instrumentation realized they shared a common
dream of building a world-class semiconductor services company.

Since 2019, the company has provided design services several semiconductor gains in the
field of AMS verification, Analog Layout, PDK, and embedded services. Teloquence is a
fast-growing semiconductor service company and is well-positioned to take advantage of
the Semiconductor boom that is currently happening in India and across the globe.

The team has excellent experience in solving some of the most complex SOC
implementation challenges. They not only emphasize the technical aspect of the team but
they also make sure that they have the right work culture inside the company which
motivates the team and helps to deliver high-quality design services. One of the key
features of the Teloquence service model is in-house training. They hire the right talent
with the right attitude from college and train them and make the industry ready.

2
 Chapter 3
Problem Statement and Objectives
3.1 Problem statement

To design and implement the Memory Access and Writeback stages of a modular 5-stage
pipelined RISC-V processor, ensuring accurate data handling, seamless integration with
preceding pipeline stages, and maintaining efficient pipeline operation with clear block-
wise division for enhanced debugging and scalability.

3.2 Objectives

i. To design the Memory Access and Writeback stages of a 5-stage pipelined RISC-V
processor as part of a modular architecture divided into 9 functional blocks.
ii. To ensure correct instruction execution during the memory and writeback phases,
with efficient handling of pipeline hazards and smooth data flow between all stage.

3
 Chapter 4

Weekly Overview of Internship

Week Date Day Task assigned Task completed
17 Feb 2025 Monday Assignments on basic digital Assignments submitted on time
electronics
18 Feb 2025 Tuesday Assignments on basic digital Assignments submitted on time
electronics
Week 1
19 Feb 2025 Wednesday Assignments on basic digital Assignments submitted on time
electronics
20 Feb 2025 Thursday Assignments on basic digital Assignments submitted on time
electronics
21 Feb 2025 Friday Assignments on basic digital Assignments submitted on time
electronics
22 Feb 2025 Saturday Assignments on basic digital Assignments submitted on time
electronics
24 Feb 2025 Monday Assignments on basic analog Assignments submitted on time
electronics
25 Feb 2025 Tuesday Assignments on basic analog Assignments submitted on time
electronics
Week 2
26 Feb 2025 Wednesday Assignments on basic analog Assignments submitted on time
electronics
27 Feb 2025 Thursday Assignments on basic analog Assignments submitted on time
electronics
28 Feb 2025 Friday Assignments on basic analog Assignments submitted on time
electronics
1 Mar 2025 Saturday Assignments on basic analog Assignments submitted on time
electronics
Solving problem statements based on
3 Mar 2025 Monday Solved
Linux and TCL commands
Solving problem statements based on
4 Mar 2025 Tuesday Solved
Linux and TCL commands
Solving problem statements based on
5 Mar 2025 Wednesday Solved
Linux and TCL commands
Week 3
Solving problem statements based on
6 Mar 2025 Thursday Solved
Linux and TCL commands
Solving problem statements based on
7 Mar 2025 Friday Solved
Linux and TCL commands
Solving problem statements based on
8 Mar 2025 Saturday Solved
Linux and TCL commands
Designing RTL for Memory access
10 Mar 2025 Monday block code completed

Designing RTL for Memory access

11 Mar 2025 Tuesday block code completed

Designing RTL for Memory access

12 Mar 2025 Wednesday block code completed
Week 4
Designing RTL for Memory access
13 Mar 2025 Thursday block code completed

4
 Designing RTL for Memory access
14 Mar 2025 Friday block code completed

Designing RTL for Memory access

15 Mar 2025 Saturday block code completed

Designing RTL for Writeback stage

17 Mar 2025 Monday block code completed
Week 5
Designing RTL for Writeback stage
18 Mar 2025 Tuesday block code completed

Designing RTL for Writeback stage

19 Mar 2025 Wednesday Simulation

Designing RTL for Writeback stage

20 Mar 2025 Thursday Debugging

Designing RTL for Writeback stage

21 Mar 2025 Friday Debugging

Designing RTL for Writeback stage

22 Mar 2025 Saturday Debugging

Designing RTL for Writeback stage

24 Mar 2025 Monday Simulation successful

Designing RTL for Writeback stage

25 Mar 2025 Tuesday Synthesis

Designing RTL for Writeback stage

26 Mar 2025 Wednesday Debugging
Week 6
Designing RTL for Writeback stage
27 Mar 2025 Thursday Debugging

Designing RTL for Writeback stage

28 Mar 2025 Friday Synthesis successful

Designing RTL for Writeback stage

29 Mar 2025 Saturday Generating reports

31 Mar 2025 Monday Floorplanning Trying different combinations

1 Apr 2025 Tuesday Floorplanning Trying different combinations
2 Apr 2025 Wednesday Floorplanning Trying different combinations
Week 7
3 Apr 2025 Thursday Floorplanning Trying different combinations
4 Apr 2025 Friday Floorplanning Trying different combinations
5 Apr 2025 Saturday Floorplanning Trying different combinations
7 Apr 2025 Monday Deciding Pin location of each block Ongoing
8 Apr 2025 Tuesday Deciding Pin location of each block Ongoing
9 Apr 2025 Wednesday Deciding Pin location of each block Done
Week 8
10 Apr 2025 Thursday Generating .lef files Executing TCL command
11 Apr 2025 Friday Generating .lef files Executing TCL command
12 Apr 2025 Saturday Generating .lef files Done
14 Apr 2025 Monday Assignments on Floorplanning Done
15 Apr 2025 Tuesday Assignments on Floorplanning Done
16 Apr 2025 Wednesday Assignments on Floorplanning Done
Week 9
17 Apr 2025 Thursday Assignments on Floorplanning Done
18 Apr 2025 Friday Assignments on Floorplanning Done
19 Apr 2025 Saturday Generation of .lib files Ongoing

5
 21 Apr 2025 Monday Generation of .lib files Done
22 Apr 2025 Tuesday Placement Ongoing
Week 10
23 Apr 2025 Wednesday Placement Done
24 Apr 2025 Thursday Optimizing Floorpalnning Ongoing

25 Apr 2025 Friday Optimizing Floorpalnning Done

26 Apr 2025 Saturday CTS Ongoing
28 Apr 2025 Monday CTS Done
29 Apr 2025 Tuesday Optimizing CTS Done
30 Apr 2025 Wednesday Routing Ongoing
Week 11
1 May 2025 Thursday Routing
2 May 2025 Friday Routing Done
3 May 2025 Saturday Generating GDS Done
5 May 2025 Monday Basics of state machines Done
6 May 2025 Tuesday FSM Done
7 May 2025 Wednesday Introduction to digital verification Done
Week 12
8 May 2025 Thursday Interface Done
9 May 2025 Friday Array and its types Done
10 May 2025 Saturday Array and array methods hands-on Done
12 May 2025 Monday Interface Done
13 May 2025 Tuesday Oops Done
14 May 2025 Wednesday Constraints Done
Week 13
15 May 2025 Thursday Threads Done
16 May 2025 Friday Verification processes Done
17 May 2025 Saturday FIFO -project Ongoing
19 May 2025 Monday FIFO -project Ongoing
20 May 2025 Tuesday FIFO -project Ongoing
21 May 2025 Wednesday FIFO -project Done
Week 14
22 May 2025 Thursday GDSII of Memory access Ongoing
23 May 2025 Friday GDSII of Memory access Ongoing
24 May 2025 Saturday GDSII of Writeback stage Done
26 May 2025 Monday Optimization methods Ongoing
27 May 2025 Tuesday Optimization methods Done
28 May 2025 Wednesday ECO Ongoing
Week 15
29 May 2025 Thursday ECO Done
30 May 2025 Friday Sign off Ongoing
31 May 2025 Saturday Sign off Done
Table 4.1: Weekly overview of internship

6
7
 Chapter 5
Training Outline
5.1 Introduction
VLSI (Very Large-Scale Integration) technology has revolutionized the electronics
industry by enabling millions to billions of transistors to be integrated into a single silicon
chip. This integration allows the creation of highly complex digital circuits such as
microprocessors, memory devices, and system-on-chips (SoCs). However, designing
these chips involves a sophisticated and multi-step process to ensure the final product
meets stringent requirements in terms of performance, power consumption, area, and
reliability.

Physical design and verification constitute a crucial phase in the VLSI design flow that
bridges the gap between the logical design and the manufacturable silicon layout. Starting
from a gate-level netlist obtained after logic synthesis, physical design translates this
abstract representation into a detailed geometrical description that specifies the exact
placement of transistors and routing of interconnections on the chip.

This process involves several interdependent steps. Initially, floorplanning sets the
foundation by defining the chip’s overall dimensions, determining the placement of major
blocks or macros, and designing the power grid to supply stable voltage to all
components. This phase directly influences the chip’s area efficiency, timing, and power
distribution. Following floorplanning, placement algorithms assign exact positions to
standard cells within the defined floorplan, aiming to optimize wirelength, reduce signal
delay, and minimize congestion. Precise placement is essential to achieve the desired
operating frequency and power targets.

The next critical step, clock tree synthesis (CTS), creates a balanced clock distribution
network to ensure that the clock signal arrives simultaneously (or with minimal skew) at
all sequential elements, which is vital for correct timing and synchronization across the
chip. After CTS, routing connects all the placed cells by creating metal interconnections
across multiple metal layers, ensuring that signals can travel between cells without
violating the foundry’s strict manufacturing design rules.

8
Throughout and after these steps, physical verification is performed to confirm that the
layout complies with manufacturing constraints and matches the original logical design.
The Design Rule Check (DRC) ensures that the layout geometry adheres to the foundry’s
rules such as minimum widths, spacing, and overlaps, which are critical to avoid defects
during fabrication. The Layout Versus Schematic (LVS) check verifies that the netlist
extracted from the layout corresponds exactly to the intended circuit schematic,
guaranteeing functional correctness. Additionally, advanced checks like antenna effects
and electromigration assessments help prevent reliability issues during the chip’s
operational life. Physical design and verification are indispensable because even a
logically correct design may fail to perform as intended if the physical implementation
does not meet these constraints. A well-executed physical design optimizes performance,
reduces power consumption, minimizes area, and ensures manufacturability and
reliability, all of which are essential for the successful production of modern integrated
circuits.

5.2 Complementary Metal–Oxide–Semiconductor (CMOS)

Figure 5.1: CMOS structure

CMOS is a type of Metal Oxide Semiconductor field-effect transistor (MOSFET)

fabrication process that uses complementary and symmetrical pairs of p-type and n- type
MOSFETs for logic functions. CMOS technology is used for constructing integrated
circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including
CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog
circuits such as image sensors (CMOS sensors), data converters,

Two important characteristics of CMOS devices are high noise immunity and low static
power consumption. Since one transistor of the MOSFET pair is always off, the series
combination draws significant power only momentarily during switching between on and
off states. Consequently, CMOS devices do not produce as much waste heat as other

9
forms of logic, like NMOS logic or transistor–transistor logic (TTL), which normally
have some

10
standing current even when not changing state. These characteristics allow CMOS to
integrate a high density of logic functions on a chip. It was primarily for this reason that
CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOS

field-effect transistors, having a metal gate electrode placed on top of an oxide insulator,
which in turn is on top of a semiconductor material. Aluminium was once used but now
the material is polysilicon. Other metal gates have made a comeback with the advent of
highκ dielectric materials in the CMOS process, as announced by IBM and Intel for the
45- nanometer node and smaller sizes.

5.3 ASIC Design Flow

Figure 5.2: ASIC flow diagram

Very Large Scale Integration (VLSI) is the process of fabricating integrated circuits by
combining millions of transistors and other components such as resistors and capacitors
onto a single silicon chip. It enables the creation of compact, efficient, and high-
performance electronic systems. Designing a VLSI chip is an iterative and multi-step
process involving functional, logic, circuit, and physical design. At each step, simulation
and verification are crucial to ensure the correctness of the design. If errors are detected,

11
designers may need to revisit and revise earlier stages. The VLSI design flow is generally
categorized into two major parts: Front-End Design and Back-End Design.

Front-End Design begins with the system specifications provided by the customer. These
specifications describe the required functionality, performance, and interfacing of the
chip. Based on these, RTL (Register Transfer Level) engineers write the design using
hardware description languages such as Verilog or VHDL. The RTL code describes the
behavior and data flow within the chip. Once the RTL is complete, it undergoes
simulation to verify its functionality. If the verification team confirms that the design is
bug-free, the RTL is passed on to the synthesis stage. This marks the transition from high-
level design to a more hardware-specific gate-level representation, initiating the RTL to
GDS (RTL2GDS) flow.

Back-End Design deals with converting the technology-independent RTL code into a
layout that can be physically fabricated. The first step is Logic Synthesis, which
transforms RTL into a gate-level netlist using a specific standard cell library and design
constraints. This step also includes Design for Testability (DFT) insertion to ensure the
fabricated chip can be tested effectively. A Logic Equivalence Check (LEC) is performed
to verify that the synthesized logic is functionally equivalent to the original RTL. Reports
on timing, area, and power are generated, and an SDC (Synopsys Design Constraints) file
is created to guide further physical design steps.

System Specification and Architectural Design are foundational stages where the
performance targets, cost, and overall functionality of the chip are defined. In the
architectural phase, high-level decisions such as analog/digital block integration, memory
hierarchy, and power requirements are finalized. After this, Floorplanning determines the
size and placement of functional blocks and allocates resources such as power grids and
I/O pins. This is followed by Placement, where individual standard cells are positioned
considering timing and connectivity.

Finally, Routing connects these cells using metal layers to create signal paths. Routing
must satisfy several constraints, including timing, capacitance, resistance, and DRC
(Design Rule Check) requirements. After layout is complete, the chip undergoes Post-
Silicon Validation, where real silicon is tested in actual operating environments to ensure
it performs correctly under all specified conditions.

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5.4 UNIX and TCL Commands

Linux is a Unix-like computer operating system assembled under the model of free and
open-source software development and distribution. The defining component of Linux is
the Linux kernel, an operating system kernel first released on 5 October 1991 by Linus
Torvalds. Linux was originally developed as a free operating system for Intel x86-based
personal computers. It has since been ported to more computer hardware platforms than
any other operating system. It is a leading operating system on servers and other big iron
systems, such as mainframe computers and supercomputers more than 90% of today's 500
fastest supercomputers run some variant of Linux, including the 10 fastest. Linux also
runs on embedded systems (devices where the operating system is typically built into the
firmware and highly tailored to the system) such as mobile phones, tablet computers,
network routers, televisions and video game consoles; the Android system in wide use on
mobile devices is built on the Linux kernel.

Command Description

pwd Print the name of the present working directory

ls List the contents of the current working directory

cd Change the current working directory

mkdir Create a new directory

man Display the manual for a given program

mv Move or rename a file

cp Copy a file

chmod Change the permission of a file

rm Remove a file forever

more Display the contents of a text file, page by page

find Search through directories, find files

df, du Check how much space is left on disks

grep Search for a pattern in a file or multiple files

Table 5.1: Basic commands in Linux

13
TCL (Tool Command Language) is a high-level, interpreted scripting language developed
by John Ousterhout in the late 1980s at the University of California, Berkeley. Originally
designed to provide a simple yet powerful way for applications to communicate and be
extended, TCL has grown into a versatile language used for a wide range of programming
tasks. Its syntax is straightforward to learn, making it accessible for beginners, while its
flexibility and extensibility appeal to experienced developers. TCL is platform-
independent, running seamlessly on Windows, Mac OS, and virtually all Unix/Linux
systems. One of TCL’s most notable features is its ability to be embedded into other
applications, allowing developers to add scripting capabilities to their software.
Additionally, when paired with the Tk toolkit, TCL becomes a robust tool for building
cross-platform graphical user interfaces (GUIs).

5.5 Physical Design Overview

Figure 5.3: Physical design flow

14
The Physical Design (PD) flow in VLSI refers to the process of converting a synthesized
RTL (Register Transfer Level) design—represented by a gate-level netlist—into a
geometric layout that can be manufactured on a silicon wafer. It bridges the gap between
digital logic and actual chip fabrication. This phase is crucial for translating the abstract
logic design into a real-world implementation that meets timing, power, area, and
manufacturing constraints. The PD flow involves various steps starting from
floorplanning and continuing through placement, clock tree synthesis (CTS), routing, and
ending with physical verification and tapeout. Each step in the flow contributes to
optimizing performance, reducing power consumption, improving area utilization, and
ensuring that the layout complies with design and manufacturing rules.

The flow begins with the import of essential files such as the SDC (timing constraints),
UPF (power intent), LEF/DEF (abstract and placement data), Liberty (.lib) files (cell
timing and power information), and the technology file (design rules and layer
information). Partitioning is then performed for hierarchical or large designs to divide the
system into smaller, manageable blocks, which simplifies design closure and allows
parallel development. Floorplanning defines the chip outline, places large macros and
memory blocks, allocates standard cell areas, and establishes the foundation for power
planning and signal flow. It’s also where the I/O pad ring and power grid topology are
defined. Once floorplanning is complete, placement tools arrange standard cells in rows
within their designated areas, optimizing wirelength, minimizing congestion, and
preparing the layout for timing closure and routing.

After placement, Clock Tree Synthesis (CTS) is performed. This step creates a balanced
tree structure to distribute the clock signal evenly across all sequential elements (like flip-
flops and registers) with minimal skew and controlled latency. CTS often involves buffer
insertion, clock gating, and balancing paths to ensure synchronous operation. The routing
phase follows, connecting all the logical nets using available metal layers. Routing occurs
in two phases: global routing, which outlines approximate paths to minimize congestion,
and detailed routing, which finalizes wire paths and adds vias. It’s essential that routing
adheres to DRC (Design Rule Check) constraints and minimizes parasitic effects like
resistance and capacitance, which can degrade signal integrity and timing.

After routing, further optimization is performed to resolve signal integrity issues such as
crosstalk, antenna effects, excessive delay, or via resistance. Techniques like buffer
insertion, shielding, wire spreading, and layer reassignment are used. Timing closure is a

15
critical, iterative process that ensures all data paths meet setup and hold time requirements
under worst-case conditions. Static Timing Analysis (STA) is applied extensively at this
stage, supported by techniques such as logic restructuring, gate sizing, and placement
adjustments. Simultaneously, power integrity is verified through checks like IR drop
analysis (ensuring sufficient voltage across the chip) and electromigration analysis
(ensuring wires can handle current densities without failure). These checks are vital for
reliable, long-term operation of the chip.

Before a design can be sent for fabrication, it must undergo rigorous physical verification.
This includes DRC (ensuring geometry complies with foundry rules), LVS (ensuring the
layout is logically equivalent to the schematic or netlist), and ERC (checking for electrical
violations such as floating pins or missing connections). These checks are automated
using physical verification tools and are essential for guaranteeing that the design will
work correctly and yield well in silicon. Once verification is complete and all violations
are resolved, the final layout is converted into a GDSII (or OASIS) file, the standard
format used by foundries. This process is called tapeout. The GDSII file is then handed
over to the fabrication facility, where masks are generated, and the silicon wafer
fabrication process begins. A successful tapeout marks the end of the physical design
phase and the beginning of silicon production.

5.6 RISC V 5- Stage Pipeline

A RISC-V processor is a type of CPU that implements the RISC-V (Reduced Instruction
Set Computer - Five) instruction set architecture, which is open-source, modular, and
designed for simplicity and scalability. Unlike proprietary ISAs like x86 or ARM, RISC-
V is free to use, allowing developers and companies to build custom processors without
licensing fees. Its clean and minimalist design makes it easy to implement, verify, and
modify, making it ideal for a wide range of applications, from small embedded devices to
high-performance computing systems. RISC-V processors are increasingly used in
education, research, and industry due to their flexibility, openness, and growing
ecosystem.

The 5-stage pipeline in a RISC-V(32-bit) processor is a common design that divides the
execution of instructions into five distinct stages. This approach improves performance by
allowing multiple instructions to be processed simultaneously at different stages of
completion. Two Clock sources (clk1, clk2) are used for consecutive stages. They are

16
non- overlapped to take care of variable delays like clocks skew, there is also a gap in
between

17
them where both clocks are Low. This is a very safe kind of clocking scheme where we
have non-overlapping clocks with a safe margin in between. Prevents metastable
conditions. The five stages are:

i. Instruction Fetch (IF)

ii. Instruction Decode (ID)
iii. Instruction Execution (EX)
iv. Memory Access (MEM)
v. Write Back (WB)
The blocks that were decided for the design were:
Memory access: The Memory Access stage handles interaction with the data memory.
For load instructions, this stage reads data from the memory address computed in the
Execute stage. For Store instructions, it writes the value from a register into the computed
memory address. If the instruction does not involve memory (e.g., an arithmetic
operation), this stage simply passes the ALU result forward.

Figure 5.4: Logic diagram of Memory access

Writeback stage: In the Write Back stage, the final result of the instruction is written
into the destination register in the register file. This result could be the output from the
ALU (in case of arithmetic/logical instructions) or data loaded from memory (in case of
Load instructions). Store and branch instructions do not write back to the register file, so
no action is taken in this stage for them. Proper synchronization ensures that the correct
data is written at the right time, and that the result is not overwritten by other operations.
This stage completes the instruction cycle and ensures that the output of computations is
made available for future instructions.

18
 Figure 5.5: Logic diagram of Writeback stage

5.7 FIFO Design and Verification

A FIFO (First-In First-Out) buffer is a fundamental component in digital systems,

primarily used for temporary data storage between two subsystems that operate at the
same or different clock domains. The main principle of FIFO is that the data which enters
first is the data that exits first, maintaining a strict order of processing. In the given design
(FIFO.v), a synchronous FIFO is implemented using Verilog, which includes key
components like a memory array, read and write pointers, and control logic to handle full
and empty conditions. The design is parameterized for depth and data width, enabling
customization for various applications. The read and write pointers are incremented on
valid read_en and write_en signals respectively, and proper boundary checks are enforced
to prevent data loss or corruption.

The FIFO logic includes a memory block to hold the data, and logic to monitor and
update the full and empty flags, which help manage the data flow without causing
overflows or underflows. When the FIFO is full, additional write attempts are blocked,
and when it is empty, read attempts are restricted. This makes the design robust and
suitable for use in streaming data environments, buffering between producer and
consumer modules, or in communication channels like UARTs and networking buffers.

To validate the FIFO functionality, a SystemVerilog testbench (FIFO_tb.sv) is used for

simulation and verification. The testbench performs several operations such as applying
resets, writing random data until the FIFO is full, and then reading the data back to verify
correctness. It checks the status signals (full, empty) at each step and ensures that the read
data matches the written data, thereby confirming that the FIFO maintains data order and
integrity. Randomization and looping constructs are used to create varied and effective
stimulus scenarios.

The verification not only confirms functional correctness but also checks edge cases, such
as writing when the FIFO is full or reading when it is empty. This comprehensive testing

19
ensures reliability in real-time applications. The testbench environment can be extended
further with assertions and coverage analysis for exhaustive verification. Overall, the
FIFO design and its accompanying verification demonstrate a solid and reusable digital
component that plays a crucial role in data communication and processing pipelines.

20
 Chapter 6

Testing and Result Analysis

6.1 Test results
Simulation Result: A digital simulation waveform is a graphical representation that
shows how digital signals change over time during the simulation of a circuit. For
synchronous circuits, outputs often change in response to clock edges, while in
combinational logic, outputs change directly based on input variations. This waveform
helps verify functionality, check timing relationships like setup and hold times, and
identify logical or timing errors before implementing the design in hardware.

Figure 6.1: Simulation waveform of Memory access

Figure 6.2: Simulation waveform of Writeback Stage

21
Synthesis Report: The synthesis report provides detailed insights into the design after
logic synthesis. It includes information such as total cell area, standard cell usage, timing
summary (worst negative slack, total negative slack), logic optimization stats, and design
hierarchy. It also highlights constraint violations, reports on clock definitions and
generated clocks, and provides summaries for datapath and control logic. This report
helps verify whether the synthesized gate-level netlist meets the functional and timing
goals defined by the user.

Figure 6.3 Area report of Writeback stage

Figure 6.4 Timing report of Writeback stage

22
These results provide confidence that the constraints set in the SDC (Synopsys Design
Constraints) file are appropriate for the design's operational needs. The timing closure
process can be considered complete, and the design is ready for sign-off or further
optimization for power and area if required.

During the timing analysis phase, various operating frequencies were tested to evaluate
the design's performance and stability. By examining the slack values under different
clockconstraints, it was observed that frequencies beyond 850 MHz began to introduce
negative slack, indicating timing violations.

Figure 6.5: Gate-level netlist

Sl.
Blocks Original Area Rounded Area Dimensions (in µm2)
No.

1 Memory access 8655 9025 140x65

2 Write back 792 800 30x30

Table 6.1: Area report of each block

23
Floorplanning: The floorplanning stage is a critical step in physical design that involves
defining the physical layout of the chip before placement and routing. The floorplanning
report typically includes details such as core area, die area, aspect ratio, utilization
percentage, and locations of macros, I/O pads, and blockages. It outlines the placement of
power rings and straps, along with reserved areas for standard cells and macros. This step
ensures optimal space utilization, minimized congestion, and efficient power and clock
distribution, laying the foundation for a successful place-and-route process.

Placement: The placement stage involves positioning standard cells and macros within
the defined core area of the chip, after floorplanning and before routing. The placement
engine arranges these cells to optimize timing, area, and power, while ensuring minimal
congestion and optimal routing paths. During this stage, no physical connections (wires)
are made, but the tool considers logical connections to reduce net length and improve
performance. The

placement report provides information such as total wirelength estimation, cell utilization,
timing metrics (slack and critical paths), and congestion hotspots, guiding the next steps
of optimization and routing.

Routing: The placement stage involves positioning standard cells and macros within the
defined core area of the chip, after floorplanning and before routing. The placement
engine arranges these cells to optimize timing, area, and power, while ensuring minimal
congestion and optimal routing paths. The placement report provides information such as
total wirelength estimation, cell utilization, timing metrics (slack and critical paths), and
congestion hotspots, guiding the next steps of optimization and routing.

Routing creates physical connections to all clock and the signal pins through metal
interconnects. After CTS, we have information about the exact location of placed cells,
blockages, clock tree buffers/inverters and 1/0 pins. The tool depends on this information
to electrically complete all connections.

24
 Figure 6.6 Complete PnR of Writeback stage

Figure 6.7 Complete PnR of Memory access

The GSDII: The .gds file is created for all the blocks and then merged into the top
module GDSII file. A .gds file (also known as GDSII, short for Graphic Design System
II) is a standard file format used in the VLSI physical design flow to represent the layout
of an integrated circuit (IC). It contains geometric shapes, layer information, and
hierarchy that describe how a chip should be fabricated.

25
FIFO Verification: The testbench carries out multiple operations, including applying
resets, writing random data into the FIFO until it reaches full capacity, and then reading
the data back to verify accuracy. Throughout the process, it monitors status signals such
as full and empty to ensure proper behavior. It confirms that the data read matches the
data written, thereby validating the FIFO's ability to preserve data order and integrity.
Randomization and looping constructs are employed to generate diverse and effective test
scenarios.

In addition to verifying basic functionality, the testbench also evaluates edge cases, such
as attempting writes when the FIFO is full or reads when it is empty, ensuring robustness
under all conditions. For more exhaustive validation, the environment can be enhanced
with assertions and coverage analysis. Overall, the FIFO design and its verification
process illustrate a reliable and reusable digital component, essential for data

communication and processing pipelines.

Figure 6.8: Result of design verification

26
 Chapter 7

Discussion
7.1 Common faults observed

When working on digital design flows, some typical issues can cause errors in synthesis,
floorplanning, and analysis. Below are the common faults and which part of the design
flow they relate to:
i. Error while reading the SDC file due to the wrong usage of design constraints in
the SDC file.
ii. Error while reading the MMMC file due to improper specifying of PVT corners,
QRC, and QX tech files.
iii. While specifying the required HDL code at the top.f file.
iv. Faults occurred while creating configuration in library sets, rc corners, op-conds,
delay corners, constraint modes, analysis views, setup analysis views, and hold
analysis views.
v. Wrong usage of ports during floorplan in the tickle file.
vi. Improper placement of design in a specified area.

7.2 Causes and Remedies

i. By linking proper standard cell libraries like liberty file, technology file, and
library exchange format file to the required design during the synthesis process.
ii. Specifying the proper design constraints in the SDC file, by understanding the
proper syntax and its needs using the man command.
iii. By giving the proper PVT corners based on the technology file, and specifying the
proper QRC tech file for the synthesis process.
iv. By attaching the HDL file to the local directory (user-defined directory) and
specifying the proper path to the top.f file.
v. Improper placement of design can be achieved by varying the height and width of
the PR boundary in the floorplan tickle file.

27
 Chapter 8
Conclusions
8.1 Outcome of the internship
The internship provided valuable practical exposure to the VLSI design flow, contributing to
the development of both technical and professional skills relevant to the semiconductor
industry. Hands-on experience was gained using the CADENCE tool, along with a solid
understanding of synthesis, floor planning, and various Unix commands. Theoretical
knowledge of the semiconductor fabrication process was also strengthened. Additionally,
the opportunity to interact with industry professionals supported the building of a strong
professional network for future growth.

8.2 Scope for future work

Power consumption is a critical concern in VLSI design, especially for portable devices such
as smartphones and wearables. Future work can focus on developing power-aware
synthesis and floor planning algorithms that minimize power consumption without
compromising performance.

i. As VLSI designs become more complex and interconnected, reliability and

security become more critical. Future work can explore ways to integrate
reliability and security considerations into the synthesis and floor planning
process.
ii. Synthesis and floor planning are computationally intensive tasks, and the design
sizes are growing rapidly. Future work can focus on developing parallel
algorithms and optimization techniques to improve performance and scalability.
iii. To improve the placement to reduce routing congestion or optimize the RTL and
the get improve the performance of the design.

28
 Chapter 9
SWOT Analysis
Strengths:
i. Tool knowledge on PD flow (genus, innovus and tempus) in CADENCE.
ii. Understood concepts of PD flow.
iii. Workload management and soft skills.
Weaknesses:

i. Understanding complex SystemVerilog coding.

ii. Sticking on to work until its completion.
Opportunities:

i. With increasing advancements in AI, IoT, and semiconductor applications,

physical design remains a highly valued and growing specialization.

ii. Engaging in more complex physical design projects or certifications can enhance
readiness for full-time roles in semiconductor companies.

iii. Experience in physical design builds a strong technical base for roles in backend
VLSI design, timing analysis, and EDA tool support.

Threats:

i. The VLSI design flow is highly competitive, and designers must deliver high-
quality products on time and within budget to remain competitive.
ii. Change of domain from VLSI to other domain such as any IT sectors would be
difficult.

29
 Bibliography

[1] N. Weste, D. Harris, and A. Banerjee, "CMOS VLSI Design: A Circuits and
Systems Perspective," 4th Edition, Pearson Education, 2010.
[2] J. Cong, B. Liu, and Y. Ding, "Physical Design for 3D Integrated Circuits,"
Springer, 2018.
[3] Y. Cheng, "Physical Design Essentials: An ASIC Design Implementation
Perspective," Springer, 2018.

30
 Appendix
MMMC.tcl
set lib_dir "/home/training/Desktop/Memory_access/RISC_V_library/lib/"

set qx_dir "/home/training/Desktop/Memory_access/RISC_V_library/qx/"

set qxc_dir "/home/training/Desktop/Memory_access/RISC_V_library/qrc/"

create_library_set -name slow_libs -timing [ list "${lib_dir}slow.lib"]

create_library_set -name typical_libs -timing [ list "${lib_dir}typical.lib"]

create_library_set -name fast_libs -timing [ list "${lib_dir}fast.lib"]

#create_opcond -name op_cond_slow -process 1 -voltage 0.9 -temperature 125

#create_opcond -name op_cond_typical -process 1 -voltage 1 -temperature 25

#create_opcond -name op_cond_fast -process 1 -voltage 1.1 -temperature 0

create_op_cond -name opcond_slow -library_file ${lib_dir}slow.lib -P 1 -V 0.9 -T 125

create_op_cond -name opcond_typical -library_file ${lib_dir}typical.lib -P 1 -V 1 -T 25

create_op_cond -name opcond_fast -library_file ${lib_dir}fast.lib -P 1 -V 1.1 -T 0

#create_opcond -name op_cond_slow process 1 -voltage 0.9 -temperature 125

#create_opcond -name op_cond_typical -process 1 -voltage 1 -temperature 25

#create_opcond -name op_cond_fast -process 1 -voltage 1.1 -temperature

#create_timing_condition -name slow_tc -opcond op_cond_slow -library_sets slow_libs

#create_timing_condition -name typical_tc -opcond op_cond_typical -library_sets typical_libs

#create_timing_condition -name fast_tc -opcond op_cond_fast -library_sets fast_libs

#create_rc_corner -name slow_rc -T 125 -qrc_tech ${qx_dir}gpdk090_9l.tch

#create_rc_corner -name typical_rc -T 25 -qrc_tech ${qx_dir}gpdk090_9l.tch

#create_rc_corner -name fast_rc -T 0 -qrc_tech ${qx_dir}gpdk090_9l.tch

create_rc_corner -name slow_rc -T 125 -qx_tech_file ${qx_dir}gpdk090_9l.tch

create_rc_corner -name typical_rc -T 25 -qx_tech_file ${qx_dir}gpdk090_9l.tch

create_rc_corner -name fast_rc -T 0 -qx_tech_file ${qx_dir}gpdk090_9l.tch

# create_delay_corner -name slow_dc -timing_condition slow_tc -rc_corner slow_rc

#create_delay_corner -name typical_dc -timing_condition typical_tc -rc_corner typical_rc

#create_delay_corner -name fast_dc -timing_condition fast_tc -rc_corner fast_rc

# create_delay_corner -name slow_dc -library_set ${lib_dir}slow.lib -rc_corner slow_rc

# create_delay_corner -name typical_dc library_set ${lib_dir}typical.lib -rc_corner typical_rc

# create_delay_corner -name fast_dc library_set ${lib_dir}fat.lib -rc_corner fast_rc

create_delay_corner -name slow_dc -late_library_set slow_libs -early_library_set fast_libs -

rc_corner slow_rc

create_delay_corner -name typical_dc -late_library_set slow_libs -early_library_set fast_libs -

rc_corner typical_rc

create_delay_corner -name fast_dc -late_library_set slow_libs -early_library_set fast_libs -

rc_corner fast_rc

#create_constraint_mode -name func_const -sdc_files

/home/install/script_file/design_constraints.sdc

create_constraint_mode -name func_const -sdc_files

/home/training/Desktop/Memory_access/work/PnR/memoryac_sdc.sdc

create_analysis_view -name func_slow -constraint_mode func_const -delay_corner slow_dc

create_analysis_view -name func_typical -constraint_mode func_const -delay_corner

typical_dc

create_analysis_view -name func_fast -constraint_mode func_const -delay_corner fast_dc

set_analysis_view -setup {func_slow func_typical} -hold {func_typical func_fast}

set_analysis_view -setup {func_slow func_typical} -hold {func_fast func_typical}

Command for Floorplan, Placement, CTS and Routing

set init_gnd_net VSS

set init_pwr_net VDD

set init_top_cell memoryac

set init_verilog /home/training/Desktop/Memory_access/work/PnR/memoryac_netlist.v

set init_mmmc_file /home/training/Desktop/Memory_access/work/PnR/mmmc.tcl

set init_lef_file
{/home/training/Desktop/Memory_access/RISC_V_library/lef/gsclib090_translated.lef
/home/training/Desktop/Memory_access/RISC_V_library/lef/gsclib090_macro.lef}

init_design

floorPlan -flip f -s {65.00 140.00 1.016 1.04 1.016 1.04}

createPGPin VDD -net VDD

createPGPin VSS -net VSS

editPin -pin clk2 -use CLOCK -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Top -layer 6 -spreadType START -spacing 0.29 -start 60.0 140.0 -pinDepth
0.583500 -pinWidth 0.14

#editPin -pin {{o_RX_Byte[0]} {o_RX_Byte[1]} {o_RX_Byte[2]} {o_RX_Byte[3]}

{o_RX_Byte[4]} {o_RX_Byte[5]} {o_RX_Byte[6]} {o_RX_Byte[7]} {o_RX_DV} } -use
SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Left -
layer 4 -spreadType START -start 0.0 10.0 -spacing 0.29 -pinDepth 0.583500 -pinWidth 0.14

#editPin -pin {{tx_data[0]} {tx_data[1]} {tx_data[2]} {tx_data[3]} {tx_data[4]} {tx_data[5]}

{tx_data[6]} {tx_data[7]} {uld_tx_data} } -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit
MICRON -spreadDirection clockwise -side Left -layer 4 -spreadType START -start 0.0 10.0 -
spacing 0.29 -pinDepth 0.583500 -pinWidth 0.14

#editPin -pin {{rx_data[0]} {rx_data[1]} {rx_data[2]} {rx_data[3]} {rx_data[4]} {rx_data[5]}

{rx_data[6]} {rx_data[7]} {uld_rx_data} } -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit
MICRON -spreadDirection clockwise -side Left -layer 4 -spreadType START -start 0.0 10.0 -
spacing 0.29 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin EX_MEM_ALUOUT* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Right -layer 4 -spreadType START -start 65.0 90.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14
editPin -pin EX_MEM_IR* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -
spreadDirection clockwise -side Right -layer 4 -spreadType START -start 65.0 60.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin EX_MEM_type* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Right -layer 4 -spreadType START -start 65.0 30.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin MEM_WB_rs2* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Right -layer 4 -spreadType START -start 65.0 20.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin TAKEN_BRANCH* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Right -layer 4 -spreadType START -start 65.0 135.0 -spacing
0.29 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin MEM_WB_ALUOUT* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Top -layer 4 -spreadType START -start 35.0 140.0 -spacing
0.29 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin data_mem_addr* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Left -layer 4 -spreadType START -start 00.0 40.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin data_mem_write* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -

spreadDirection clockwise -side Left -layer 4 -spreadType START -start 00.0 10.0 -spacing
0.40 -pinDepth 0.583500 -pinWidth 0.14

editPin -pin en_w* -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Left -layer 4 -spreadType START -start 00.0 5.0 -spacing 0.29 -pinDepth
0.583500 -pinWidth 0.14

#editPin -pin rxclk -use SIGNAL -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Left -layer 4 -spreadType START -start 0.0 18.0 -spacing 0.29 -pinDepth
0.583500 -pinWidth 0.14

globalNetConnect VSS -type pgpin -pin VSS

globalNetConnect VDD -type pgpin -pin VDD

addStripe -nets {VDD VSS} -layer Metal6 -direction vertical -width 0.44 -spacing 4.75 -
set_to_set_distance 10 -create_pins 0 -start_from left -switch_layer_over_obs false -
max_same_layer_jog_length 2 -padcore_ring_top_layer_limit Metal9 -
 padcore_ring_bottom_layer_limit Metal1 -block_ring_top_layer_limit Metal9 -
block_ring_bottom_layer_limit Metal1 -use_wire_group 0 -snap_wire_center_to_grid none

addStripe -nets {VDD VSS} -layer Metal7 -direction horizontal -width 0.44 -spacing 4.75 -
set_to_set_distance 10 -create_pins 0 -start_from bottom -switch_layer_over_obs false -
max_same_layer_jog_length 2 -padcore_ring_top_layer_limit Metal9 -
padcore_ring_bottom_layer_limit Metal1 -block_ring_top_layer_limit Metal9 -
block_ring_bottom_layer_limit Metal1 -use_wire_group 0 -snap_wire_center_to_grid none

sroute -connect {blockPin padPin padRing corePin floatingStripe} -layerChangeRange {Metal1

Metal9} -blockPinTarget nearestTarget -padPinPortConnect {allPort oneGeom} -
padPinTarget nearestTarget -corePinTarget firstAfterRowEnd -floatingStripeTarget
{blockring padring ring stripe ringpin blockpin followpin} -allowJogging 0 -
crossoverViaLayerRange {Metal1 Metal9} -nets {VDD VSS} -allowLayerChange 0 -
blockPin useLef -targetViaLayerRange {Metal1 Metal9}

write_lef_abstract -noCutobs -extractBlockobs -SpecifyTopLayer 7 -PGpinLayers {Metal6

Metal7} -stripePin /home/training/Desktop/Memory_access/work/mem_library/memoryac.lef
-5.7

place_opt

create_ccopt_clock_tree_spec -file memoryac.spec

clock_design

globalRoute

detailRoute

extractRC

rcOut -spef memoryac.spef

saveNetlist memoryac.v