11-1 Basic ldeas
GOOD TO KNOW
ienueafure stalble toan agadoc xiemal gate !
Aicld Etfect
pue 2shows thc wmalbsing voltitges fot a l!T The r tik
the gate Mpply volfoe npaltVe e term Se id
apc is i e , ahd
ntated fo the deplefion fayety Aroud esh ptyon These tplttem ltyets e
S2e of ch coponent s
strn
cittco! bnatot of lre elecho)% nd oes cteates the depleios iayer,
calored arcax
/Reverse Bias ofGate
n ig. !-2, the piype gate snd ile n-type sourcc korm the gate- sUf CE fed
Becaue nf ree
GOOD TO KNOW With a FET, we always rverse-bias the gate-sOurCe dode.
tbras, the gate current t; is approximately zero, which s cqusvalent to sayang te
The fied etiect tranststor was the JFET has an almost info:ite input tesistance.
pEtantÈd in 1926 vear betore
the Eit y sulus i#iente:d
Fiqure 11-1 (o) Part of JFET, (b)single-gate JFET
(882-*963) Prat tic ai JFETs
were ot invented until rvany
yEars tter
DRAN
GATE
SOURCE
Fiqure f4-2 Normal btasing ot JFET
DRAIN
GATE
Ve
SOURCE
418
JGate Voltage Controls
Dran Currem
natw lhannet etween the depletion laycr Whnthe zale
tON negative, the
depletinn layes expa Bdthe
hwe, lhe oe negative
sOuCC and the drain the gate voltagr the snaller the
The fET is a
GOOD TO KNOW voltagecontrolled deviee bc HEe
mueh uTent loWs between ihe source ai
thc
Te depietion iayes are
sctually mum drancurtcnt flows through the IEET ThE drus Wher Vs 1 a
is why a
adet ne the top of the-tvop nomally-0n device. On the othcrand, if Vsis negatise JFEI sreirsed o2
laycrs toIch and the drain current is enogh the epieu
mateiats 3nd nairowet at the cut off
atto. The reasOn tor tthe
change in the width can be
VSchematic Symbol
understoc by reaizing that the The JFET of Fig. 1-2 is an n-chanel JFET
hecause the channei tetsten e
dr8n Curreh witlproduce a source and the drain is an n-typc semiconductor. Figure l-34
matic symboi for an n-channel JFET. In many shors the tk
votBge drop along the iength of low-frequency appizctions the
source and the drain are interchangeable because vou can use ether
he channei. With fespect to the etai as thc
source and the other end as the drain.
sourCe, a more p0sitive voltage The source and drain terminals are not interchangeable a high ireget
S preseni as you move up the Cies. Almost always, the manufacturer aninimizes the internal capacitatce nff
channel toward the drain end. drain side of the JFET. In other words, the capacitance between the ga asd the
Snce the width of a depietion drain is smaller than the capacitance between the gate and the source YoE *
lean nore ahout internaleapacitances and ther eftect on circuit acion ia a
iaye iS Dproportional so the
chapter.
aMOunt of reverse-bias voftage. Figure l1-3h shows an lternative syntoi for an n-channe! 1FET T
ire depietion layet of the pn syImbof with its offset gate is preterred by many engineers and technscans The
iunCUO Tàust be wider at the offset gate points to the sourcc end of the device, adefinite advantage in con:
10p. here the atnount of cated multistage circuts.
severse-tbies voitage ís greater. There is aiso ap-chanme! JFET. The schematte synboi for a rehanne
JFET.shown in Fig. 11-3c, is similar to that lorthe a-hne! JFET Cee t
the gate arrow poinis in te opposite direction. The acten ef a p-chsanel #
is complementary;thal is, allvoltages and crrents are revesed Toreverg
pchannet JFET, hegatc is made positive with respect 4o the sue Thenr
Ves is made positive.
tla ayoto jna n
Fiqure 11-3 (o) 5chematr synlo () otse
DRAIN DRAIN
GATE
GAE
5OUHCI
JFET
M1-2 Drain Curves
votage l
otage lx cquals tihe drain suppìy
Maximum Drain Current
grester th£n lp.
staredcts
Figure$4 Nomahas. t zer gae votae ici
4)
Vihe Ohmic Region
ln Fg I-5, the pucholt votage separates two majo pcratm
JFET The almost-horizontal region is the active region
of the drain cuvehelow pinchoff is called the ohiieregion.
When operated n the ohmic region, aJFET is cquivaint i0 rsiSt
with a value of approximately:
Rps =
Ipss
= 4 V and irss
Rps is caled the ohnic resistance of the JFET In Fig. }-5. Vp
i0 mA. Therefore, the chmic resistance is:
4V
Rps
reS0Stace
fthe ETisoperating ywhere ii the onmic region, i! has an ofDRIE
of 400 S2.
Gate CutoffVoitage
the shosted-gate condtio)
In this erank. thN
always tor Vs ), w
curve is The iNÉ cHh
Pichoif voitageis 4V and
the breakdown volare ts 30
cuvnt
Voltage, the smallerthe drain
Hegatise the gatc-sOUICE
Fiqure 11-5 Dtat CUIV
(t 625 1tA
NOW
Example 11-2
An MPEA857 has Vp = oV and pss =}00 mA. hat is the ohmc teutyy.
The gate-ource cutoff vollage"}
SOLUTION The ohmic reSIStance is:
6V
Since the pinchoff voltage is 6V, the gate-source cutott voltage is
PRACTICE PROBLEM 11-2 A 2NS484 has a Vesoti =-30 Vand
Inss=5mA. FHnd its ohme resistanee and , values.
11-3 The Transconductance Curve
The iransconductance curve of aJFET is a traph of h, versus V By r.ch
the values of ty snd Vs ef cach drais cuein F. 5, we can pktthe urvei
NOW g 1a Notke that the curve is bonimear bevause the cusrent iCTe iad
Any 31Tbis a bansceoluctawe ue ike Fg t Ihecn
by tie HSut
Becaus at thesuated quatuy inn dn cyuae) iIafe ten callext xji'e
devkces ihe squaing ot the quantuty poluces tle kHlga cUve of Fig 1
tioiiediescotectice
Heans thal we are gpung taos bke p/lpy VN
thupker li
3
point
In ig. l -6e. the half cutoff
current of:
produces anormal1zed
votage. ite raa current
half the cuioff
the gate voltage is
In words: When
quarter o f m a x i t R .
Example 11-3
hulltoff
(oint
cHTUnt at the
drain
cuoll point
SOLUTION
ALlHe half
L25 mÀ
423
A1-4 Biasing in the Ohmic Region
Ihe iET can be biascdin the ohte or n thc active regm y hen bai
ohnic region. the JHiT is cquivaleni to a sesIsiae. When bined a thc
regon. the ItET sequi valent to a curent soufee. In thrs section we he
tte biay, the method ised te bias a PET in the ohnic regon.
Gate Bias
Figure !1-7ashows gate bias. Anegative gate votage of -Voe is appizcd to ibe
gate through biasing resistor Re. T?is sets up adraia cuten that is iess than ip
When the drain current fiows theough Ry, it sets up a drain votage of
Gale bias is the wors way to bias a JFET nthe active regon becAuse tie ti r
is fao unstable,
For example, a 2N5459 has the toiow ing spreads betsees uGKTUE
and aaxium: Ips Varies from 4 te l6 mA. and Vaso, Varies fom- -
Figure !-76 shows the minimT aRd aximuR: trAsCOnCtare . s
gatc bias of -Vis Uscd witih thìs JFEE, We get tbe miimum ai eRT
potts shon. (0, has a tian current of 12.3 mA, abd has adrait ures
HardSaturation
t
Example 11-5
425
Fiie11.8
Voo
Ros
400 S2
3 safuration cuten
the dc ioad ine haS
voltage is V. The upper end of
Between points A anxd B, the input
saturstton
than Ips_. the FET is in had
s the dc iai iine Since p:sti is much less
Figure ii-8h sho.
Te ohnnic Fesistahce is:
4V
i1-X thiea i n votage is
in çeeqvaient cifcuit of Ip
4902
Using Fig. li-8, int Kpy aust p it , 3V
PRACICEPROBLEM 175
426
(10
V11-5 Biasing I the Active letj1o
wed IoremyB, uhen
Iamg OHs, It is offen tony uelnay
desitable futc teal salñs andeiBt
Caliet to, wcan usc uhcal
aedesnmg }l solulios o etereunc ACiH
cts
sulator like Multism ot nced even
Self-Bias
tigure I ushowN self-bias. Since
R. avollageex1sts drin curent tiowsthrougl the soufce
between the source and ground, ren
given by
(i-6;
Since Ve is zero:
(11-7)
Ihis says that the gate-source voitage
source resistor. Basically, the circujt equals the negative of the voitage aTTUSS tH
creates
developed across Rç to reverse-bias the gate. its own bias by using ihe voia*
Fgure 1i-9h shows the efect of different source
resistors. Thee s 2
nediun value of Rs at which the gate-source voltage is
An approXimation for this medium resistance is: half of the cutott vottage
R_ Rps (l1-8)
This cquation says that the source resisiance shouhd eqtai the ohmie resisiance ot
the JFET. When this condition is saisfied. the Vos is FOughly haif the cuoit oit
age and the drain current is Oughiy one-quarter of ps.
Figure 11-9 Seitoras
SMALL R
MEDIUM R
1ARGE R.
427
Fioure 11.t0
tetrge
Sihe ány (k poHnts can be tsed. e hR the t i comPreent e
coondates for ihe frst
ondng to l, 0and p pss: therekote, ihe
(0. 0), which is the origin To get the sccond potnt. fim Ves for l, La
mA)(S00 ) -2V therefone. the
Case, Ip a 4 mA and Vos4
the sccond point are at (4 mA, -2 V).
We now havetwo ponts on the graph of Eq (1-7), The t n peamts ar
0.0) and(4mA, -2 V). By plotting these two ponts as shown in Pig ll.th
This
can draw astraight line through the two points as shown.
intersect the transconductance curve. This intersection point is the operxin
of the self-biascd JFET. As you can see, the drain current is shghtly les fhag
2mA, and the gate-source voBtage is slightly less than -1V.
In sunamary. here is aprocess for finding the point of any seif-bie
JFET,provided you have the transconductance curve. If the curve is not w
ablc, you can use the Vcsiotn and Ipss rated values, along with the se
cquation (il-3), to develop one:
1. Multiply pss by Rç to get Vas for the second point.
2. Plot the second point (/pss. Vas).
3. Draw a line through the origin and the second pojnt
4. Read the coordinates of the intersection point.
The point with self-bias is not extremely stable. Because of his,
bias is used oniywith small-signal amplifiers. This is wùY you nay see seifas
JFET circuits near the front end of cOmmunication rceivers whe he
is smali.
Example 11-6
In Fig. i-tio, what is a edHnSoCe sesstuce
Usng the ule discussed eardier' Esiae the iraitt voilar a n
SEiSCE esistt
the J1T:
Kps 4V
Fizure i0b shows asHrC Iesislahc ol 4X) S2 n
sbis cKC, the diain cureut s amt
and the drain voltage is roughly: otteotarter of 10 mA, 0F
Vy= 30 V-(2.5 mÀX2 kS2) 25 V
