ECE 6130: ADVANCED VLSI DESIGN

Chapter # 4
Fabrication of CMOS Integrated Circuits

Shafaat Ahmed Bazaz (Ph.D France)

Professor
Beaconhouse National University, Lahore
Pakistan

Lecture # 3
4.1 Overview of Silicon Processing
Si wafer showing die sites

• Start with crucible of molten silicon (»1425ºC)

• Insert crystal seed in melt
• Slowly rotate/raise seed to form single crystal boule
• After cooling, slice boule into wafers & polish
4.1 Overview of Silicon Processing
Si wafer showing die sites

Most important steps for VLSI designer:

•Patterning and creating the layers of material
needed in CMOS process
300 mm
•Cleaning and rinsing of wafer
wafer
• Wafers are taken in groups per week
4.1 Overview of Silicon Processing Yield: Percentage of functional sites
Si wafer showing die sites on a wafer

•NG→ good number of sites

•NT→ Total no of sites on wafer
•85 % yield is considered good
• High yield requires hours of
thinking and experimenting
•Requires thorough understanding
of Si process
No of total die sites on a wafer of
diameter d is estimated as:

• Empirical Analysis shows that Large die

areas tend to have smaller yield:

•Adie→ area of the die

•A→ area of the die •de→ Wasted edge distance by placing
•D→ defect density in cm-2 (average no of rectangular sites in circular wafer
defects per cm2), limit of perfection
• generally D= 1 cm2,
4.1 Overview of Silicon Processing
Physical Defects tends to occur in clusters on the wafer
Using
Binomial
equation form:
Yield to the failure
of die in larger where
area Afail

• generally, VLSI designer is not responsible for yield

analysis
• people involved in production line do so (physicist,
materials and chemical engineering, mathematics,
statistics)
4.1 Overview of Silicon Processing
Economics

•Both Cs are difficult to compute

• Cchip depends on material used, salaries of all personnel, overhead
(electricity, water, taxes ….). Cost of Fab $1-3 Billion
• Csell depends on direct and indirect cost plus a fraction of plant debt.
– It should be price the customer is willing to pay
– If product is in demand, easy to calculate for more profit
– Great engineering design may go astray if could not market well in front of
clients
– It decreases with time
–Time to market
•Chip with 100 million transistor requires financial backing, strong
technological support, innovative engineering and reliable sale force
•Fabrication process is the major expense in the profit
•Keep in mind, design (engineering) cost is very high
4.2 Material Growth and Deposition
MOS Transistor Structure:
• Stack of layer
• Both electrical and geometric properties are important

• Layers are deposited/created first,

• patterned/etching using
lithographic techniques
– Doping of the layers in specific
shapes in lithographic process
4.2 Material Growth and Deposition: Basic Processing Steps
4.2.1 Silicon Dioxide growth
• good insulator
• adheres to most materials grown or
deposited on top of Si wafer
•Generally known as QUARTZ glass
Thermal Oxides: use pure Oxygen
and used as GATE OXIDE
•Si is used from wafer thickness of Si wafer consumed:
• Heat as Catalyst

Final structure
(a) Growth phase
•Thickness xox depends on
temperature, crystal orientation and
growth time
Wet Oxidation: in Nitrogen and Cl environment • better yield but slow

•Native Oxide (naturally available)

• growth temperature 850-1000 C
4.2 Material Growth and Deposition: Basic Processing Steps
4.2.1 Silicon Dioxide Deposition
• Use Silane to produce SiO2 molecules above the wafer
• Chemical Vapor Deposition (CVD) Oxide
• Thickness of Oxide is controlled by growth rate and
deposition time
• LTO- Low Temperature Oxide
• Doping glass help in planarization
4.2 Material Growth and Deposition: Basic Processing Steps
4.2.2 Silicon Nitride
• High dielectric constant so good insulator
– to separate adjacent FETs
– used as ON (Oxide Nitride) sandwich for the dielectrics in capacitor structure
• Used as passivation layer (over glass layer) to protect against external
contamination

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4.2 Material Growth and Deposition: Basic Processing Steps
4.2.3 Polycrystal Silicon (PolySi, Poly)
• When Si atoms are deposited on amorphous SiO2 layer, the Si attempts
to crystallize but cannot find a crystal structure for reference. This results
in small regions of Si crystals.
• Used as GATE material in FETs.
–Can be doped
– good adhesive property with SiO2
– Poly has sheet resistance of 25-50 Ohms.
–Coated with high melting temperature (refractory) metal Ti or Pt to reduce the
sheet resistance (Silicide)

• Performed at 500-600C
• Poly-Metal layer is considered
as single layer in the processing
• Stacks of PolySi are developed
to make capacitors in DRAMs

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4.2 Material Growth and Deposition: Basic Processing Steps
4.2.4 Metals
• Al is the most common metal used for
interconnecting wiring in ICs
• Can be evaporated by heating in vacuum chamber to
coat the wafer
• Has good adhesive property and is easy to pattern
• Has bulk resistivity of p= 2.65 μΩ-cm. Al interconnect
line that is 0.1 μm has a sheet resistance of :

Visualization of Electromigration effects in Al

• Mixing Copper during the metal deposition step. 12

Increase the resistivity to p=3.5 μΩ-cm
• But now special patterning technique (lift-off)
4.2 Material Growth and Deposition: Basic Processing Steps

4.2.4 Metals (Controlling the current density)

• For interconnect line with thickness t and width w (area
A=wt), current density:

• VLSI designer cannot alter thickness.

• So VLSI designer uses minimum line width to
keep J below Jmax (Design Rule)
• Al has low melting temperature that prohibits the
use of high-temperature processing steps once it
is deposited on the wafer
• Transition from Metal Gate to Poly Gate
• Cu has half resistivity than Al but patterning is
difficult (lift-off technique)

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4.2 Material Growth and Deposition: Basic Processing Steps
4.2.5 Doped Silicon Layers
• To add acceptors or donor atoms into the wafer
• Atoms are ionized in a chamber then accelerated to
high energies in a particle accelerators

Basic section of an ion implanter:

Annealing process:
• To heal the crystal and set the dopants
into proper locations with crystal lattice
through particle diffusion
• Diffusion is the collective heat induced
motion of particles concentrated in small
regions
• temperature is raised and then lowered
in rapid manner

The ion stopping process:

Ion smash to the substrate
at typical energies of 100-
200KeV

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4.2 Material Growth and Deposition: Basic Processing Steps
4.2.5 Doped Silicon Layers
Ion distribution into Si using first order Gaussian form (in cm-3)

• x=0 is the surface of the wafer

• Rp is projected range showing the average depth of an implant ion
– Depends on incident energy, species and crystal orientation
– ranges from 0.1 to as deep as 1μm
– peak density occurs at x=Rp
• Standard deviation is denoted as the straggle △Rp representing the variation in
the stopping depth of individual ions due to statistical energy loss
•Number of implanted ions is usually described
by the implant dose:

• Has unit of cm-2

• can be measured using charge
counter
Gaussian implant profile 15
4.2 Material Growth and Deposition: Basic Processing Steps
4.2.6 Chemical Mechanical Polishing

(a) After oxide deposition (b) After CMP

• Used when more than two metal layers are stacked 16
• used during metal deposition, photo-resist in lithography
4.3 (Photo) Lithography
How to make the sub-micron feature to a material layer?
• Optically project the shadow of the pattern onto the chip surface
• Apply photolithography technique to transfer the pattern to the surface
• Same method used in making PCB but here the resolution is smaller
(0.12um)
• Responsible for the shrinking of chip size

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4.3 (Photo) Lithography

Photolithographic
Procedure
• Starts from the design file you
submit to the manufacturer in GDS-II
or CIF formats
• Data is used to create a piece of
high-quality glass (reticle) that has
the pattern (5-10 times the actual size)
defined using a metal such a Cr
•When light is illuminated on the
reticle, the shadow of the pattern is
projected on the chip

(a) Glass 18
(b) Reticle or Mask (5-10 times the
size if actual pattern size)
4.3 (Photo) Lithography-Deposition
Deposition of Photoresist: Sensitive to light

(a) Resist application (b) Coated wafer

(c) Beading Effect

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Figure 4.11 Exposure step
4.3 (Photo) Lithography-Deposition
Deposition of Photoresist:
• Sensitive to light
• Exposure Step: React to UV
region of the spectrum where
the photon energies are
highest and the wavelengths Exposure step
are shortest
• Positive Photoresist: where
the regions that are shielded
from the light are hardened in
the development process,
while regions that were
exposed to light are rinsed
away

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4.3 (Photo) Lithography-Deposition
• Positive Photoresist: where the regions that are shielded from the light are
hardened in the development process, while regions that were exposed to light
are rinsed away
• Photo-resist is rinsed after the exposure step
• Negative Photoresist has opposite characteristics

Dark Region
Light Region

Hardened resist layer protects

underlying regions

(a) Exposure pattern (b) After development and 21

rinsing
4.3 (Photo) Lithography-Etching
•Reactive Ion Etching: Surface of the wafer is subjected to gaseous plasma
formed from inert gases (Ar) with reactant chemicals
• Chemical and plasma are used to attack and remove (etch) the material layer not
shielded by the mask (photo-resist)
• Finally transfer the data from CAD layout design to the physical wafer thus
creating the physical implementation of the logic network
•Resist withstands the etchant mixture during this process
• Photoresist layer is sometimes also referred as MASK
• PolySi, Metals, Oxides, Nitrides can be patterned using etching techniques

Etching of an oxide layer

(a) Initial patterning of resist (b) After etching process

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4.3 (Photo) Lithography-Doping
Creation of doped Si patterns
• Oxide is grown on the wafer and then use lithography to etch down to the Si surface.
• Resist-Oxide layer (Oxide openings) is used to shield the Si from an Ion Implantation step
• Lateral doping: Width of n+ region is larger than the oxide opening

(a) Incoming ion beam (b) Doped n-type regions

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4.3 (Photo) Lithography-Summary

Major Steps in
Lithography
• Deposition of
Photoresist
• UV Patterning of photo-
resist
• Rinsing of photoresist
(Mask making)
• Etching of the material
to be patterned or
• Doping of n+ and p+
regions
• Remove photoresist

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4.3 (Photo) Lithography-Wafer site
•Step-and-Repeat process using Wafer
Stepper that allows the accurate movement
of the wafer to align the optics to each site,
one at a time
• After a site is exposed , the mechanism
steps the wafer to the next site
• Registration Target (geometric patterns)
used for alignment references

• Test Site locations: Contains the test structures

and circuits (MOS capacitor, doped regions of Si,
MOSFETs and Simple circuits
• Well characterized devices, allow wafer to be
electrically tested during various phases of the
manufacturing sequence.
• Provides info about how well the fabrication
flow is progressing

• Wafer Probes (Probe Station)

are set of very small metallic
probes that can contact regions
on the wafer to allow the
electrical testing

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4.3 (Photo) Lithography-Wafer site
• Wafer Probes (Probe Station) are set of very small metallic probes that can contact regions
on the wafer to allow the electrical testing (MEMS Microgripper Testing at COMSATS))

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4.3.1 Clean Rooms • Dust may lead to defect
due to small pattern sizes
Cigarette Smoke:
• Constant top-down flow of
• … contains 10.000.000 dust filtered air
• All air is replaced several
particles per cubic foot (» 27l)
times a minute
• Clean air only 100.000 • Wear gore-tex ‘bunny suits’
• Operating room less then 1000 all the time
• Q: How many dust particles per cubic
foot in an IC foundry?
• A: Less then 1!

• Class X clean room means that there are less than X

particles per cubic feet with diameter greater than 0.5micron
•Pellicles: Used in lithographic site to avoid dust on reticles 27
4.4 CMOS Process Flow

• Device and circuit engineer view processing parameters as the

fundamental limits to how fast their transistors and circuits can switch
• Systems Architect understand the logic blocks need to be created in Si
and that the processing dictates area allocation, interconnect levels,
delays, clock speed and other dozen of systems level consideration
• Process info affects everyone in all VLSI design levels

Types of CMOS Process:

• n-Well with p-type Si Substrate
• P-Well with n-type Si Substrate
• Twin Tub
• Silicon on Insulator (SOI)

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4.4 CMOS Process Flow: n-Well with p-type Si Substrate
Initial sequences in the CMOS fabrication sequence
(a) Starting wafer with lightly
epitaxial layer for high quality
Crystal layer by dropping Si
atoms on heated wafer
Epitaxel (Epi) Layer:
• Means arranged upon
• Protection against Latch-up (SECTION 5.2.8), flow of unwanted high current
• GROW HIGH PURITY Si layers of controlled thickness with accurately determined
dopant concentrations distributed homogeneously throughout the layer
• Electrical properties for this layer are determined by the dopant and its concentration
in the Si

(b) Creation of n-well in p+

epitaxial layer for FET using
masking step (MASK1)

(c) Active area definition using

nitride/oxide. Thin layer of
thermal oxide for releasing the
mechanical stress of the crystal
surface 29
4.4 CMOS Process Flow: n-Well with p-type Si Substrate
Initial sequences in the CMOS fabrication sequence
(a) Starting wafer with epitaxial
layer for high quality Crystal
layer by droping Si atoms on
heated wafer

(b) Creation of n-well in p+

epitaxial layer for FET using
masking step (MASK1)

(c) Active area definition using

nitride/oxide. Thin layer of
thermal oxide for releasing the
mechanical stress of the crystal
surface

(d) Si etch for active areas

to make electrical isolation
between adjacent FETs

(e) Region of Field OXide

(FOX) growth

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(f) Removal of Nitride
Layer. Surface preparation
4.4 CMOS Process Flow
Formation of nFET and pFET: Self Aligned Gate Process

(a) Gate oxide growth, tox is

defined here

(b) Poly gate deposition and

Self Aligned gate patterning

(c) pSelect mask (photoresist

to block nFET locations) and
implant

(d) nSelect mask (photo-

resist to block pFET
locations) and implant

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Silicided gates are created by refractory metal on the Poly to
reduce the sheet resistance of Poly lines
4.4 CMOS Process Flow First metal interconnect layer

(a) After anneal and CVD

oxide

(b1) Active Contact

Mask to make HOLES
in Oxide

(b2) Active Contact Mask to make

HOLES in Oxide. After CVD oxide,
activate contact Mask for Metal
holes to n-p regions, filled with
metal (W) plugs

(c) Metal coating and

patterning

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Passivation layer of Si3N4 (overglass): protection from
external contamination and electrical isolation
 Bonding pad structure: to electrically connect the
4.4 CMOS Process Flow chip to external world

Final
Package

Layout
Design

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 Bonding pad structure: to electrically connect the
4.4 CMOS Process Flow chip to external world

VIA

VIA Mask

(a) Top view

(b) Side view

Size of Bonding (100 μ m  100 μm)

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 • Better electrical characteristics
4.4.1 CMOS Process Flow: Variations • Smaller size, higher density
Lightly Doped Drain nFET: Reduce electric field thus • Enhance the yield
increasing the reliability of the transistor

(a) Light (n-) implant: Low

dose donor dopant

(b) Oxide coating

(c) After etching: Side Wall

Spacer blocks the heavy
donor implant in drain and
source regions

(d) Heavy donor implant

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4.4.1 CMOS Process Flow: Variations
Figure 4.21 LDD nFET with silicided gate and contacts

(a) LDD (Lightly Doped Drain) FET

structure: Sheet resistance of Poly is 25
Ohms or more

(b) Silicide formation: Reduces sheet

resistance of Poly to 10m ohms

Ti and W cannot be replaced by Poly 36

as they don’t adhere to Si properly
4.4.1 CMOS Process Flow: Variations
Use of Cu interconnect material instead of Al • Bulk resistivity of Cu is
1.67 μΩ-cm
Cu patterning using the Damascene process
• Cu is difficult to deposit
and etch using standard
RIE process
• Cu diffuses into Si thus
(a) Oxide patterning alters the electrical
characteristics. So cannot
be deposited directly on
the top of Si
• Also diffuses in SiO2
• Micragem Process for
new materials for Metal

(b) Cu deposition using

electroplating

(c) After planarization

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4.4.1 CMOS Process Flow: Variations
Dual-Damscene structure with copper vias

First Pattern on Oxide layer

Second step Pattern on Oxide layer

Cu VIAS

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4.4.1 CMOS Process Flow: Variations

• Cu is also used to connect FETs to the external world

• Cu provides lower resistance than Tungsten.
• Less contact resistance as compared to standard Al-W interface
•Cu diffuses into Si regions and has poor adhesion properties. A
barrier layer is provided of W, Ti, TiN, Ta TaN.
• Keep in mind it effects the resistivity and sheet resistance

•Years of research required to understand such effects

• Change of mentality on our side is required

Dual-Damscene structure with copper vias

Cu VIAS

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4.5 Design Rules
• Role of physical design is to create a set of masks that define our IC.
• The design rules are a set of requirements and advises that are defined by the
limits of the process (i.e. the stable process window) which in turn is defined by
the capabilities of the individual process steps.
• In general, minimum design rules are defined by the resolution and alignment
capabilities of the lithography system.
• Design rules define
– the minimum feature sizes and spaces for all levels, minimum overlap and
spacing between relevant levels.
• The minimum line widths and spaces are mandatory rules to ensure that all
layouts will remain compatible with lithographic process tolerances. Violation of
minimum line/space rules will result in missing, undersized, oversized or fused
features. Minimum spacing between levels guarantees that features of two
different levels can be delineated by photolithography and etch.
• Minimum overlap (enclosure, cut-in and cut-out rules) requirements reduce the
effect of large topographies and prevent unnecessary etching of underlying
layers.
• Design Rules (DRs) are set of geometrical specifications that dictate the design
of the layout masks

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4.5 Design Rules

• Design rules, in design, are usually minimum allowable values for certain
widths, separations, extensions, and overlaps of and between
geometrical objects.
• Mandatory Rules: Min width, distance between two layers.
– User cannot violate these rules
• Advisory Rules: Overlap, enclose. Use can violate at his
risk.

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4.5 Design Rules: Naming Convention
–Light field features: draw the feature–the object you want
left behind after the etch. When drawing Metal and Poly0 (light field
features), the final layer obtained is of these drawn features

Metal

Metal

Poly0 Poly0

–Dark field features: Areas you want to etch away. When

drawing CONTACT, VIA, HOLES, a dark field level, you will draw the
holes that will later serve as Poly 1 anchor holes.

Anchor1

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Oxide1
4.5 Design Rules: Types

• Minimum Width
• Exact Width
• Not Exist
• Spacing
• Surround
• Overlap
• Extension
• Density
• Angles

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 • difficult to obtain Sharp Edges due to line width limitations
4.5 Design Rules: Width of imaging system.
•Light-wave with an optical wavelength of λ cannot accurately
1. Minimum Width: image a feature size much less than that value
Minimum width rules • Positive photo-resist has better development properties
specify the minimum
width of all objects, in
any direction, on the
named layer.
2. Exact Width: Exact
width rules specify the
exact width of all
objects on the named
layer. The width of
octagons is measured
between parallel sides.

Design rule limits for Polysilicon Width

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4.5 Design Rules: Spacing between Layers

4. Spacing: Spacing rules specify

the minimum distance that
should separate all pairs of
objects, either on the same layer
or two different layers.

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4.5 Design Rules: Surround
5. Surround/Enclose: Surround
rules specify that objects on
one layer must be completely
surrounded by objects on
another layer.

(a) Side view (b) Surround rule: Between

Active area (n+) and Active
Contact Edge
Surround rules compensate for the alignment 46
tolerance of the stepper
4.5 Design Rules: Surround rule if not followed
5. Surround/Enclose: Surround
rules specify that objects on
one layer must be completely
surrounded by objects on
another layer.
Figure 4.26 Misalignment-induced defect

(a) Top view

Surround rules compensate for the 47

alignment tolerance of the stepper
4.5 Design Rules: Surround rule if not followed

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4.5 Design Rules: Extension Rule
7. Extension/Cut-out: Extension rules specify the
minimum amount that an object on one layer must
extend beyond the edge of an object on another
layer. Objects are not considered in violation of
extension rules when they:
▪ Extend more than the specified distance
▪ Have a coincident edge but are otherwise outside
▪ Are entirely surrounded

Example of an extend (gate overhang) design rule

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(a) Gate overhang DR (b) Misalignment failure

4.5 Lambda Design Rules:
▪ Generalized Design Rules (not specific to a fabrication technology)
▪ Based on reference matrix λ that has unit of μm
▪ All widths, spacing and distances are written in the form of:
Value= m λ
▪ Where m is scaling factor. For example, w=2 λ and s=3 λ for the min width
and spacing on layer
▪ One λ is generally the half of min feature size of the technology (length of
the transistor channel).

▪ For λ=0.15, the above values become,

▪ w=0.30μm and s= 0.45μm
▪ Changing to different value of λ means the change in the numerical values
for the dimension but the relative dimensions remain same.
▪ Good to interchange the same design between various technologies as per
their DR but the optimum packing density is not achieved

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4.5.1 Physical Limitation
• Presence of lateral etching in rvert limits the resolution that
can be achieved
•Absorption profile of light by the resist layer resulting in the
resist edges having finite slopes instead of well defined vertical
shapes

Figure 4.28 Etching profiles

(a) Resist pattern (b) Pure anisotropic etch. rlat =0, (c) Isotropic etch
A=1

Degree of Anisotropy:
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4.5.1 Physical Limitation: Semiconductor
Effects
• Depletion regions: Depleted of free electrons and holes because of the
electric field that originates from dopants and forces the charge out
• If the depletion regions of adjacent pn Junctions touch, then the current
blocking characteristics are altered and current can flow between the two
• This limits the spacing rule Sn-n

Limits on n+ spacing

• Electrical Capacitive Coupling: Cross talk in which a portion of energy from one line 52
is coupled to another causing NOISE
4.5.2 Electrical Rules

• These are in the form of changes to the basic design

rule values when certain electrical condition occur

• Line width with respect to reducing electomigration

effect for the flow of max current (larger current requires
wider lines

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