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The document outlines the final-term exam for the Algorithm to Silicon Mapping course at Sir Syed C@SE Institute of Technology, focusing on Verilog code generation for a switch/router in a Network-on-Chip and the architecture of a Very Long Instruction Word (VLIW) Processor. It includes detailed questions requiring students to generate code and design block-level architecture for both fixed and variable-length VLIW packets. The exam consists of two main questions with multiple parts, emphasizing practical coding and architectural design skills.

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7 views2 pages

RTL Font End

The document outlines the final-term exam for the Algorithm to Silicon Mapping course at Sir Syed C@SE Institute of Technology, focusing on Verilog code generation for a switch/router in a Network-on-Chip and the architecture of a Very Long Instruction Word (VLIW) Processor. It includes detailed questions requiring students to generate code and design block-level architecture for both fixed and variable-length VLIW packets. The exam consists of two main questions with multiple parts, emphasizing practical coding and architectural design skills.

Uploaded by

aqib2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Sir Syed C@SE Institute of Technology, Islamabad

Final-Term Exam – Fall 2024

Algorithm to Silicon Mapping(RTL Front End)


Dr Hamood

Total Marks:100 Time Allowed: 60min

Question 1(20+10+10)
Generate Verilog code for a switch/router in a Network-on-Chip fabric. The router acts on a simple 14 bit
packet having three fields: src (3 bit), dst (3 bits) and data payload (8 bits). Each router talks directly to its
four neighboring routers (through dedicated interfaces). Each also has a local port to its own processing
element (PE). Also generate a testbench and test your code.Also paste your prompt.

Question 2(20+10+5+5)
A Very Long Instruction Word (VLIW) Processor has 2 AGUs (Address Generation Units that operate on
the multi-ported data memory) and 4 integer ALU units featuring, add, subtract, multiply, MAC, logical
operations in each ALU unit. The processor has two 16x32 bit register files. One for the AGU and one for
the data path. There are two variations of the Instruction Set Architecture (ISA). In one ISA, unused fields
in a packet are marked as NOP, thus all VLIW packets are of the same size but have different number of
instructions. In the second variation the length VLIW packet changes (NOPs are not added) (this requires
an instruction alignment/fetch buffer). Also paste your prompt.

Some example assembly code in like RISC-V like format is given below.

// Demonstrates variable-length VLIW packets

// VLIW Packet Format:


// Each instruction has 6 fields (AGU1, AGU2, ALU1, ALU2, ALU3, ALU4)

// Initialize registers and memory addresses


LOAD R1, *0x100 // Load value from memory address 0x100 into R1
LOAD R2, *0x104 // Load value from memory address 0x104 into R2

// Packet 1: 2 Instructions (AGU1 and ALU1 only)


[LOAD R3, *AR0++ | ADD R4, R1, R2] // Load R3 and perform R4 = R1 + R2

// Packet 2: 4 Instructions (AGU1, AGU2, ALU1, ALU2)


[STORE R4, *0x10C | LOAD R5, *(AR0+AR1) | SUB R6, R2, R3 | MUL R7, R4, R5]

// Packet 3: 6 Instructions (All fields utilized)


[LOAD R8, *10(AR1) | STORE R6, *20(AR2) | ADD R9, R6, R7 | SHIFT_L R10, R9, 2 | AND R11, R8, R10
| MAC R7, R10, R11]

// Packet 4: 2 Instructions (AGU1 and ALU1 only)


[LOAD R13, *0x11C | OR R14, R11, R13]

// Packet 5: 4 Instructions (AGU1, AGU2, ALU1, ALU2)


[STORE R14, *0x120 | LOAD R15, *0x124 | XOR R16, R13, R15 | SHIFT_R R17, R16, 3]

// End of Program
HALT

Your goal is to draw the block level architecture of the processor for both variations (variable length
VLIW and fixe length VLIW).

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