Spring 2025 CA Lab-4

Namal University, Mianwali

Department of Computer Science
CSS-242L – Computer Architecture (Lab)

Lab -4

32-Bit Arithmetic Logic Unit (ALU)

& Its Implementation in Verilog

Student’s Name Gulfam Afzal

Roll No. NUM-BSCS-2023-31
Date Performed

Marks Obtained

Course Instructor: Lab Instructor:

Dr. Shafiq Ur Rehman Khan Engr. Majid Ali

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Document History
Rev. Date Comment Author
1.0 24/02/2025 Initial draft Engr. Majid Ali

Instructions

 Read the manual carefully before start of any tasks / experiments.

 Carefully handle all equipment available in the lab.
 Carefully write your particulars at first page on the manual.
 In case of simulation at PC, try to avoid opening of unnecessary tabs.
 Submit PDF report of each lab at Q-OBE, attach all findings in report properly.
 Write precise conclusion of every lab.
 Submission time is end of respective lab session for each manual, late submission of
manual is not acceptable.
 Fill manual individually even in case of group work.
 Plagiarism will be dealt with strict consequences.

Objectives

 The objective of this lab is to introduce students to the design and

implementation of a 32-bit Arithmetic Logic Unit (ALU) using Verilog.

Learning Outcomes

This lab satisfies the following learning outcomes of the course:

 CLO1: Follows fundamental computer architecture concepts through practical
laboratory exercises, following theoretical knowledge to design, measure, and
evaluate the performance of simulated architectural components.
 CLO3: Present concise and comprehensive technical reports

Equipment & Components

 Computer with Ubuntu OS installed.
 Icarus Verilog for simulation.
 GTKWave for waveform analysis.
 ModelSim Installed.
Introduction
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RV32I Instruction Formats:

 Instructions all 32-bits wide; must be 32-bit aligned in memory
 4 base formats (R/I/S/U) + 2 immediate-encoding variants (B/J)
 Register specifiers (rs2/rs1/rd) always in same place

Fig. 1: Core Instruction Formats

RV32I Arithmetic and Logical Operations

 Most arithmetic instructions use R-type format

 Perform the computation rs1 OP rs2 and write result to rd
 Arithmetic: ADD, SUB
 Bitwise: AND, OR, XOR
 Shifts: SLL, SRL, SRA
 Comparisons: SLT (rd = rs1 < rs2 ? 1 : 0), SLTU (same, but unsigned)

 Also have register-immediate forms using I-type format

 Perform the computation rs1 OP imm and write result to rd
 Same ones as R-type, but no need for SUB
 Arithmetic: ADDI
 Bitwise: ANDI, ORI, XORI
 Shifts: SLLI, SRLI, SRAI
 Comparisons: SLTI, SLTIU
 Immediate is always sign-extended (even when it represents an
unsigned quantity)

RV32I Memory Access Instructions

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 Loads also use I-type format

 Compute address rs1 + imm, read from memory, write result to rd
 LB, LH, LW: load byte (8b), load halfword (16b), load word (32b)
 LB and LH sign-extend the quantity before writing rd
 LBU, LHU (load byte unsigned, load halfword unsigned) zero-extend

 Stores use S-type format

 Compute address rs1 + imm; write contents of rs2 to memory
 SW stores all 32 bits of rs2; SB and SH store lower 8b/16b
 Note, imm[4:0] moves to bits 11:7 to accommodate rs2

RV32I Conditional Branches

 Branches use B-type format

 Same as S-type format, except immediate scaled by 2 (can only
branch to even-numbered addresses)
– Supports ISA extensions with instruction lengths in multiples of
2 bytes
 Compare rs1 and rs2; if true, set pc := pc + imm; else fall through
 Equality (BEQ/BNE), magnitude (BLT/BGE/BLTU/BGEU)

Arithmetic Logic Unit (ALU)

An arithmetic Logic Unit (ALU) is a combinational logic digital circuit that
performs arithmetic operations (Addition, Subtraction, Multiplication,
Division) and logical operations (AND, OR, NAND, NOR, XOR, XNOR, and
many more). ALU is also referred as the brain of a processor. The graphical
representation of ALU is represented in Fig. 2

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Fig.2: ALU

ALU
Functions Name
controls lines
0000 and AND

0001 or OR

0010 add ADD

0110 Sub Subtract

0011 not NOT

1101 xor XOR

0100 nand NAND

0111 nor NOR

1001 sll Shift Left Logical

1010 srl Shift Right Logical

1011 sra Shift Right Arith*

1000 slt Set Less Than

Table 1: ALU Control inputs and Operations

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Lab Task 1:

Design a 32-bit ALU that supports the operations listed in Table 1

Verilog Code: Testbench:

module ALU(A,B,controlin,zero,result); module Alu_TB;

input [31:0] A,B; reg [31:0] A,B;
input [3:0] controlin; reg [3:0] controlin;
output reg [31:0] result; wire [31:0] result;
output reg zero; wire zero;
always @(*)
begin
case(controlin) ALU
4'b0000: result= A & B; uut(.A(A), .B(B), .controlin(controlin), .re
4'b0001: result= A | B; sult(result), .zero(zero));
4'b0010: result= A + B;
4'b0110: result= A - B; initial
4'b0011: result= ~A; begin
4'b1101: result= A ^ B;
4'b0100: result= ~(A & B);
4'b0111: result= ~(A | B); A = 32'd5; B = 32'd4; controlin =
4'b1001: result=A<<B; 4'b0000; #10;
4'b1010: result=A>>B;
4'b1011: result= A>>B; // Test OR
4'b1000: result= (A<B)?1:0; controlin = 4'b0001; #10;
endcase
zero = (result == 32'b0) ? 1 : 0; // Test ADD
end controlin = 4'b0010; #10;
endmodule
// Test SUB
controlin = 4'b0110; #10;

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// Test NOT (only on A)

controlin = 4'b0011; #10;

// Test XOR
controlin = 4'b1101; #10;

// Test NAND
controlin = 4'b0100; #10;

// Test NOR
controlin = 4'b0111; #10;

// Test Left Shift

controlin = 4'b1001; #10;

// Test Logical Right Shift

controlin = 4'b1010; #10;

// Test Arithmetic Right Shift

controlin = 4'b1011; #10;

// Test Less Than

controlin = 4'b1000; #10;

$finish;
end

endmodule
Waveform:

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ALU Control
The ALU Control module is a crucial component in the design of an Arithmetic Logic Unit
(ALU) within a processor architecture. The ALU Control interprets control signals from the
instruction decoder to determine which arithmetic or logical operation the ALU should
perform. This allows the ALU to execute a wide range of instructions, from basic arithmetic
(like addition and subtraction) to bitwise operations (like AND, OR, and XOR). By processing
inputs such as aluOP, funct3 and funct7, the ALU Control can dynamically configure the
ALU to handle different operations based on the instruction set architecture (ISA). This
adaptability is essential for executing various types of instructions in a processor.

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Fig.3: ALU Control

ALUop
ALU Operation func7[30] func3[14:12] Control Output
(2 bits)
AND 00 0 000 0000

OR 00 0 001 0001

ADD 10 0 000 0010

Subtract 10 1 000 0110

NOT 10 0 111 0011

XOR 00 0 100 1101

NAND 00 1 000 0100

NOR 00 1 001 0111

Shift Left Logical 10 0 001 1001

Shift Right Logical 10 0 101 1010

Shift Right Arith* 10 1 101 1011

Set Less Than 10 0 010 1000

Table 2: Truth table for the 4 ALU control bits

Lab Task 2:
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Design an ALU Control module that generates a 4-bit control signal (Control Output) to direct
the ALU in performing specific operations.

Verilog Code: Testbench:

module ALU_control_tb;
reg [1:0] aluop;
reg [2:0] fun3;
reg fun7;
module ALU_control wire [3:0] cntrl_signal;
(
input [1:0] aluop, ALU_control uut
input [2:0] fun3, ( .aluop(aluop),.fun3(fun3),.fun7(fun7), .cntrl_sign
input fun7, al(cntrl_signal) );
output reg [3:0] cntrl_signal
); initial begin
aluop = 2'b00; fun3 = 3'b000; fun7 = 1'b0;
always @(*) begin #10;
case(aluop) aluop = 2'b00; fun3 = 3'b001; fun7 = 1'b0;
2'b00: begin #10;
case(fun3) aluop = 2'b10; fun3 = 3'b000; fun7 = 1'b1;
3'b000: cntrl_signal = #10;
4'b0000; aluop = 2'b10; fun3 = 3'b000; fun7 = 1'b0;
3'b001: cntrl_signal = #10;
4'b0001; aluop = 2'b10; fun3 = 3'b010; fun7 = 1'b0;
3'b100: cntrl_signal = #10;
4'b1011; aluop = 2'b10; fun3 = 3'b101; fun7 = 1'b1;
default: cntrl_signal = #10;
4'b0000; aluop = 2'b10; fun3 = 3'b101; fun7 = 1'b0;
endcase #10;
end aluop = 2'b10; fun3 = 3'b001; fun7 = 1'b0;
2'b10: begin #10;
case(fun3) aluop = 2'b10; fun3 = 3'b100; fun7 = 1'b0;
3'b000: cntrl_signal = #10;
fun7 ? 4'b0110 : 4'b0010; aluop = 2'b10; fun3 = 3'b110; fun7 = 1'b0;
3'b001: cntrl_signal = #10;
4'b1001; aluop = 2'b10; fun3 = 3'b111; fun7 = 1'b0;
3'b101: cntrl_signal = #10;
fun7 ? 4'b1011 : 4'b1010; aluop = 2'b10; fun3 = 3'b100; fun7 = 1'b1;
3'b010: cntrl_signal = #10;
4'b1000; $stop;
3'b100: cntrl_signal = end
4'b1100;
3'b110: cntrl_signal = endmodule
4'b1101;
3'b111: cntrl_signal =
4'b0111;
default: cntrl_signal =
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4'b0000;
endcase
end
default: cntrl_signal =
4'b0000;
endcase
end

endmodule
Waveform:

Conclusion
In this lab, we designed and implemented a 32-bit Arithmetic Logic Unit (ALU) using
Verilog, supporting various arithmetic and logical operations. We also developed an ALU
Control module to generate control signals based on instruction formats. The implementation
was verified using testbenches and waveform analysis in Icarus Verilog and GTKWave. The
results confirmed correct functionality, demonstrating the practical application of RISC-V
ALU operations. Overall, this lab enhanced our understanding of computer architecture and
digital circuit design.

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Marks
Domain Criteria Excellent (10) Good (8-9) Satisfactory (6-7) Improvement (4-5)
Obtained

RISC-V
Designed an efficient Implemented the Designed a basic Incomplete or
Psychomotor Datapath in
RISC-V datapath with RISC-V datapath datapath with some incorrect design with
(P3) HDL
correct functionality with minor errors issues major errors
(CLO-1)

Report Presented Provided basic Unable to answer

Writing Presented outstanding comprehensive answers in reports questions and had
(CLO-3) and detailed reports. reports with some with limited significant knowledge
Affective (A2)

minor gaps. knowledge gaps. gaps.

Answered questions Answered

Answered questions
confidently and questions Unable to answer
Lab Viva with basic
showed exceptional comprehensively questions and was not
(CLO-3) understanding and
knowledge and and exhibited confident.
limited knowledge.
comprehension. strong knowledge

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