Objectives

● Design and implement a combinational 16 Bit ALU

● Implement a test bench that tests the ALU
● One partner to use Verilog, and the other is to use VHDL.
 Procedure
● Using combinational logic implement a simple ALU that
conforms to the truth table given.
● Name your entity/module “ALU”
● Start with the provided ALU template in the course shell.
 Procedure
● Your ALU will have the following interface:
● ABUS[15:0] – A input bus (unsigned)
● BBUS[15:0] – B input bus (unsigned)
● FOUT[15:0] – Function Output (unsigned)
● FSEL[3:0] – Function select Input (std_logic_vector)
● Z,S,C,V – Status flags output. (std_logic)
● CIN – Carry In (std_logic)
 Procedure
ABUS[15:0] BBUS[15:0]

ALU

FSEL[3:0] Z
S
CIN C
V

FOUT[15:0]

5
 Procedure
● Pay Close attention to the status flag outputs, and how they are
implemented. Status outputs need to be valid for all functions.
● S – is a copy of the MSB of FOUT
● Z – is a '1' when FOUT == 0
● C – is a '1' when there is a carry out from any operation, or it contains
the bit shifted out from the input.
● V – is a '1' when there is an overflow condition present after an
operation. (Note: This also includes shifting operations.)
● Remember that the ALU should be combinational, be sure to
pay close attention to sensitivity lists and don't infer latches in
your design.
 Procedure
● VHDL:
● Remember that the data buses should be of type unsigned.
● The FSEL input should be of type std_logic_vector.
● Status flag outputs should be of type std_logic.
● Remember you cannot read from output signals in VHDL, so you may
have to introduce variables to hold the output value.
● When running the test bench, if you experience many test failures, or
no output, verify that the time in the simulator is moving forward, and
that you are running the simulation long enough. Each test in the
VHDL simulation is set to take 1ns, so simulate at least 100ns of time.
 Procedure
● Verilog:
● Outputs may have to be declared as reg in order to be written to.
● It is bad form to read from outputs in Verilog, I would suggest using
internal reg items to hold values temporarily.
 Procedure
● Truth Table:
Name Code Function
TSA 0000b Transfer ABUS
INC 0001b Increment ABUS by one
DEC 0010b Decrement ABUS by one
ADD 0011b Add ABUS+BBUS+CIN
SUB 0100b Subtract ABUS-BBUS-CIN
AND 0101b Bitwise ABUS AND BBUS
OR 0110b Bitwise ABUS OR BBUS
XOR 0111b Bitwise ABUS XOR BBUS
NOT 1000b Bitwise NOT ABUS
SHL 1001b Shift ABUS left, C contains ABUS[15], FOUT[0] contains 0.
SHR 1010b Shift ABUS right, C contains ABUS[0], FOUT[15] contains 0.
ASR 1011b Arithmetic Shift A right, Bit C contains ABUS[0]
RLC 1100b Rotate Left through Carry, FOUT[0] contains CIN, C contains ABUS[15]
RRC 1101b Rotate Right through Carry, FOUT[15] contains CIN, C contains ABUS[0]
RV1 1110b Reserved 1 (Can set FOUT = all 'X, or implement something custom.)
RV2 1111b Reserved 2 (Can set FOUT = all 'X, or implement something custom.)
 Procedure
● There are two reserved codes, it's up to you how these behave.
● I suggest you assign the outputs to 'X' values for these two operations.
● This will tell any synthesis tool that the outputs are don't cares for
these cases, and will result in simpler generated logic.
● You will need to do research to understand how all the
operations work in the ALU.
 Shifting
C Rn-1 Rn-2 Rn-3 ⋯ R2 R1 R0

Rn-2 Rn-3 R0 Shift Left Rn-1 R2 R1 Shift Right

⋯ 0 0 ⋯

Arithmetic Shift
Rn-1 Rn-1 ⋯ R2 R1 Right

Rotate Left
Through Carry

Rn-2 Rn-3 ⋯ R0 CIN Rn-1

Rotate Right
Through Carry
R0 CIN Rn-1 ⋯ R2 R1
 Procedure
● Test Bench
● In your test bench, instantiate the ALU and connect signals to it's
inputs and outputs.
● As part of the test bench, apply test vectors to the inputs, wait for a
short delay, and then check that all the ALU outputs match the
expected values.
● I have 64 vectors defined for my test bench.
● Use the provided test bench as a starting point.
 Evaluation – ALU
● Demonstrate your ALU works by showing a passing test bench.
● Upload your Verilog, and VHDL source code in a zip file to the
associated drop box.
● I will simulate your ALU code against my test bench to verify
functionality, using my vectors.
● NOTE: your entity/module MUST be 'ALU', if I cannot verify your
design, you will not earn marks.
● I will also use your test bench to test my design, to see how
thorough you have been.
 Evaluation – ALU
● Basic Outcomes (55% to 70%)
● Creating an ALU, and associated test bench code that shows some
level of functionality will earn minimum marks.
● Maximum marks are obtained for an ALU that passes your own test
vectors.
 Evaluation – ALU
● Intermediate Outcomes (70% to 80%)
● Basic outcomes are met, and your test bench uses my vectors will
earn middle marks.
● If your ALU passes all my test vectors, then you will earn maximum
marks.
 Evaluation – ALU
● Advanced Outcomes (80% - 100%)
● In addition to 100% passing my test vectors you extend the test bench
to include additional functionality.
● Examples of additional functionality include (and are not limited to, be
creative!):
– Random value testing
– Demonstrated use of functions and procedures that are available in Verilog and
VHDL. (To make the code more readable)
– Counting of test failures, with a report at the conclusion (or during) the
simulation of failing test vectors.