Digital VLSI Circuit Design –

Verilog HDL

Dr. Yushi Zhou

Electrical and Computer Engineering

Email: yzhou30@lakeheadu.ca
HDLs’ History
• 1971-ISP
– Introduce the concept of Register Transfer Level (RTL)
– no synthesis
• 1985-Verilog
– Develop by Gateway(acquired by Cadence)
– Similar to C language
– IEEE standard
• 1987-VHDL
– Request from U.S. Department of Defence
– More structural than Verilog but verbose
– IEEE standard
• Now
– Verilog-95, Verilog-2001, System Verilog
– VHDL-1987, … VHDL 2008
• Ref
– https://en.wikipedia.org/wiki/Verilog
– https://en.wikipedia.org/wiki/VHDL
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Design Methodology
• Structural and behavioral Inputs

• Simulation
Functional verification HDL description
• Synthesis Timing verification
Netlist (gate level) verification
• Place and Route Simulation

Mapping Verilog to logic

gates and transistors Synthesis

Place the modules and

P&R
making connections

Fab
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Verilog Language
• One of the two most commonly-used HDL
in digital design
• Using text rather than pictures to describe
a circuit or

Is it possible to draw billions

transistor?

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Verilog module
• A Verilog description is included in a
module
;

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Two Main Data Types
• wire (refer to combinational logic)
– Represent electrical connections between blocks, using assign
– Cannot be assigned in an initial or always block
– Used for left hand side
• reg (refer to sequential logic and combinational logic)
– Behave like memory, DFF in a computer
– Hold the value until explicitly assigned in an initial or always
– Synthesized to latches, flip-flops, but not necessary
– Used for left hand side(LHS)

Verilog 2001

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Cont.
• Integer
– Converted to right number of bits automatically if stored in a scalar or vector
• Scalar
– A single wire or reg, holding 1 bit
• Vector
– A wire or reg with more than 1 bit
• Array
– A 2-dimentional array of wire or reg
– Often used in a testbench
• A test bench is a source file that is used to instantiate the designed module, generate test vectors,
and collect the output puts from the module
– Not preferred for synthesis

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Verilog description
• Structural vs. Behavioral
– Structural Description
• Similar to the schematics but using text
• List of gates and their connections
• A natural representation of a digital logic circuit
• Hard to understand and to write
• Suitable for module connections
– Behavioral Description
• Describe what the function of the component is, like C
• Much easier to understand and to write
• Always preferred
• But not all behavior statements are synthesizable
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Verilog general
• Character sets
– 0-9, A-Z, a-z(case sensitive), _ $
– All keywords are in lower case
– Exp.:

• Comments
– Single line comments: //
– Multiple line comments: /* comment*/
– Exp.:

• White space
– Space(\b), tabs(\t), newlines(\n)
– Used in strings
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Data Values
• Constants
– Specified by number of bits and value
– Integer values are truncated to fit variable size
– Exp.: <size>'<radix><value>

• Parameters
– Given a constant value
– Can be overridden when a design is complied
– Exp.:

• Strings – not synthesizable

– Store in reg, 8 bits per character

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Statements
• Statement delimiter
– End of statement is a “;”
– Returns do not affect the statements
– Multiple statements using the same form can be
grouped and distinguished by commas(not
recommended)

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Operators – Three Types
• Unary operators
– On the left of their operand
• Binary operators
– In the middle of their operands
• Ternary has three operands by two operators(conditional assignment)

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Operators Summary-1

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Operators Summary-2

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Four – Valued Logic
• Verilog logic values
– 1, 0, Z(high impedance), X(unknown)
– X: one of 1, 0 , Z or in the state of change(unknown).
It is not a real value, no real corresponding gate. It is
simply meaning “don’t care” whatever the value
– Z: the high impedance output of a tri-state gate
Truth table
NAND 0 1 X Z
0 1 1 1 1
1 1 0 X X
X 1 X X X
Z 1 X X X
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Structural Design
• Top module
– The top of the synthesized code
– Comprises of other modules with different
functions
• This is the file where structural description is required
– Define the chip I/O signals
• Sub-modules
– Function units, e.g. multiplier, adder, filter, etc.
– Memories, e.g. SRAM, register array, etc.
– Other IPs, e.g. decoder, encoder, etc.

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Design and Test
• Construct a “test bench” for the design
– Generate test vectors
– Monitor the outputs of the design under test
(DUT)
– Create a “testbench.v” file, which incorporate
vector generation, outputs monitor and DUT.

16
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Half Adder Example
Truth Table
A B S C
A B
0 0 0 0
C 0 1 1 0
1 0 1 0
1 1 0 1
S

S = A xor B
C = AB

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Half Adder Example (1)

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Half Adder Example (2)

$monitor: print string when executed and when

any one of the listed values changes . Only one
$monitor can be used in test bench. Binary,
%d:decimal

@Time 0, print out a,b,summ, cout, and a=b=0

@Time 5 ns, print out a,b,summ, cout, and b=5

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Primitives in Verilog
• Verilog supports basic logic gates as
primitives
– and, nand, or, nor, xor, xnor, not, buf
– Bufif1 and bufif2 are tri-state buffers
• Using Net(wire) represents connections of
primitives

sel out
0 b
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Continuous Assignment
• Key word: assign
• Represent combinational logic
• RHS* is continuously evaluated like data flow
• LHS* must be a scalar or vector net not reg

*RHS/LHS: right hand side and left hand side

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Procedural Verilog
• Using always and initial construct
• always is synthesizable, initial is not
• They all execute concurrently with arbitrary
order, but inside always and initial,
statements are executed sequentially
• Can specify combinational and sequential
circuits
• Order is important

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Procedural with always
• High-level behavioral description of
combinational logic
Not a latch and DFF

Multiple statements must be enclosed in begin..end

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Cont.
• In a module, there can be more than one
always statements
• Two separate always cannot calculate the
same function

Not allowed

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Behavioral Statements
• if(condition is true) else
– Four value logic. 1 is “true”, 0, X, Z are “false”
• case is similar to if else but easy to read than a
long if else

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Combinational Circuits - 1
• Combinational: the output is only a function
of the inputs(not the previous value)
Wait for any change on a,
b, or sel, then execute the
begin-end block. Then
wait for another change.

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Combinational Circuits - 2
• A reg type variable is not a
register in comb. circuits
– The synthesis tool translates
it as a combinational circuit
– So, reg is artificial in this case
– Inside always, LHS must be
reg type

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Combinational Circuits Style

• Combinational circuits follow this template:

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Rules for Combinational Logic
• Every element of the input sets must be in the
sensitivity list, e.g @()
• The combinational output must be assigned in
every control path

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Incomplete Specification - 1
• Infer latches

We want 3-1 mux We code

a 00
b 01
c out
10

sel

Combinational logic
Correct?
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Incomplete Specification - 2

a 00 out
b 01 D Q
c 10

Incomplete
case list, missing
sel 2’b11

Sel0,1
If out is not assigned in this case, the
previous value will be retained, inferring
latches. Avoiding inferred latches all the
time
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Incomplete Specification - 3
• Solution
– Complete the all the cases, e.g. complete if…else and
case
– Given default value

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Incomplete Specification(4)
• One more example
BAD Good

Missing other bits

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Incomplete Specification - 5
• More example

BAD

No default values
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Incomplete Specification - 6

Good

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More Complex Examples

A FSM, will see in

the following slides

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 A Full Adder
cin A B S cout
0 0 0 0 0
A B 0 0 1 1 0
COUT CIN 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
S
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Build truth table→

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A Full Adder Implementation – 1
• Behavioral implementation
• Module fulladder2bits

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A Full Adder Implementation - 2
• Structural Approach
– Design a Half Adder(we’ve learned)
– Cascade two Half Adders → 1 bit Full Adder
– Cascade n Full Adders → n bits Full Adder
1-bit Half Adder- module halfadder

1-bit Full Adder-module fulladder

Multi-bit Full Adder- module fulladder2b

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A Full Adder Testbench
• Instantiate two 3-
bits Full Adder
– Behavioral Verilog
Initialization(remove
– Structural Verilog these three
statements, see
– Compare the output again)
results

Are they same?

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 A Full Adder Simulations
Q1: Which one is correct?
Q2: Why it happens?

Simulated on ModelSim 10.5

A tutorial of how to use ModelSim can be found in the lab manual.

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Multiplier
• How to implement a “*”, multiplication
– In digital world, it is simple
– 0*1=0, 1*1=1→ AND gate
– N-bit * M-bit→(N+M) bits of product
Unsigned 3-bit multiplication
A[2:0] B[2:0] A2 A1 A0
* B2 B1 B0
A2B0 A1B0 A0B0
+
A2B1 A1B1 A0B1
+
P[5:0] A2B2 A1B2 A0B2
P5 P4 P3 P2 P1 P0

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 Multiplier Structure
A2 A1 A0
* B2 B1 B0
A2B0 A1B0 A0B0
+
A2B1 A1B1 A0B1
+
A2B2 A1B2 A0B2
P5 P4 P3 P2 P1 P0

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 Multiplier Implementation(1)
• Unsigned multiplication

Nothing but *

Why this?
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Multiplier Implementation(2)
a b
• 110*011=110*(0*22+1*21+1*20) 20=no shift
21=shift left 1 bit
• 110*111=110*(1*22+1*21+1*20) 22=shift left 2 bits
23=shift left 3 bits
…
2N=shift left N bits

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Multiplier Testbench

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Multiplier Simulation

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Priority Logic (1)
• Beware of priority coding
– Different coding style infers different logic gates
– See example

A 4-to-2 one-hot-code decoder

A3 A2 A1 A0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
others Don’t care

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Priority Logic (2)
We want We get

• Unintended priority logic (if else/case)

– a[0] has the highest priority
– a[1] has the second highest priority
– So on.
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Priority Logic (3)
• If else and case are parallel
– Mutually exclusive conditions for each branch
– Synthesize tools give better result

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Behavioral Statements-Loops
• for…end/while
– Synthesizable, but DO NOT USE IT
– Best applicable situation is to use it in a testbench,
not for a circuit design
• repeat/forever
– Not synthesizable

What’s problem here?

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Verilog Timing (1)
• Three types
– #<delay><event>
• Only for simulation purpose
• Not for synthesis

– @<edge-triggered event>
• For procedural code
• Process is triggered when the correct edge happens

– Wait(<signal has high level>)

• Process is triggered when the high logic occurs
• Not for synthesis

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Verilog Timing (2)
• always and initial
– Initial starts at time=0
– always starts when
meet the condition
• always
– always: this will run
forever
– always @(a or b):
runs when a or b
changes
– always @(posedge
clk): runs at each
rising clock(synthesize
to flip-flops

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Verilog Timing (3)

• initial
– Initial is not
synthesizable
– initial is used for
test bench
– Initialize variables

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Sequential Logic
• Combinational logic circuits
– The output of a logic block is only the function of
the current input values
– No memory
– E.g. NAND, NOR and NOT
• Sequential logic circuits
– The output of a logic block is the function of current
inputs and preceding input values
– Has memory
– e.g. latches(level sensitive) and registers(edge
triggered)

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Delay of An Inverter
• tpdr: rising

Input of a inverter
propagation delay
– From input to rising
output crossing VDD/2
• tpdf: falling

output of a inverter
propagation delay
– From input to falling
output crossing VDD/2
• tpd: (tpdr+tpdf)/2

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Timing Metrics for Sequential Circuits
• Setup time: tsu
– The time that the data input(D) must be valid
before the clock transition (0→1 for positive edge
triggered register, 1→0 for negative edge triggered
register)
• Hold time: thold
– The time that the data input(D) must be retained
valid after the clock edge
• Propagation delay(clock to Q): tcq
– The time that the data at D input is transferred to
the Q output
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tsu,thold, tcq

register
D Q

CLK

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Setup and Hold Time Violation
• What happens if failure of setup and hold time occurs?
– The D flip-flop enters a state where its output is unpredictable,
e.g. not “1” or “0”
– Called metastability
– How long D flip-flop can be recovered from metastable states is
unknown
– It happens in asynchronized system→ avoid asynchronized Sys.

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Dealing with Metastability
• Sometimes asyncrhonized design cannot be
avoided, e.g. traffic light button
– Using double synchronizer to minimize the
probability of metastability of a DFF

From external Can be metastable Very unlike to be metastable

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A Synchronized Circuits – One CLK
Chip Boundary
Comb:
sequential: adders sequential
reg multipliers comb
Q Q Q

tcq tpd_comb tsu

tCLK>tcq+tpd_comb+tsu thold<tcq+tpd_comb
Determine minimum time
period of a clock
Exp:
tcq=200ps
tsu=100ps
tpd_comb=1000ps
tCLK_min=200+100+1000=1300ps
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 Pipelining
td=(td1+td2+td3) < Tclk td1<Tclk td2<Tclk td3<Tclk
REG

REG
a a

REG

REG

REG
REG
CLK + log Out CLK + log Out

REG
REG

b CLK b CLK CLK CLK

CLK Reference CLK Pipelined

Latency:
3 clock cycles
Ref: [J.Rabaey02]

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Sequential Logic in Verilog
• always is often used to construct sequential circuits
– edge triggered circuits is for synchronized design

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Posedge/Negedge DFF

• Sometimes may not have negative edge triggered DFF in

library
• Avoid using positive edge triggered DFF and negative
edge triggered DFF in the same design
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Synchronized and Asynchronized Reset
• Sensitivity list in always determines the synthesis
results
– Edge triggered key words, posedge/negedge

Register with asynchronize reset Register with synchronize reset

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Synchronized Reset(1)
• Name convention
– Active low is named with suffix _n
• if reset = 1’b0, out is
assigned to 0
@positive edge of
clock.
• if reset =1’b1, out is
assigned to a
@positive edge of
clock
• Also you can use
if(~rst_n)
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Synchronized Reset(2)
• Timing diagram example

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Synchronized vs Asynchronized Reset
• Synchronized resets
– Ensure circuits are 100% synchronous
– Ensure reset can only occur at an active clock edge
– Remove any glitches on reset signal unless the
glitches are near the active clock edge
– Use more area
– May cause timing issue in data path
– Preferable technique in most of the designs
• Asynchronized resets(if in library)
– Better timing in data path
– Can reset circuits without clocks
– But it may cause metastability issue
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Blocking Assignment
• Two types assignments within always blocks, inferring
different behaviors
– “=“ and “<=“
• Blocking assignment “=“
– Evaluate and assign are happening immediately
– The next assignment awaits(is blocked) until the present
assignment is completed

1. Evaluate a&b, assign result to x

2. Evaluate a|b|c, assign result to y
3. Evaluate ~a, assign result to z

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Nonblocking Assignment
• Nonblocking assignment “<=“
– All assignments are executed until right hand
sides have been evaluated

1. Evaluate a&b,
2. Evaluate a|b|c
3. Evaluate ~a
4. Assign x,y,z

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Shift Registers
• Are they same?

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Nonblocking for Sequential Circuits

a_d1 and out simultaneously update the old

value at each rising edge of clock

out

At each of rising edge of clock, a_d1=a. then

out=a_d1. therefore, out = a
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Counter Example
• A 3-bit modulo 6 counter

testbench
Source code

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sim
Using Blocking and Nonblocking
• Use blocking, “=“, for combinational logic
circuits
• Use nonblocking, “<=“, for sequential logic
circuits

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S-to-P and P-to-S (1)
• Series to parallel conversion
• Parallel to series conversion
• Often used in a storage device in microprocessor or
ASIC

S-to-P

For parallel to series, one more MUX is required

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S-to-P and P-to-S (2)
• Integrate S-to-P and P-to-S
• Signal SP determines the current status
– SP=0, it is in series to parallel conversion
– SP=1, it is in parallel to series conversion

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S-to-P and P-to-S (3)
• S-to-P • P-to-S

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S-to-P and P-to-S (4)
• P-to-S full example

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Finite State Machine(FSM)
• Most useful abstraction for sequential
circuits
• FSM is defined by its next-state

State graph

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Two Types of FSM
• Moor state machine: the outputs are only a
function of the present state
• Mealy state machine: one or more of the outputs
are a function of the present state and one or
more of the inputs

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Coding Styles of FSM
• One always
– State transition, next state generation and output
are in the same always blocks
– NOT recommended since it is hard to maintain
• Two/three always
– Easiest method to implement FSM
– Exactly same as the FSM diagram
– Distinguish clocked present state logic, next state
combinational logic and output combinational logic
– Must define very clear FSM state generation

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One always Block

BAD

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Three always Blocks(1)

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Three always Blocks(2)

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Common Errors in FSM
• No default state → inferring unintended
latches, e.g default next_state=2’b00
• Incomplete branches → inferring unintended
latches, e.g. if..else if ..
• Inappropriate sensitive list → incorrect
function
– (state or data_in): state is missing, resulting in
wrong state transition
– X = A+B: x is listed in ()

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A FSM Example – MIT Open Course
• Goal:
– Build an electronic combination lock with a
reset button, two number inputs buttons(0
and 1), and an unlock output. The key
password is 01011.

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Step 1: Block Diagram

• Synchronized design
• Asynchronized signals from external must be synchronized first
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 Step 2: State Transition Diagram

Button input

Unlock indicator

We need correct input, 01011, to unlock it,

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Step 3: Blocks in Verilog

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Step 3A: Synchronizer

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Step 3B: State Transition

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Step 4: Testbench

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Step 5: Simulation Results

0 1 0 1 1 Unlock
indicator

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Common Rules for Verilog Coding(1)
• Have a block diagram ready before coding
• Have a timing schedule ready before coding
• Have a pin definitions ready before coding
• Keep same naming convection and coding style for the entire design
• Add comments for each statement and block
• Use lowercase letters for all signal, variable, and port, e.g. reg a, b ;
• Use descriptive names, e.g. fsm, clk, ram, etc.
• Use clk for clock signals, e.g. clk1, clk2, etc.
• Use rst for reset signals
• Active low signals postfix with _n
• Use convention bits order, e.g. [MSB:LSB]
• Each .v file should only contain one module/endmodule
• Pins’ order should follow input and output
• No glue logic in top level module, i.e. using hierarchy

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Common Rules for Verilog Coding(2)
• Continued code lines should be indented
• Do not mix rising edge triggered register with falling edge
triggered register in the same design
• Use behavioral description rather than structural description for
reuse purpose
• Use rational partition
• Avoid incomplete sensitivity list(you may use always @*, but not
preferred)
• Given default values for case/if statements
• Never use loop statements in your design
• Avoid using large FSM
• Use three always type FSM
• Use Moor rather than Mealy FSM
• Better to use registered output signal

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 A FIR Filter Design
• Goal:
– Build an FIR filter with Fs(sampling
frequency)=10MHz, Fc(cut-off
frequency)=0.1MHz, hamming window, 8 order
– Use minimum resource to implement the FIR
filter, i.e. the less multipliers or adders, the
better
– Verify the RTL simulation results, comparing to
the Matlab data

2023-10-23 Email: yzhou@ee.ryerson.ca 97

 FIR Coefficients(1)
– Matlab

FIR Order

FIR Window

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Click design Fs and Fc 98
 FIR Coefficients(2)
• Use Matlab to generate floating point
coefficients

Convert to binary
See next

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 FIR Coefficients(4)
• Floating point to fixed point data
– Normalize to the max(abs(fir coefficients)) so that
the maximum coefficient is 1
– Multiply the maximum dynamic range of the data,
determined by the number of bits, e.g. 2^(N-1)-1 or
-2^(N-1)
• Convert decimal data to binary data using 2’s
complement format if you have negative
coefficients
original

Normalized

Decimal
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 FIR Architecture(1)
• Convolution

• Direct Form

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 FIR Architecture(2)
• Even Number Coefficients→ Symmetric
structure
– Coefficients h0=h7,h1=h6,h2=h5,h3=h4
– Give rise to better structure than direct form

2023-10-23 Email: yzhou@ee.ryerson.ca 102

 FIR Architecture(3)
• Optimized structure
– Do addition first: x(0)+x(7), x(1)+x(6), x(2)+x(5), and
x(3)+x(4)
– Then multiply h(0),h(1),h(2) and h(3)

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 Sequencing Graph(1)
• Determine the resource binding and
timing schedule

7 Adders
4 Multipliers

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 Sequencing Graph(2)
• Optimize to less resources

4 Adders
1 Multipliers

What’s the cost?

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 Timing Diagram

Latency is 8 clock cycles

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 FIR Symbol

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 Pin Descriptions
PIN NAME I/O DESCRIPTION

Fir_rst I global reset signal

Fir_clk I FIR module clock (50MHz)

Fir_ena I FIR module enable signal

Fir_din_nd I New data in indicator

Fir_din [7:0] I FIR input data

Fir_busy O FIR module busy signal

Fir_end O End computation signal

Fir_dout_nd O New data out available signal

Fir_dout [20:0] O Fir output data

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 FIR Block Diagram

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 FIR Implementation
• Use what you’ve learned to code
• May need $fopen, $fwrite, $fclose in the
Testbench to write output data to a file

Start

End

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 FIR Verification
• Compare
Matlab to RTL
simulation
– If they are
equal, the
design is
completed
– If not, go back
and check

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Most Important: You are a HARDWARE
designer not a SOFTWARE designer

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References

1. MIT Open course

2. “The Verilog Golden Reference Guide”,
DOULOS, 1996
3. Textbook

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