Verilog Labs & Homework

© 2016 Synopsys, Inc. 1

 Lab 1 – 1 bit full adder

• Use Karnaugh Map to derive logic expression for the addition.

• Create the file OneBitAdder.v
– Write the Verilog code that implements binary addition operation based on the expression obtained
previously
• Use the following interface
a b cin sum cout
1 module onebitadder ( 0 0 0 0 0
2 input a, b, cin,
0 0 1 1 0
3 output sum, cout
4 ); 0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

© 2016 Synopsys, Inc. 2

 Lab 2 – Basic modules

• This lab will consist on creating some basic designs (modules).

• A description of the design functionality will be provided.

• The objective is to translate the description into a synthesizable Verilog code.

• It is very important to use the module interface that will be provided.

• In order to do a syntax check on the Verilog code written, vlogan tool can be used. The
following line can be executed on the shell

vlogan <verilog_file.v> –full64 –sverilog +v2k

© 2016 Synopsys, Inc. 4

 Lab 2a – Parameterized 4-input MUX

• Write the Verilog code that implements a 4-input multiplexer (mux) with variable (parameterized)
input and output bus width.

• Use the following interface

1 module mux4 #(
2 parameter WIDTH= 8 din1
3 ) ( din2
dout
4 input [WIDTH-1:0] din1, din2, din3, din4, din3
5 input [1:0] select, din4
6 output [WIDTH-1:0] dout
7 );
select

© 2016 Synopsys, Inc. 5

 Lab 2b – Parameterized Register Bank

• Write the Verilog code that implements a D-type Register Bank with parameterized depth. It
should:
– Operate on positive edge of the clock (clk)
– Have a Synchronous reset (rst)
– Have an enable signal (wr_en) which allows data capturing only when asserted.

• Use the following interface

1 module register_bank #( in[0]
2 parameter WIDTH = 8 in[1]
3 ) ( in[2]
4 input [0:0] clk, in[3] out
5 input [0:0] rst, in[4] 8
6 input [0:0] wr_en, in[5]
7 input [WIDTH-1:0] in, in[6]
8 output [WIDTH-1:0] out in[7]
9 ); clk

wr_en rst
© 2016 Synopsys, Inc. 6
 Lab 2c – Basic ALU
• Write the Verilog code for a basic ALU module (Arithmetic Logic Unit).
– This ALU has to have addition, subtraction, multiplication and division operations.
– It should have two variable (parameterized) width inputs and output bus in accordance.
– Signal zero[0] should be asserted when the result of the current operation is 0.
– Signal error[0] should be asserted when dividing by 0 is attempted or when input data is not valid.
– On error condition, output must be forced to be -1
– Operations should be described using Verilog arithmetic operators.

• Use the following interface

1 module ALU #(
2 parameter WIDTH = 8
3 ) (
4 input [WIDTH-1:0] in1, in2,
5 input [3:0] op,
6 input [0:0] nvalid_data,
7 output [2*WIDTH-1:0] out,
8 output [0:0] zero,
9 output [0:0] error
10 );
© 2016 Synopsys, Inc. 7
 Lab 3 – Full Design Simulation
• The objective is to create a basic multicycle processor as shown in the diagram below.
– Modules previously designed should be used. (Mux, ALU, Regbank)

zero
d_in1 2
d_in2 error
Mux A
d_in3 w

alu
{dout_high, dout_low}
2w

Mux B

2w 4
reset
clk

cmdin
control
6

© 2016 Synopsys, Inc. 8

 Lab 3 – Full Design Simulation (cont.)
• Specifications of the design:
–This is a multicycle processor (3 stages) with no pipelining.
–It has 3 variable with input buses to be used as operands.
–The ALU has 2 multiplexed inputs:
– Each MUX is feed by the 3 input buses and the ALU output.
– Details on how to control the ALU are available in Lab 2d.
–Both reset (rst) and clock (clk) signals should be connected to every module that uses
them.
–It has a control unit feed by a 6 bit word (cmdin). This control unit has to:
– Enable the register stages only when applicable
– Select the outputs of each MUX
– Provide the control signals for the ALU.
– Inverted valid data signal must be asserted when data is feed from the feedback loop and the previous result
was not valid (Error condition)
– OPCODE to select the operation performed by the ALU.

© 2016 Synopsys, Inc. 9

 Lab 3 – Full Design Simulation (cont.)

• The control block shall be designed to implement the following Instruction Set Architecture
(ISA): cmdin
5 4 3 2 1 0

muxA muxB opcode

• The opcode bus should be decoded according to the following table:

opcode[1] opcode[0] Operation

0 0 Add
0 1 Sub
1 0 Mul
1 1 Div

© 2016 Synopsys, Inc. 10

 Lab 3 – Full Design Simulation (cont.)

• The control module

– Write the Verilog code for implementing this module based on the details and ISA provided previously.
– Write a test bench to validate this module. It should cover all possible operations, corner cases and
exercise all outputs.
– Its interface should be as follows:
1 module control (
2 input wire [0:0] clk,
3 input wire [0:0] rst,
4 input wire [5:0] cmd_in,
5 input wire [0:0] p_error,
6 output reg [0:0] aluin_reg_en,
7 output reg [0:0] datain_reg_en,
8 output reg [0:0] aluout_reg_en,
9 output reg [0:0] nvalid_data,
10 output wire [1:0] in_select_a,
11 output wire [1:0] in_select_b,
12 output reg [4:0] opcode
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 Lab 3 – Full Design Simulation (cont.)
• Full design
– Write the Verilog code that implements this simple microprocessor. At this point it is mostly about
connecting together all the modules created so far.
– A test bench will be provided.
– Its interface should be as follows
1 module top #(
2 parameter WIDTH= 8
3 ) (
4 input wire [0:0] clk,
5 input wire [0:0] rst,
6 input wire [5:0] cmdin,
7 input wire [WIDTH-1:0] din_1,
8 input wire [WIDTH-1:0] din_2,
9 input wire [WIDTH-1:0] din_3,
10 output wire [WIDTH-1:0] dout_low,
10 output wire [WIDTH-1:0] dout_high,
10 output wire [0:0] zero,
10 output wire [0:0] error
11 );
© 2016 Synopsys, Inc. 12
 Lab 4 – Line Code Coverage Simulation
• Generating Coverage
Line code coverage can be enabled as shown below:

 vcs –cm line –f filelist.f ……… \

[–cm_dir comp_covdir.vdb] \

 simv –cm line ……… \

[–cm_dir run_covdir.vdb] \
[-cm_name test1]

© 2016 Synopsys, Inc. 13

 Lab 4 – Line Code Coverage Simulation (Cont.)
• Load coverage database in Verdi:
 verdi –cov –covdir simv.vdb

© 2016 Synopsys, Inc. 14

 Practice for you learn (Homework)
• Copy Lab4 to a new directory homework.
 Choose 3 VCS features you learn to run of VCS
 Choose 3 Verdi features you learn to debug of Verdi
 Submit homework (Text to describe what benefit for you using the 3 features
of VCS and Verdi) under:
[External] IC Design Summer Workshop 2021 > Channel: “VCS & Verdi” > Files > Folder: “Homework”.
Please label the file name as : 學號+姓名
Thanks,

© 2016 Synopsys, Inc. 15

Thank You