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ALU Design

This document specifies an 8-bit ALU with 2 input lines, 1 output line, and 1 select line that can perform addition, subtraction, shifting, rotation, and logical operations based on a 4-bit select line. It provides the port definitions, operation codes for the select line, Verilog code for the ALU module and testbench, and confirms that all 100 random tests passed without failure.

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Vishnu Sasidharan
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147 views6 pages

ALU Design

This document specifies an 8-bit ALU with 2 input lines, 1 output line, and 1 select line that can perform addition, subtraction, shifting, rotation, and logical operations based on a 4-bit select line. It provides the port definitions, operation codes for the select line, Verilog code for the ALU module and testbench, and confirms that all 100 random tests passed without failure.

Uploaded by

Vishnu Sasidharan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MINI PROJECT A-3 :ALU

SPECIFICATION:

8 Bit ALU.
2 input lines, 1 output line, 1 select line.
Functions : Addition, subtraction, shifting, rotation and logical operations.

BLOCK DIAGRAM:
ARCHITECTURE:
TABLE OF PORTS:

PORT DIRECTION FUNCTION


in1 INPUT First input line of ALU
in2 INPUT Second input line of ALU
sel INPUT Line for selecting ALU function
out OUTPUT Output line of ALU

sel Operation
0 Addition

1 Subtraction

2 Left shift

3 Right shift

4 Rotate left

5 Rotate right

6 Logical or

7 Logical and

8 Logical not

9 Logical xor
CODE:

Design :-

module alu(input in1,in2,sel,output out);

wire [7:0]in1,in2; //Input lines


wire [3:0]sel; //select lines
reg [7:0]out; //output lines

initial out = 0;

always@(sel)
begin
case(sel)
//Arithmetic unit
0: out = in1 + in2; //case 0 : Add
1: out = in1 + ~in2 + 1; //case 1 : Sub
//Shifting unit
2: out = in1 << 1; //case 2 : Left shift
3: out = in1 >> 1; //case 3 : Right shift
4: begin //case 4 : Rotate left
out = in1 << 1;
out[0] = in1[7];
end
5: begin //case 5 : Rotate right
out = in1 >> 1;
out[7] = in1[0];
end
//Logical unit
6: out = in1 | in2; //case 6 : Logical or
7: out = in1 & in2; //case 7 : Logical and
8: out = !in1; //case 8 : Logical not
9: out = in1 ^ in2; //case 9 : Logical xor
default:$display("incorrect case");
endcase
end
endmodule
Testbench :-

module tb;
wire [7:0] out;
reg [7:0] in1,in2;
reg [3:0] sel;
reg [7:0] out_e;
reg [7:0]c=0; //for counting the number of fails

alu a(in1,in2,sel,out); //module instantiation

initial begin
repeat(100)
begin
for(int i=0;i<10;i++)
begin
sel = i;
in1 = $urandom;
in2 = $urandom;
#10
case(i) //CHECKER to compare obtained with expected
0: out_e = in1 + in2;
1: out_e = in1 + ~in2 + 1;
2: out_e = in1 << 1;
3: out_e = in1 >> 1;
4: begin
out_e = in1 << 1;
out_e[0] = in1[7];
end
5: begin
out_e = in1 >> 1;
out_e[7] = in1[0];
end
6: out_e = in1 | in2;
7: out_e = in1 & in2;
8: out_e = !in1;
9: out_e = in1 ^ in2;
endcase
if(out!=out_e) //comparison of obtained with expected
begin
c++; //counting the number of failed test cases
$display("sel=%0d :in1=%b and in2=%b\nexpected output=
%b\nobtained output=%b",sel,in1,in2,out_e,out);
end
end
end
if(c==0) //checking for no test fails
$display("all tests passed");
else
$display("Test failed %0d times",c);
end
endmodule

OUTPUT:

# KERNEL: all tests passed.


# KERNEL: Simulation has finished. There are no more test vectors to
simulate.

ANALYSIS:
100 test cases have been considered for each operation of the ALU with random
input values. Each value is compared with an expected output value to assure
the working of the design.

SUBMITTED BY
Ashish Suman
Hujebkhan Yusufkhan Pathan
Sai Kiran S
Vishnu S

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